tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
6 *
7 * HBI-0249A
8 */
9
10/dts-v1/;
11
12/ {
13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 i2c0 = &v2m_i2c_dvi;
29 i2c1 = &v2m_i2c_pcie;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a15";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <1>;
46 };
47
48/* A7s disabled till big.LITTLE patches are available...
49 cpu2: cpu@2 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0x100>;
53 };
54
55 cpu3: cpu@3 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a7";
58 reg = <0x101>;
59 };
60
61 cpu4: cpu@4 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a7";
64 reg = <0x102>;
65 };
66*/
67 };
68
69 memory@80000000 {
70 device_type = "memory";
71 reg = <0 0x80000000 0 0x40000000>;
72 };
73
74 wdt@2a490000 {
75 compatible = "arm,sp805", "arm,primecell";
76 reg = <0 0x2a490000 0 0x1000>;
77 interrupts = <98>;
78 clocks = <&oscclk6a>, <&oscclk6a>;
79 clock-names = "wdogclk", "apb_pclk";
80 };
81
82 hdlcd@2b000000 {
83 compatible = "arm,hdlcd";
84 reg = <0 0x2b000000 0 0x1000>;
85 interrupts = <0 85 4>;
86 clocks = <&oscclk5>;
87 clock-names = "pxlclk";
88 };
89
90 memory-controller@2b0a0000 {
91 compatible = "arm,pl341", "arm,primecell";
92 reg = <0 0x2b0a0000 0 0x1000>;
93 clocks = <&oscclk6a>;
94 clock-names = "apb_pclk";
95 };
96
97 gic: interrupt-controller@2c001000 {
98 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
101 interrupt-controller;
102 reg = <0 0x2c001000 0 0x1000>,
103 <0 0x2c002000 0 0x1000>,
104 <0 0x2c004000 0 0x2000>,
105 <0 0x2c006000 0 0x2000>;
106 interrupts = <1 9 0xf04>;
107 };
108
109 memory-controller@7ffd0000 {
110 compatible = "arm,pl354", "arm,primecell";
111 reg = <0 0x7ffd0000 0 0x1000>;
112 interrupts = <0 86 4>,
113 <0 87 4>;
114 clocks = <&oscclk6a>;
115 clock-names = "apb_pclk";
116 };
117
118 dma@7ff00000 {
119 compatible = "arm,pl330", "arm,primecell";
120 reg = <0 0x7ff00000 0 0x1000>;
121 interrupts = <0 92 4>,
122 <0 88 4>,
123 <0 89 4>,
124 <0 90 4>,
125 <0 91 4>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
128 };
129
130 timer {
131 compatible = "arm,armv7-timer";
132 interrupts = <1 13 0xf08>,
133 <1 14 0xf08>,
134 <1 11 0xf08>,
135 <1 10 0xf08>;
136 };
137
138 pmu {
139 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
140 interrupts = <0 68 4>,
141 <0 69 4>;
142 };
143
144 oscclk6a: oscclk6a {
145 /* Reference 24MHz clock */
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <24000000>;
149 clock-output-names = "oscclk6a";
150 };
151
152 dcc {
153 compatible = "arm,vexpress,config-bus";
154 arm,vexpress,config-bridge = <&v2m_sysreg>;
155
156 osc@0 {
157 /* A15 PLL 0 reference clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 0>;
160 freq-range = <17000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk0";
163 };
164
165 osc@1 {
166 /* A15 PLL 1 reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 1>;
169 freq-range = <17000000 50000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk1";
172 };
173
174 osc@2 {
175 /* A7 PLL 0 reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 2>;
178 freq-range = <17000000 50000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk2";
181 };
182
183 osc@3 {
184 /* A7 PLL 1 reference clock */
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 3>;
187 freq-range = <17000000 50000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk3";
190 };
191
192 osc@4 {
193 /* External AXI master clock */
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 4>;
196 freq-range = <20000000 40000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk4";
199 };
200
201 oscclk5: osc@5 {
202 /* HDLCD PLL reference clock */
203 compatible = "arm,vexpress-osc";
204 arm,vexpress-sysreg,func = <1 5>;
205 freq-range = <23750000 165000000>;
206 #clock-cells = <0>;
207 clock-output-names = "oscclk5";
208 };
209
210 smbclk: osc@6 {
211 /* Static memory controller clock */
212 compatible = "arm,vexpress-osc";
213 arm,vexpress-sysreg,func = <1 6>;
214 freq-range = <20000000 40000000>;
215 #clock-cells = <0>;
216 clock-output-names = "oscclk6";
217 };
218
219 osc@7 {
220 /* SYS PLL reference clock */
221 compatible = "arm,vexpress-osc";
222 arm,vexpress-sysreg,func = <1 7>;
223 freq-range = <17000000 50000000>;
224 #clock-cells = <0>;
225 clock-output-names = "oscclk7";
226 };
227
228 osc@8 {
229 /* DDR2 PLL reference clock */
230 compatible = "arm,vexpress-osc";
231 arm,vexpress-sysreg,func = <1 8>;
232 freq-range = <20000000 50000000>;
233 #clock-cells = <0>;
234 clock-output-names = "oscclk8";
235 };
236
237 volt@0 {
238 /* A15 CPU core voltage */
239 compatible = "arm,vexpress-volt";
240 arm,vexpress-sysreg,func = <2 0>;
241 regulator-name = "A15 Vcore";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1050000>;
244 regulator-always-on;
245 label = "A15 Vcore";
246 };
247
248 volt@1 {
249 /* A7 CPU core voltage */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 1>;
252 regulator-name = "A7 Vcore";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1050000>;
255 regulator-always-on;
256 label = "A7 Vcore";
257 };
258
259 amp@0 {
260 /* Total current for the two A15 cores */
261 compatible = "arm,vexpress-amp";
262 arm,vexpress-sysreg,func = <3 0>;
263 label = "A15 Icore";
264 };
265
266 amp@1 {
267 /* Total current for the three A7 cores */
268 compatible = "arm,vexpress-amp";
269 arm,vexpress-sysreg,func = <3 1>;
270 label = "A7 Icore";
271 };
272
273 temp@0 {
274 /* DCC internal temperature */
275 compatible = "arm,vexpress-temp";
276 arm,vexpress-sysreg,func = <4 0>;
277 label = "DCC";
278 };
279
280 power@0 {
281 /* Total power for the two A15 cores */
282 compatible = "arm,vexpress-power";
283 arm,vexpress-sysreg,func = <12 0>;
284 label = "A15 Pcore";
285 };
286 power@1 {
287 /* Total power for the three A7 cores */
288 compatible = "arm,vexpress-power";
289 arm,vexpress-sysreg,func = <12 1>;
290 label = "A7 Pcore";
291 };
292
293 energy@0 {
294 /* Total energy for the two A15 cores */
295 compatible = "arm,vexpress-energy";
296 arm,vexpress-sysreg,func = <13 0>;
297 label = "A15 Jcore";
298 };
299
300 energy@2 {
301 /* Total energy for the three A7 cores */
302 compatible = "arm,vexpress-energy";
303 arm,vexpress-sysreg,func = <13 2>;
304 label = "A7 Jcore";
305 };
306 };
307
308 smb {
309 compatible = "simple-bus";
310
311 #address-cells = <2>;
312 #size-cells = <1>;
313 ranges = <0 0 0 0x08000000 0x04000000>,
314 <1 0 0 0x14000000 0x04000000>,
315 <2 0 0 0x18000000 0x04000000>,
316 <3 0 0 0x1c000000 0x04000000>,
317 <4 0 0 0x0c000000 0x04000000>,
318 <5 0 0 0x10000000 0x04000000>;
319
320 #interrupt-cells = <1>;
321 interrupt-map-mask = <0 0 63>;
322 interrupt-map = <0 0 0 &gic 0 0 4>,
323 <0 0 1 &gic 0 1 4>,
324 <0 0 2 &gic 0 2 4>,
325 <0 0 3 &gic 0 3 4>,
326 <0 0 4 &gic 0 4 4>,
327 <0 0 5 &gic 0 5 4>,
328 <0 0 6 &gic 0 6 4>,
329 <0 0 7 &gic 0 7 4>,
330 <0 0 8 &gic 0 8 4>,
331 <0 0 9 &gic 0 9 4>,
332 <0 0 10 &gic 0 10 4>,
333 <0 0 11 &gic 0 11 4>,
334 <0 0 12 &gic 0 12 4>,
335 <0 0 13 &gic 0 13 4>,
336 <0 0 14 &gic 0 14 4>,
337 <0 0 15 &gic 0 15 4>,
338 <0 0 16 &gic 0 16 4>,
339 <0 0 17 &gic 0 17 4>,
340 <0 0 18 &gic 0 18 4>,
341 <0 0 19 &gic 0 19 4>,
342 <0 0 20 &gic 0 20 4>,
343 <0 0 21 &gic 0 21 4>,
344 <0 0 22 &gic 0 22 4>,
345 <0 0 23 &gic 0 23 4>,
346 <0 0 24 &gic 0 24 4>,
347 <0 0 25 &gic 0 25 4>,
348 <0 0 26 &gic 0 26 4>,
349 <0 0 27 &gic 0 27 4>,
350 <0 0 28 &gic 0 28 4>,
351 <0 0 29 &gic 0 29 4>,
352 <0 0 30 &gic 0 30 4>,
353 <0 0 31 &gic 0 31 4>,
354 <0 0 32 &gic 0 32 4>,
355 <0 0 33 &gic 0 33 4>,
356 <0 0 34 &gic 0 34 4>,
357 <0 0 35 &gic 0 35 4>,
358 <0 0 36 &gic 0 36 4>,
359 <0 0 37 &gic 0 37 4>,
360 <0 0 38 &gic 0 38 4>,
361 <0 0 39 &gic 0 39 4>,
362 <0 0 40 &gic 0 40 4>,
363 <0 0 41 &gic 0 41 4>,
364 <0 0 42 &gic 0 42 4>;
365
366 /include/ "vexpress-v2m-rs1.dtsi"
367 };
368};