Linux kernel mirror (for testing)
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linux
1/*
2 * OMAP GPIO handling defines and functions
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 *
6 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __ASM_ARCH_OMAP_GPIO_H
25#define __ASM_ARCH_OMAP_GPIO_H
26
27#include <linux/io.h>
28#include <linux/platform_device.h>
29#include <mach/irqs.h>
30
31#define OMAP1_MPUIO_BASE 0xfffb5000
32
33/*
34 * These are the omap15xx/16xx offsets. The omap7xx offset are
35 * OMAP_MPUIO_ / 2 offsets below.
36 */
37#define OMAP_MPUIO_INPUT_LATCH 0x00
38#define OMAP_MPUIO_OUTPUT 0x04
39#define OMAP_MPUIO_IO_CNTL 0x08
40#define OMAP_MPUIO_KBR_LATCH 0x10
41#define OMAP_MPUIO_KBC 0x14
42#define OMAP_MPUIO_GPIO_EVENT_MODE 0x18
43#define OMAP_MPUIO_GPIO_INT_EDGE 0x1c
44#define OMAP_MPUIO_KBD_INT 0x20
45#define OMAP_MPUIO_GPIO_INT 0x24
46#define OMAP_MPUIO_KBD_MASKIT 0x28
47#define OMAP_MPUIO_GPIO_MASKIT 0x2c
48#define OMAP_MPUIO_GPIO_DEBOUNCING 0x30
49#define OMAP_MPUIO_LATCH 0x34
50
51#define OMAP34XX_NR_GPIOS 6
52
53/*
54 * OMAP1510 GPIO registers
55 */
56#define OMAP1510_GPIO_DATA_INPUT 0x00
57#define OMAP1510_GPIO_DATA_OUTPUT 0x04
58#define OMAP1510_GPIO_DIR_CONTROL 0x08
59#define OMAP1510_GPIO_INT_CONTROL 0x0c
60#define OMAP1510_GPIO_INT_MASK 0x10
61#define OMAP1510_GPIO_INT_STATUS 0x14
62#define OMAP1510_GPIO_PIN_CONTROL 0x18
63
64#define OMAP1510_IH_GPIO_BASE 64
65
66/*
67 * OMAP1610 specific GPIO registers
68 */
69#define OMAP1610_GPIO_REVISION 0x0000
70#define OMAP1610_GPIO_SYSCONFIG 0x0010
71#define OMAP1610_GPIO_SYSSTATUS 0x0014
72#define OMAP1610_GPIO_IRQSTATUS1 0x0018
73#define OMAP1610_GPIO_IRQENABLE1 0x001c
74#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
75#define OMAP1610_GPIO_DATAIN 0x002c
76#define OMAP1610_GPIO_DATAOUT 0x0030
77#define OMAP1610_GPIO_DIRECTION 0x0034
78#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
79#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
80#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
81#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
82#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
83#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
84#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
85#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
86
87/*
88 * OMAP7XX specific GPIO registers
89 */
90#define OMAP7XX_GPIO_DATA_INPUT 0x00
91#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
92#define OMAP7XX_GPIO_DIR_CONTROL 0x08
93#define OMAP7XX_GPIO_INT_CONTROL 0x0c
94#define OMAP7XX_GPIO_INT_MASK 0x10
95#define OMAP7XX_GPIO_INT_STATUS 0x14
96
97/*
98 * omap2+ specific GPIO registers
99 */
100#define OMAP24XX_GPIO_REVISION 0x0000
101#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103#define OMAP24XX_GPIO_IRQENABLE2 0x002c
104#define OMAP24XX_GPIO_IRQENABLE1 0x001c
105#define OMAP24XX_GPIO_WAKE_EN 0x0020
106#define OMAP24XX_GPIO_CTRL 0x0030
107#define OMAP24XX_GPIO_OE 0x0034
108#define OMAP24XX_GPIO_DATAIN 0x0038
109#define OMAP24XX_GPIO_DATAOUT 0x003c
110#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
111#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
112#define OMAP24XX_GPIO_RISINGDETECT 0x0048
113#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
114#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
115#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
116#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
117#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
118#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
119#define OMAP24XX_GPIO_SETWKUENA 0x0084
120#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
121#define OMAP24XX_GPIO_SETDATAOUT 0x0094
122
123#define OMAP4_GPIO_REVISION 0x0000
124#define OMAP4_GPIO_EOI 0x0020
125#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
126#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
127#define OMAP4_GPIO_IRQSTATUS0 0x002c
128#define OMAP4_GPIO_IRQSTATUS1 0x0030
129#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
130#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
131#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
132#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
133#define OMAP4_GPIO_IRQWAKEN0 0x0044
134#define OMAP4_GPIO_IRQWAKEN1 0x0048
135#define OMAP4_GPIO_IRQENABLE1 0x011c
136#define OMAP4_GPIO_WAKE_EN 0x0120
137#define OMAP4_GPIO_IRQSTATUS2 0x0128
138#define OMAP4_GPIO_IRQENABLE2 0x012c
139#define OMAP4_GPIO_CTRL 0x0130
140#define OMAP4_GPIO_OE 0x0134
141#define OMAP4_GPIO_DATAIN 0x0138
142#define OMAP4_GPIO_DATAOUT 0x013c
143#define OMAP4_GPIO_LEVELDETECT0 0x0140
144#define OMAP4_GPIO_LEVELDETECT1 0x0144
145#define OMAP4_GPIO_RISINGDETECT 0x0148
146#define OMAP4_GPIO_FALLINGDETECT 0x014c
147#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
148#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
149#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
150#define OMAP4_GPIO_SETIRQENABLE1 0x0164
151#define OMAP4_GPIO_CLEARWKUENA 0x0180
152#define OMAP4_GPIO_SETWKUENA 0x0184
153#define OMAP4_GPIO_CLEARDATAOUT 0x0190
154#define OMAP4_GPIO_SETDATAOUT 0x0194
155
156#define OMAP_MAX_GPIO_LINES 192
157
158#define OMAP_MPUIO(nr) (OMAP_MAX_GPIO_LINES + (nr))
159#define OMAP_GPIO_IS_MPUIO(nr) ((nr) >= OMAP_MAX_GPIO_LINES)
160
161struct omap_gpio_dev_attr {
162 int bank_width; /* GPIO bank width */
163 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
164};
165
166struct omap_gpio_reg_offs {
167 u16 revision;
168 u16 direction;
169 u16 datain;
170 u16 dataout;
171 u16 set_dataout;
172 u16 clr_dataout;
173 u16 irqstatus;
174 u16 irqstatus2;
175 u16 irqstatus_raw0;
176 u16 irqstatus_raw1;
177 u16 irqenable;
178 u16 irqenable2;
179 u16 set_irqenable;
180 u16 clr_irqenable;
181 u16 debounce;
182 u16 debounce_en;
183 u16 ctrl;
184 u16 wkup_en;
185 u16 leveldetect0;
186 u16 leveldetect1;
187 u16 risingdetect;
188 u16 fallingdetect;
189 u16 irqctrl;
190 u16 edgectrl1;
191 u16 edgectrl2;
192 u16 pinctrl;
193
194 bool irqenable_inv;
195};
196
197struct omap_gpio_platform_data {
198 int bank_type;
199 int bank_width; /* GPIO bank width */
200 int bank_stride; /* Only needed for omap1 MPUIO */
201 bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
202 bool loses_context; /* whether the bank would ever lose context */
203 bool is_mpuio; /* whether the bank is of type MPUIO */
204 u32 non_wakeup_gpios;
205
206 struct omap_gpio_reg_offs *regs;
207
208 /* Return context loss count due to PM states changing */
209 int (*get_context_loss_count)(struct device *dev);
210};
211
212extern void omap2_gpio_prepare_for_idle(int off_mode);
213extern void omap2_gpio_resume_after_idle(void);
214extern void omap_set_gpio_debounce(int gpio, int enable);
215extern void omap_set_gpio_debounce_time(int gpio, int enable);
216
217#endif