Linux kernel mirror (for testing)
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linux
1/*
2 * SuperH FLCTL nand controller
3 *
4 * Copyright © 2008 Renesas Solutions Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef __SH_FLCTL_H__
21#define __SH_FLCTL_H__
22
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h>
26#include <linux/pm_qos.h>
27
28/* FLCTL registers */
29#define FLCMNCR(f) (f->reg + 0x0)
30#define FLCMDCR(f) (f->reg + 0x4)
31#define FLCMCDR(f) (f->reg + 0x8)
32#define FLADR(f) (f->reg + 0xC)
33#define FLADR2(f) (f->reg + 0x3C)
34#define FLDATAR(f) (f->reg + 0x10)
35#define FLDTCNTR(f) (f->reg + 0x14)
36#define FLINTDMACR(f) (f->reg + 0x18)
37#define FLBSYTMR(f) (f->reg + 0x1C)
38#define FLBSYCNT(f) (f->reg + 0x20)
39#define FLDTFIFO(f) (f->reg + 0x24)
40#define FLECFIFO(f) (f->reg + 0x28)
41#define FLTRCR(f) (f->reg + 0x2C)
42#define FLHOLDCR(f) (f->reg + 0x38)
43#define FL4ECCRESULT0(f) (f->reg + 0x80)
44#define FL4ECCRESULT1(f) (f->reg + 0x84)
45#define FL4ECCRESULT2(f) (f->reg + 0x88)
46#define FL4ECCRESULT3(f) (f->reg + 0x8C)
47#define FL4ECCCR(f) (f->reg + 0x90)
48#define FL4ECCCNT(f) (f->reg + 0x94)
49#define FLERRADR(f) (f->reg + 0x98)
50
51/* FLCMNCR control bits */
52#define _4ECCCNTEN (0x1 << 24)
53#define _4ECCEN (0x1 << 23)
54#define _4ECCCORRECT (0x1 << 22)
55#define SHBUSSEL (0x1 << 20)
56#define SEL_16BIT (0x1 << 19)
57#define SNAND_E (0x1 << 18) /* SNAND (0=512 1=2048)*/
58#define QTSEL_E (0x1 << 17)
59#define ENDIAN (0x1 << 16) /* 1 = little endian */
60#define FCKSEL_E (0x1 << 15)
61#define ACM_SACCES_MODE (0x01 << 10)
62#define NANWF_E (0x1 << 9)
63#define SE_D (0x1 << 8) /* Spare area disable */
64#define CE1_ENABLE (0x1 << 4) /* Chip Enable 1 */
65#define CE0_ENABLE (0x1 << 3) /* Chip Enable 0 */
66#define TYPESEL_SET (0x1 << 0)
67
68/*
69 * Clock settings using the PULSEx registers from FLCMNCR
70 *
71 * Some hardware uses bits called PULSEx instead of FCKSEL_E and QTSEL_E
72 * to control the clock divider used between the High-Speed Peripheral Clock
73 * and the FLCTL internal clock. If so, use CLK_8_BIT_xxx for connecting 8 bit
74 * and CLK_16_BIT_xxx for connecting 16 bit bus bandwith NAND chips. For the 16
75 * bit version the divider is seperate for the pulse width of high and low
76 * signals.
77 */
78#define PULSE3 (0x1 << 27)
79#define PULSE2 (0x1 << 17)
80#define PULSE1 (0x1 << 15)
81#define PULSE0 (0x1 << 9)
82#define CLK_8B_0_5 PULSE1
83#define CLK_8B_1 0x0
84#define CLK_8B_1_5 (PULSE1 | PULSE2)
85#define CLK_8B_2 PULSE0
86#define CLK_8B_3 (PULSE0 | PULSE1 | PULSE2)
87#define CLK_8B_4 (PULSE0 | PULSE2)
88#define CLK_16B_6L_2H PULSE0
89#define CLK_16B_9L_3H (PULSE0 | PULSE1 | PULSE2)
90#define CLK_16B_12L_4H (PULSE0 | PULSE2)
91
92/* FLCMDCR control bits */
93#define ADRCNT2_E (0x1 << 31) /* 5byte address enable */
94#define ADRMD_E (0x1 << 26) /* Sector address access */
95#define CDSRC_E (0x1 << 25) /* Data buffer selection */
96#define DOSR_E (0x1 << 24) /* Status read check */
97#define SELRW (0x1 << 21) /* 0:read 1:write */
98#define DOADR_E (0x1 << 20) /* Address stage execute */
99#define ADRCNT_1 (0x00 << 18) /* Address data bytes: 1byte */
100#define ADRCNT_2 (0x01 << 18) /* Address data bytes: 2byte */
101#define ADRCNT_3 (0x02 << 18) /* Address data bytes: 3byte */
102#define ADRCNT_4 (0x03 << 18) /* Address data bytes: 4byte */
103#define DOCMD2_E (0x1 << 17) /* 2nd cmd stage execute */
104#define DOCMD1_E (0x1 << 16) /* 1st cmd stage execute */
105
106/* FLINTDMACR control bits */
107#define ESTERINTE (0x1 << 24) /* ECC error interrupt enable */
108#define AC1CLR (0x1 << 19) /* ECC FIFO clear */
109#define AC0CLR (0x1 << 18) /* Data FIFO clear */
110#define ECERB (0x1 << 9) /* ECC error */
111#define STERB (0x1 << 8) /* Status error */
112#define STERINTE (0x1 << 4) /* Status error enable */
113
114/* FLTRCR control bits */
115#define TRSTRT (0x1 << 0) /* translation start */
116#define TREND (0x1 << 1) /* translation end */
117
118/*
119 * FLHOLDCR control bits
120 *
121 * HOLDEN: Bus Occupancy Enable (inverted)
122 * Enable this bit when the external bus might be used in between transfers.
123 * If not set and the bus gets used by other modules, a deadlock occurs.
124 */
125#define HOLDEN (0x1 << 0)
126
127/* FL4ECCCR control bits */
128#define _4ECCFA (0x1 << 2) /* 4 symbols correct fault */
129#define _4ECCEND (0x1 << 1) /* 4 symbols end */
130#define _4ECCEXST (0x1 << 0) /* 4 symbols exist */
131
132#define LOOP_TIMEOUT_MAX 0x00010000
133
134enum flctl_ecc_res_t {
135 FL_SUCCESS,
136 FL_REPAIRABLE,
137 FL_ERROR,
138 FL_TIMEOUT
139};
140
141struct sh_flctl {
142 struct mtd_info mtd;
143 struct nand_chip chip;
144 struct platform_device *pdev;
145 struct dev_pm_qos_request pm_qos;
146 void __iomem *reg;
147
148 uint8_t done_buff[2048 + 64]; /* max size 2048 + 64 */
149 int read_bytes;
150 int index;
151 int seqin_column; /* column in SEQIN cmd */
152 int seqin_page_addr; /* page_addr in SEQIN cmd */
153 uint32_t seqin_read_cmd; /* read cmd in SEQIN cmd */
154 int erase1_page_addr; /* page_addr in ERASE1 cmd */
155 uint32_t erase_ADRCNT; /* bits of FLCMDCR in ERASE1 cmd */
156 uint32_t rw_ADRCNT; /* bits of FLCMDCR in READ WRITE cmd */
157 uint32_t flcmncr_base; /* base value of FLCMNCR */
158 uint32_t flintdmacr_base; /* irq enable bits */
159
160 unsigned page_size:1; /* NAND page size (0 = 512, 1 = 2048) */
161 unsigned hwecc:1; /* Hardware ECC (0 = disabled, 1 = enabled) */
162 unsigned holden:1; /* Hardware has FLHOLDCR and HOLDEN is set */
163 unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
164};
165
166struct sh_flctl_platform_data {
167 struct mtd_partition *parts;
168 int nr_parts;
169 unsigned long flcmncr_val;
170
171 unsigned has_hwecc:1;
172 unsigned use_holden:1;
173};
174
175static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
176{
177 return container_of(mtdinfo, struct sh_flctl, mtd);
178}
179
180#endif /* __SH_FLCTL_H__ */