tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / palmas.h
at v3.7 111 kB view raw
1/* 2 * TI Palmas 3 * 4 * Copyright 2011 Texas Instruments Inc. 5 * 6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 */ 14 15#ifndef __LINUX_MFD_PALMAS_H 16#define __LINUX_MFD_PALMAS_H 17 18#include <linux/usb/otg.h> 19#include <linux/leds.h> 20#include <linux/regmap.h> 21#include <linux/regulator/driver.h> 22 23#define PALMAS_NUM_CLIENTS 3 24 25struct palmas_pmic; 26struct palmas_gpadc; 27struct palmas_resource; 28struct palmas_usb; 29 30struct palmas { 31 struct device *dev; 32 33 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS]; 34 struct regmap *regmap[PALMAS_NUM_CLIENTS]; 35 36 /* Stored chip id */ 37 int id; 38 39 /* IRQ Data */ 40 int irq; 41 u32 irq_mask; 42 struct mutex irq_lock; 43 struct regmap_irq_chip_data *irq_data; 44 45 /* Child Devices */ 46 struct palmas_pmic *pmic; 47 struct palmas_gpadc *gpadc; 48 struct palmas_resource *resource; 49 struct palmas_usb *usb; 50 51 /* GPIO MUXing */ 52 u8 gpio_muxed; 53 u8 led_muxed; 54 u8 pwm_muxed; 55}; 56 57struct palmas_gpadc_platform_data { 58 /* Channel 3 current source is only enabled during conversion */ 59 int ch3_current; 60 61 /* Channel 0 current source can be used for battery detection. 62 * If used for battery detection this will cause a permanent current 63 * consumption depending on current level set here. 64 */ 65 int ch0_current; 66 67 /* default BAT_REMOVAL_DAT setting on device probe */ 68 int bat_removal; 69 70 /* Sets the START_POLARITY bit in the RT_CTRL register */ 71 int start_polarity; 72}; 73 74struct palmas_reg_init { 75 /* warm_rest controls the voltage levels after a warm reset 76 * 77 * 0: reload default values from OTP on warm reset 78 * 1: maintain voltage from VSEL on warm reset 79 */ 80 int warm_reset; 81 82 /* roof_floor controls whether the regulator uses the i2c style 83 * of DVS or uses the method where a GPIO or other control method is 84 * attached to the NSLEEP/ENABLE1/ENABLE2 pins 85 * 86 * For SMPS 87 * 88 * 0: i2c selection of voltage 89 * 1: pin selection of voltage. 90 * 91 * For LDO unused 92 */ 93 int roof_floor; 94 95 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in 96 * the data sheet. 97 * 98 * For SMPS 99 * 100 * 0: Off 101 * 1: AUTO 102 * 2: ECO 103 * 3: Forced PWM 104 * 105 * For LDO 106 * 107 * 0: Off 108 * 1: On 109 */ 110 int mode_sleep; 111 112 /* tstep is the timestep loaded to the TSTEP register 113 * 114 * For SMPS 115 * 116 * 0: Jump (no slope control) 117 * 1: 10mV/us 118 * 2: 5mV/us 119 * 3: 2.5mV/us 120 * 121 * For LDO unused 122 */ 123 int tstep; 124 125 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 126 * register. Set this is the default voltage set in OTP needs 127 * to be overridden. 128 */ 129 u8 vsel; 130 131}; 132 133enum palmas_regulators { 134 /* SMPS regulators */ 135 PALMAS_REG_SMPS12, 136 PALMAS_REG_SMPS123, 137 PALMAS_REG_SMPS3, 138 PALMAS_REG_SMPS45, 139 PALMAS_REG_SMPS457, 140 PALMAS_REG_SMPS6, 141 PALMAS_REG_SMPS7, 142 PALMAS_REG_SMPS8, 143 PALMAS_REG_SMPS9, 144 PALMAS_REG_SMPS10, 145 /* LDO regulators */ 146 PALMAS_REG_LDO1, 147 PALMAS_REG_LDO2, 148 PALMAS_REG_LDO3, 149 PALMAS_REG_LDO4, 150 PALMAS_REG_LDO5, 151 PALMAS_REG_LDO6, 152 PALMAS_REG_LDO7, 153 PALMAS_REG_LDO8, 154 PALMAS_REG_LDO9, 155 PALMAS_REG_LDOLN, 156 PALMAS_REG_LDOUSB, 157 /* Total number of regulators */ 158 PALMAS_NUM_REGS, 159}; 160 161struct palmas_pmic_platform_data { 162 /* An array of pointers to regulator init data indexed by regulator 163 * ID 164 */ 165 struct regulator_init_data *reg_data[PALMAS_NUM_REGS]; 166 167 /* An array of pointers to structures containing sleep mode and DVS 168 * configuration for regulators indexed by ID 169 */ 170 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS]; 171 172 /* use LDO6 for vibrator control */ 173 int ldo6_vibrator; 174}; 175 176struct palmas_usb_platform_data { 177 /* Set this if platform wishes its own vbus control */ 178 int no_control_vbus; 179 180 /* Do we enable the wakeup comparator on probe */ 181 int wakeup; 182}; 183 184struct palmas_resource_platform_data { 185 int regen1_mode_sleep; 186 int regen2_mode_sleep; 187 int sysen1_mode_sleep; 188 int sysen2_mode_sleep; 189 190 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */ 191 u8 nsleep_res; 192 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */ 193 u8 nsleep_smps; 194 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */ 195 u8 nsleep_ldo1; 196 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */ 197 u8 nsleep_ldo2; 198 199 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */ 200 u8 enable1_res; 201 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */ 202 u8 enable1_smps; 203 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */ 204 u8 enable1_ldo1; 205 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */ 206 u8 enable1_ldo2; 207 208 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */ 209 u8 enable2_res; 210 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */ 211 u8 enable2_smps; 212 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */ 213 u8 enable2_ldo1; 214 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */ 215 u8 enable2_ldo2; 216}; 217 218struct palmas_clk_platform_data { 219 int clk32kg_mode_sleep; 220 int clk32kgaudio_mode_sleep; 221}; 222 223struct palmas_platform_data { 224 int gpio_base; 225 226 /* bit value to be loaded to the POWER_CTRL register */ 227 u8 power_ctrl; 228 229 /* 230 * boolean to select if we want to configure muxing here 231 * then the two value to load into the registers if true 232 */ 233 int mux_from_pdata; 234 u8 pad1, pad2; 235 236 struct palmas_pmic_platform_data *pmic_pdata; 237 struct palmas_gpadc_platform_data *gpadc_pdata; 238 struct palmas_usb_platform_data *usb_pdata; 239 struct palmas_resource_platform_data *resource_pdata; 240 struct palmas_clk_platform_data *clk_pdata; 241}; 242 243struct palmas_gpadc_calibration { 244 s32 gain; 245 s32 gain_error; 246 s32 offset_error; 247}; 248 249struct palmas_gpadc { 250 struct device *dev; 251 struct palmas *palmas; 252 253 int ch3_current; 254 int ch0_current; 255 256 int gpadc_force; 257 258 int bat_removal; 259 260 struct mutex reading_lock; 261 struct completion irq_complete; 262 263 int eoc_sw_irq; 264 265 struct palmas_gpadc_calibration *palmas_cal_tbl; 266 267 int conv0_channel; 268 int conv1_channel; 269 int rt_channel; 270}; 271 272struct palmas_gpadc_result { 273 s32 raw_code; 274 s32 corrected_code; 275 s32 result; 276}; 277 278#define PALMAS_MAX_CHANNELS 16 279 280/* Define the palmas IRQ numbers */ 281enum palmas_irqs { 282 /* INT1 registers */ 283 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ, 284 PALMAS_PWRON_IRQ, 285 PALMAS_LONG_PRESS_KEY_IRQ, 286 PALMAS_RPWRON_IRQ, 287 PALMAS_PWRDOWN_IRQ, 288 PALMAS_HOTDIE_IRQ, 289 PALMAS_VSYS_MON_IRQ, 290 PALMAS_VBAT_MON_IRQ, 291 /* INT2 registers */ 292 PALMAS_RTC_ALARM_IRQ, 293 PALMAS_RTC_TIMER_IRQ, 294 PALMAS_WDT_IRQ, 295 PALMAS_BATREMOVAL_IRQ, 296 PALMAS_RESET_IN_IRQ, 297 PALMAS_FBI_BB_IRQ, 298 PALMAS_SHORT_IRQ, 299 PALMAS_VAC_ACOK_IRQ, 300 /* INT3 registers */ 301 PALMAS_GPADC_AUTO_0_IRQ, 302 PALMAS_GPADC_AUTO_1_IRQ, 303 PALMAS_GPADC_EOC_SW_IRQ, 304 PALMAS_GPADC_EOC_RT_IRQ, 305 PALMAS_ID_OTG_IRQ, 306 PALMAS_ID_IRQ, 307 PALMAS_VBUS_OTG_IRQ, 308 PALMAS_VBUS_IRQ, 309 /* INT4 registers */ 310 PALMAS_GPIO_0_IRQ, 311 PALMAS_GPIO_1_IRQ, 312 PALMAS_GPIO_2_IRQ, 313 PALMAS_GPIO_3_IRQ, 314 PALMAS_GPIO_4_IRQ, 315 PALMAS_GPIO_5_IRQ, 316 PALMAS_GPIO_6_IRQ, 317 PALMAS_GPIO_7_IRQ, 318 /* Total Number IRQs */ 319 PALMAS_NUM_IRQ, 320}; 321 322struct palmas_pmic { 323 struct palmas *palmas; 324 struct device *dev; 325 struct regulator_desc desc[PALMAS_NUM_REGS]; 326 struct regulator_dev *rdev[PALMAS_NUM_REGS]; 327 struct mutex mutex; 328 329 int smps123; 330 int smps457; 331 332 int range[PALMAS_REG_SMPS10]; 333}; 334 335struct palmas_resource { 336 struct palmas *palmas; 337 struct device *dev; 338}; 339 340struct palmas_usb { 341 struct palmas *palmas; 342 struct device *dev; 343 344 /* for vbus reporting with irqs disabled */ 345 spinlock_t lock; 346 347 struct regulator *vbus_reg; 348 349 /* used to set vbus, in atomic path */ 350 struct work_struct set_vbus_work; 351 352 int irq1; 353 int irq2; 354 int irq3; 355 int irq4; 356 357 int vbus_enable; 358 359 u8 linkstat; 360}; 361 362#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator) 363 364enum usb_irq_events { 365 /* Wakeup events from INT3 */ 366 PALMAS_USB_ID_WAKEPUP, 367 PALMAS_USB_VBUS_WAKEUP, 368 369 /* ID_OTG_EVENTS */ 370 PALMAS_USB_ID_GND, 371 N_PALMAS_USB_ID_GND, 372 PALMAS_USB_ID_C, 373 N_PALMAS_USB_ID_C, 374 PALMAS_USB_ID_B, 375 N_PALMAS_USB_ID_B, 376 PALMAS_USB_ID_A, 377 N_PALMAS_USB_ID_A, 378 PALMAS_USB_ID_FLOAT, 379 N_PALMAS_USB_ID_FLOAT, 380 381 /* VBUS_OTG_EVENTS */ 382 PALMAS_USB_VB_SESS_END, 383 N_PALMAS_USB_VB_SESS_END, 384 PALMAS_USB_VB_SESS_VLD, 385 N_PALMAS_USB_VB_SESS_VLD, 386 PALMAS_USB_VA_SESS_VLD, 387 N_PALMAS_USB_VA_SESS_VLD, 388 PALMAS_USB_VA_VBUS_VLD, 389 N_PALMAS_USB_VA_VBUS_VLD, 390 PALMAS_USB_VADP_SNS, 391 N_PALMAS_USB_VADP_SNS, 392 PALMAS_USB_VADP_PRB, 393 N_PALMAS_USB_VADP_PRB, 394 PALMAS_USB_VOTG_SESS_VLD, 395 N_PALMAS_USB_VOTG_SESS_VLD, 396}; 397 398/* defines so we can store the mux settings */ 399#define PALMAS_GPIO_0_MUXED (1 << 0) 400#define PALMAS_GPIO_1_MUXED (1 << 1) 401#define PALMAS_GPIO_2_MUXED (1 << 2) 402#define PALMAS_GPIO_3_MUXED (1 << 3) 403#define PALMAS_GPIO_4_MUXED (1 << 4) 404#define PALMAS_GPIO_5_MUXED (1 << 5) 405#define PALMAS_GPIO_6_MUXED (1 << 6) 406#define PALMAS_GPIO_7_MUXED (1 << 7) 407 408#define PALMAS_LED1_MUXED (1 << 0) 409#define PALMAS_LED2_MUXED (1 << 1) 410 411#define PALMAS_PWM1_MUXED (1 << 0) 412#define PALMAS_PWM2_MUXED (1 << 1) 413 414/* helper macro to get correct slave number */ 415#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1) 416#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y) 417 418/* Base addresses of IP blocks in Palmas */ 419#define PALMAS_SMPS_DVS_BASE 0x20 420#define PALMAS_RTC_BASE 0x100 421#define PALMAS_VALIDITY_BASE 0x118 422#define PALMAS_SMPS_BASE 0x120 423#define PALMAS_LDO_BASE 0x150 424#define PALMAS_DVFS_BASE 0x180 425#define PALMAS_PMU_CONTROL_BASE 0x1A0 426#define PALMAS_RESOURCE_BASE 0x1D4 427#define PALMAS_PU_PD_OD_BASE 0x1F4 428#define PALMAS_LED_BASE 0x200 429#define PALMAS_INTERRUPT_BASE 0x210 430#define PALMAS_USB_OTG_BASE 0x250 431#define PALMAS_VIBRATOR_BASE 0x270 432#define PALMAS_GPIO_BASE 0x280 433#define PALMAS_USB_BASE 0x290 434#define PALMAS_GPADC_BASE 0x2C0 435#define PALMAS_TRIM_GPADC_BASE 0x3CD 436 437/* Registers for function RTC */ 438#define PALMAS_SECONDS_REG 0x0 439#define PALMAS_MINUTES_REG 0x1 440#define PALMAS_HOURS_REG 0x2 441#define PALMAS_DAYS_REG 0x3 442#define PALMAS_MONTHS_REG 0x4 443#define PALMAS_YEARS_REG 0x5 444#define PALMAS_WEEKS_REG 0x6 445#define PALMAS_ALARM_SECONDS_REG 0x8 446#define PALMAS_ALARM_MINUTES_REG 0x9 447#define PALMAS_ALARM_HOURS_REG 0xA 448#define PALMAS_ALARM_DAYS_REG 0xB 449#define PALMAS_ALARM_MONTHS_REG 0xC 450#define PALMAS_ALARM_YEARS_REG 0xD 451#define PALMAS_RTC_CTRL_REG 0x10 452#define PALMAS_RTC_STATUS_REG 0x11 453#define PALMAS_RTC_INTERRUPTS_REG 0x12 454#define PALMAS_RTC_COMP_LSB_REG 0x13 455#define PALMAS_RTC_COMP_MSB_REG 0x14 456#define PALMAS_RTC_RES_PROG_REG 0x15 457#define PALMAS_RTC_RESET_STATUS_REG 0x16 458 459/* Bit definitions for SECONDS_REG */ 460#define PALMAS_SECONDS_REG_SEC1_MASK 0x70 461#define PALMAS_SECONDS_REG_SEC1_SHIFT 4 462#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f 463#define PALMAS_SECONDS_REG_SEC0_SHIFT 0 464 465/* Bit definitions for MINUTES_REG */ 466#define PALMAS_MINUTES_REG_MIN1_MASK 0x70 467#define PALMAS_MINUTES_REG_MIN1_SHIFT 4 468#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f 469#define PALMAS_MINUTES_REG_MIN0_SHIFT 0 470 471/* Bit definitions for HOURS_REG */ 472#define PALMAS_HOURS_REG_PM_NAM 0x80 473#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7 474#define PALMAS_HOURS_REG_HOUR1_MASK 0x30 475#define PALMAS_HOURS_REG_HOUR1_SHIFT 4 476#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f 477#define PALMAS_HOURS_REG_HOUR0_SHIFT 0 478 479/* Bit definitions for DAYS_REG */ 480#define PALMAS_DAYS_REG_DAY1_MASK 0x30 481#define PALMAS_DAYS_REG_DAY1_SHIFT 4 482#define PALMAS_DAYS_REG_DAY0_MASK 0x0f 483#define PALMAS_DAYS_REG_DAY0_SHIFT 0 484 485/* Bit definitions for MONTHS_REG */ 486#define PALMAS_MONTHS_REG_MONTH1 0x10 487#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4 488#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f 489#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0 490 491/* Bit definitions for YEARS_REG */ 492#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0 493#define PALMAS_YEARS_REG_YEAR1_SHIFT 4 494#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f 495#define PALMAS_YEARS_REG_YEAR0_SHIFT 0 496 497/* Bit definitions for WEEKS_REG */ 498#define PALMAS_WEEKS_REG_WEEK_MASK 0x07 499#define PALMAS_WEEKS_REG_WEEK_SHIFT 0 500 501/* Bit definitions for ALARM_SECONDS_REG */ 502#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70 503#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4 504#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f 505#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0 506 507/* Bit definitions for ALARM_MINUTES_REG */ 508#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70 509#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4 510#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f 511#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0 512 513/* Bit definitions for ALARM_HOURS_REG */ 514#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80 515#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7 516#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30 517#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4 518#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f 519#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0 520 521/* Bit definitions for ALARM_DAYS_REG */ 522#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30 523#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4 524#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f 525#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0 526 527/* Bit definitions for ALARM_MONTHS_REG */ 528#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10 529#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4 530#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f 531#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0 532 533/* Bit definitions for ALARM_YEARS_REG */ 534#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0 535#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4 536#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f 537#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0 538 539/* Bit definitions for RTC_CTRL_REG */ 540#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80 541#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7 542#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40 543#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6 544#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20 545#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5 546#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10 547#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4 548#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08 549#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3 550#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04 551#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2 552#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02 553#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1 554#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01 555#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0 556 557/* Bit definitions for RTC_STATUS_REG */ 558#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80 559#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7 560#define PALMAS_RTC_STATUS_REG_ALARM 0x40 561#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6 562#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20 563#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5 564#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10 565#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4 566#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08 567#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3 568#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04 569#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2 570#define PALMAS_RTC_STATUS_REG_RUN 0x02 571#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1 572 573/* Bit definitions for RTC_INTERRUPTS_REG */ 574#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10 575#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4 576#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08 577#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3 578#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04 579#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2 580#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03 581#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0 582 583/* Bit definitions for RTC_COMP_LSB_REG */ 584#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff 585#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0 586 587/* Bit definitions for RTC_COMP_MSB_REG */ 588#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff 589#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0 590 591/* Bit definitions for RTC_RES_PROG_REG */ 592#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f 593#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0 594 595/* Bit definitions for RTC_RESET_STATUS_REG */ 596#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01 597#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0 598 599/* Registers for function BACKUP */ 600#define PALMAS_BACKUP0 0x0 601#define PALMAS_BACKUP1 0x1 602#define PALMAS_BACKUP2 0x2 603#define PALMAS_BACKUP3 0x3 604#define PALMAS_BACKUP4 0x4 605#define PALMAS_BACKUP5 0x5 606#define PALMAS_BACKUP6 0x6 607#define PALMAS_BACKUP7 0x7 608 609/* Bit definitions for BACKUP0 */ 610#define PALMAS_BACKUP0_BACKUP_MASK 0xff 611#define PALMAS_BACKUP0_BACKUP_SHIFT 0 612 613/* Bit definitions for BACKUP1 */ 614#define PALMAS_BACKUP1_BACKUP_MASK 0xff 615#define PALMAS_BACKUP1_BACKUP_SHIFT 0 616 617/* Bit definitions for BACKUP2 */ 618#define PALMAS_BACKUP2_BACKUP_MASK 0xff 619#define PALMAS_BACKUP2_BACKUP_SHIFT 0 620 621/* Bit definitions for BACKUP3 */ 622#define PALMAS_BACKUP3_BACKUP_MASK 0xff 623#define PALMAS_BACKUP3_BACKUP_SHIFT 0 624 625/* Bit definitions for BACKUP4 */ 626#define PALMAS_BACKUP4_BACKUP_MASK 0xff 627#define PALMAS_BACKUP4_BACKUP_SHIFT 0 628 629/* Bit definitions for BACKUP5 */ 630#define PALMAS_BACKUP5_BACKUP_MASK 0xff 631#define PALMAS_BACKUP5_BACKUP_SHIFT 0 632 633/* Bit definitions for BACKUP6 */ 634#define PALMAS_BACKUP6_BACKUP_MASK 0xff 635#define PALMAS_BACKUP6_BACKUP_SHIFT 0 636 637/* Bit definitions for BACKUP7 */ 638#define PALMAS_BACKUP7_BACKUP_MASK 0xff 639#define PALMAS_BACKUP7_BACKUP_SHIFT 0 640 641/* Registers for function SMPS */ 642#define PALMAS_SMPS12_CTRL 0x0 643#define PALMAS_SMPS12_TSTEP 0x1 644#define PALMAS_SMPS12_FORCE 0x2 645#define PALMAS_SMPS12_VOLTAGE 0x3 646#define PALMAS_SMPS3_CTRL 0x4 647#define PALMAS_SMPS3_VOLTAGE 0x7 648#define PALMAS_SMPS45_CTRL 0x8 649#define PALMAS_SMPS45_TSTEP 0x9 650#define PALMAS_SMPS45_FORCE 0xA 651#define PALMAS_SMPS45_VOLTAGE 0xB 652#define PALMAS_SMPS6_CTRL 0xC 653#define PALMAS_SMPS6_TSTEP 0xD 654#define PALMAS_SMPS6_FORCE 0xE 655#define PALMAS_SMPS6_VOLTAGE 0xF 656#define PALMAS_SMPS7_CTRL 0x10 657#define PALMAS_SMPS7_VOLTAGE 0x13 658#define PALMAS_SMPS8_CTRL 0x14 659#define PALMAS_SMPS8_TSTEP 0x15 660#define PALMAS_SMPS8_FORCE 0x16 661#define PALMAS_SMPS8_VOLTAGE 0x17 662#define PALMAS_SMPS9_CTRL 0x18 663#define PALMAS_SMPS9_VOLTAGE 0x1B 664#define PALMAS_SMPS10_CTRL 0x1C 665#define PALMAS_SMPS10_STATUS 0x1F 666#define PALMAS_SMPS_CTRL 0x24 667#define PALMAS_SMPS_PD_CTRL 0x25 668#define PALMAS_SMPS_DITHER_EN 0x26 669#define PALMAS_SMPS_THERMAL_EN 0x27 670#define PALMAS_SMPS_THERMAL_STATUS 0x28 671#define PALMAS_SMPS_SHORT_STATUS 0x29 672#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A 673#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B 674#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C 675 676/* Bit definitions for SMPS12_CTRL */ 677#define PALMAS_SMPS12_CTRL_WR_S 0x80 678#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7 679#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40 680#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6 681#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30 682#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4 683#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c 684#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2 685#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03 686#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0 687 688/* Bit definitions for SMPS12_TSTEP */ 689#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03 690#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0 691 692/* Bit definitions for SMPS12_FORCE */ 693#define PALMAS_SMPS12_FORCE_CMD 0x80 694#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7 695#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f 696#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0 697 698/* Bit definitions for SMPS12_VOLTAGE */ 699#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80 700#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7 701#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f 702#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0 703 704/* Bit definitions for SMPS3_CTRL */ 705#define PALMAS_SMPS3_CTRL_WR_S 0x80 706#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7 707#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30 708#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4 709#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c 710#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2 711#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 712#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0 713 714/* Bit definitions for SMPS3_VOLTAGE */ 715#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80 716#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7 717#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f 718#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0 719 720/* Bit definitions for SMPS45_CTRL */ 721#define PALMAS_SMPS45_CTRL_WR_S 0x80 722#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7 723#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40 724#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6 725#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30 726#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4 727#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c 728#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2 729#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03 730#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0 731 732/* Bit definitions for SMPS45_TSTEP */ 733#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03 734#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0 735 736/* Bit definitions for SMPS45_FORCE */ 737#define PALMAS_SMPS45_FORCE_CMD 0x80 738#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7 739#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f 740#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0 741 742/* Bit definitions for SMPS45_VOLTAGE */ 743#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80 744#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7 745#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f 746#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0 747 748/* Bit definitions for SMPS6_CTRL */ 749#define PALMAS_SMPS6_CTRL_WR_S 0x80 750#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7 751#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40 752#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6 753#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30 754#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4 755#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c 756#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2 757#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03 758#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0 759 760/* Bit definitions for SMPS6_TSTEP */ 761#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03 762#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0 763 764/* Bit definitions for SMPS6_FORCE */ 765#define PALMAS_SMPS6_FORCE_CMD 0x80 766#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7 767#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f 768#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0 769 770/* Bit definitions for SMPS6_VOLTAGE */ 771#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80 772#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7 773#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f 774#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0 775 776/* Bit definitions for SMPS7_CTRL */ 777#define PALMAS_SMPS7_CTRL_WR_S 0x80 778#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7 779#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30 780#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4 781#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c 782#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2 783#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03 784#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0 785 786/* Bit definitions for SMPS7_VOLTAGE */ 787#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80 788#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7 789#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f 790#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0 791 792/* Bit definitions for SMPS8_CTRL */ 793#define PALMAS_SMPS8_CTRL_WR_S 0x80 794#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7 795#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40 796#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6 797#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30 798#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4 799#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c 800#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2 801#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03 802#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0 803 804/* Bit definitions for SMPS8_TSTEP */ 805#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03 806#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0 807 808/* Bit definitions for SMPS8_FORCE */ 809#define PALMAS_SMPS8_FORCE_CMD 0x80 810#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7 811#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f 812#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0 813 814/* Bit definitions for SMPS8_VOLTAGE */ 815#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80 816#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7 817#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f 818#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0 819 820/* Bit definitions for SMPS9_CTRL */ 821#define PALMAS_SMPS9_CTRL_WR_S 0x80 822#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7 823#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30 824#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4 825#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c 826#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2 827#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03 828#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0 829 830/* Bit definitions for SMPS9_VOLTAGE */ 831#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80 832#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7 833#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f 834#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0 835 836/* Bit definitions for SMPS10_CTRL */ 837#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0 838#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4 839#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f 840#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0 841 842/* Bit definitions for SMPS10_STATUS */ 843#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f 844#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0 845 846/* Bit definitions for SMPS_CTRL */ 847#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20 848#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5 849#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10 850#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4 851#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c 852#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2 853#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03 854#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0 855 856/* Bit definitions for SMPS_PD_CTRL */ 857#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40 858#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6 859#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20 860#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5 861#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10 862#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4 863#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08 864#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3 865#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04 866#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2 867#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02 868#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1 869#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01 870#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0 871 872/* Bit definitions for SMPS_THERMAL_EN */ 873#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40 874#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6 875#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20 876#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5 877#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08 878#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3 879#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04 880#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2 881#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01 882#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0 883 884/* Bit definitions for SMPS_THERMAL_STATUS */ 885#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40 886#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6 887#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20 888#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5 889#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08 890#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3 891#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04 892#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2 893#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01 894#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0 895 896/* Bit definitions for SMPS_SHORT_STATUS */ 897#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80 898#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7 899#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40 900#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6 901#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20 902#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5 903#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10 904#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4 905#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08 906#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3 907#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04 908#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2 909#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02 910#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1 911#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01 912#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0 913 914/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ 915#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40 916#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6 917#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20 918#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5 919#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10 920#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4 921#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08 922#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3 923#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04 924#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2 925#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02 926#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1 927#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01 928#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0 929 930/* Bit definitions for SMPS_POWERGOOD_MASK1 */ 931#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80 932#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7 933#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40 934#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6 935#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20 936#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5 937#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10 938#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4 939#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08 940#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3 941#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04 942#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2 943#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02 944#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1 945#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01 946#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0 947 948/* Bit definitions for SMPS_POWERGOOD_MASK2 */ 949#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 950#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7 951#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04 952#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2 953#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02 954#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1 955#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01 956#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0 957 958/* Registers for function LDO */ 959#define PALMAS_LDO1_CTRL 0x0 960#define PALMAS_LDO1_VOLTAGE 0x1 961#define PALMAS_LDO2_CTRL 0x2 962#define PALMAS_LDO2_VOLTAGE 0x3 963#define PALMAS_LDO3_CTRL 0x4 964#define PALMAS_LDO3_VOLTAGE 0x5 965#define PALMAS_LDO4_CTRL 0x6 966#define PALMAS_LDO4_VOLTAGE 0x7 967#define PALMAS_LDO5_CTRL 0x8 968#define PALMAS_LDO5_VOLTAGE 0x9 969#define PALMAS_LDO6_CTRL 0xA 970#define PALMAS_LDO6_VOLTAGE 0xB 971#define PALMAS_LDO7_CTRL 0xC 972#define PALMAS_LDO7_VOLTAGE 0xD 973#define PALMAS_LDO8_CTRL 0xE 974#define PALMAS_LDO8_VOLTAGE 0xF 975#define PALMAS_LDO9_CTRL 0x10 976#define PALMAS_LDO9_VOLTAGE 0x11 977#define PALMAS_LDOLN_CTRL 0x12 978#define PALMAS_LDOLN_VOLTAGE 0x13 979#define PALMAS_LDOUSB_CTRL 0x14 980#define PALMAS_LDOUSB_VOLTAGE 0x15 981#define PALMAS_LDO_CTRL 0x1A 982#define PALMAS_LDO_PD_CTRL1 0x1B 983#define PALMAS_LDO_PD_CTRL2 0x1C 984#define PALMAS_LDO_SHORT_STATUS1 0x1D 985#define PALMAS_LDO_SHORT_STATUS2 0x1E 986 987/* Bit definitions for LDO1_CTRL */ 988#define PALMAS_LDO1_CTRL_WR_S 0x80 989#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7 990#define PALMAS_LDO1_CTRL_STATUS 0x10 991#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4 992#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04 993#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2 994#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01 995#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0 996 997/* Bit definitions for LDO1_VOLTAGE */ 998#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f 999#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0 1000 1001/* Bit definitions for LDO2_CTRL */ 1002#define PALMAS_LDO2_CTRL_WR_S 0x80 1003#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7 1004#define PALMAS_LDO2_CTRL_STATUS 0x10 1005#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4 1006#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04 1007#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2 1008#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01 1009#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0 1010 1011/* Bit definitions for LDO2_VOLTAGE */ 1012#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f 1013#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0 1014 1015/* Bit definitions for LDO3_CTRL */ 1016#define PALMAS_LDO3_CTRL_WR_S 0x80 1017#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7 1018#define PALMAS_LDO3_CTRL_STATUS 0x10 1019#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4 1020#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04 1021#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2 1022#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01 1023#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0 1024 1025/* Bit definitions for LDO3_VOLTAGE */ 1026#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f 1027#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0 1028 1029/* Bit definitions for LDO4_CTRL */ 1030#define PALMAS_LDO4_CTRL_WR_S 0x80 1031#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7 1032#define PALMAS_LDO4_CTRL_STATUS 0x10 1033#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4 1034#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04 1035#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2 1036#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01 1037#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0 1038 1039/* Bit definitions for LDO4_VOLTAGE */ 1040#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f 1041#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0 1042 1043/* Bit definitions for LDO5_CTRL */ 1044#define PALMAS_LDO5_CTRL_WR_S 0x80 1045#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7 1046#define PALMAS_LDO5_CTRL_STATUS 0x10 1047#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4 1048#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04 1049#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2 1050#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01 1051#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0 1052 1053/* Bit definitions for LDO5_VOLTAGE */ 1054#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f 1055#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0 1056 1057/* Bit definitions for LDO6_CTRL */ 1058#define PALMAS_LDO6_CTRL_WR_S 0x80 1059#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7 1060#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40 1061#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6 1062#define PALMAS_LDO6_CTRL_STATUS 0x10 1063#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4 1064#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04 1065#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2 1066#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01 1067#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0 1068 1069/* Bit definitions for LDO6_VOLTAGE */ 1070#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f 1071#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0 1072 1073/* Bit definitions for LDO7_CTRL */ 1074#define PALMAS_LDO7_CTRL_WR_S 0x80 1075#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7 1076#define PALMAS_LDO7_CTRL_STATUS 0x10 1077#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4 1078#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04 1079#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2 1080#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01 1081#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0 1082 1083/* Bit definitions for LDO7_VOLTAGE */ 1084#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f 1085#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0 1086 1087/* Bit definitions for LDO8_CTRL */ 1088#define PALMAS_LDO8_CTRL_WR_S 0x80 1089#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7 1090#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40 1091#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6 1092#define PALMAS_LDO8_CTRL_STATUS 0x10 1093#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4 1094#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04 1095#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2 1096#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01 1097#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0 1098 1099/* Bit definitions for LDO8_VOLTAGE */ 1100#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f 1101#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0 1102 1103/* Bit definitions for LDO9_CTRL */ 1104#define PALMAS_LDO9_CTRL_WR_S 0x80 1105#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7 1106#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40 1107#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6 1108#define PALMAS_LDO9_CTRL_STATUS 0x10 1109#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4 1110#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04 1111#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2 1112#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01 1113#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0 1114 1115/* Bit definitions for LDO9_VOLTAGE */ 1116#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f 1117#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0 1118 1119/* Bit definitions for LDOLN_CTRL */ 1120#define PALMAS_LDOLN_CTRL_WR_S 0x80 1121#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7 1122#define PALMAS_LDOLN_CTRL_STATUS 0x10 1123#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4 1124#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04 1125#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2 1126#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01 1127#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0 1128 1129/* Bit definitions for LDOLN_VOLTAGE */ 1130#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f 1131#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0 1132 1133/* Bit definitions for LDOUSB_CTRL */ 1134#define PALMAS_LDOUSB_CTRL_WR_S 0x80 1135#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7 1136#define PALMAS_LDOUSB_CTRL_STATUS 0x10 1137#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4 1138#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04 1139#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2 1140#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01 1141#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0 1142 1143/* Bit definitions for LDOUSB_VOLTAGE */ 1144#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f 1145#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0 1146 1147/* Bit definitions for LDO_CTRL */ 1148#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01 1149#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0 1150 1151/* Bit definitions for LDO_PD_CTRL1 */ 1152#define PALMAS_LDO_PD_CTRL1_LDO8 0x80 1153#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7 1154#define PALMAS_LDO_PD_CTRL1_LDO7 0x40 1155#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6 1156#define PALMAS_LDO_PD_CTRL1_LDO6 0x20 1157#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5 1158#define PALMAS_LDO_PD_CTRL1_LDO5 0x10 1159#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4 1160#define PALMAS_LDO_PD_CTRL1_LDO4 0x08 1161#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3 1162#define PALMAS_LDO_PD_CTRL1_LDO3 0x04 1163#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2 1164#define PALMAS_LDO_PD_CTRL1_LDO2 0x02 1165#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1 1166#define PALMAS_LDO_PD_CTRL1_LDO1 0x01 1167#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0 1168 1169/* Bit definitions for LDO_PD_CTRL2 */ 1170#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04 1171#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2 1172#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02 1173#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1 1174#define PALMAS_LDO_PD_CTRL2_LDO9 0x01 1175#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0 1176 1177/* Bit definitions for LDO_SHORT_STATUS1 */ 1178#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80 1179#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7 1180#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40 1181#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6 1182#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20 1183#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5 1184#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10 1185#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4 1186#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08 1187#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3 1188#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04 1189#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2 1190#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02 1191#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1 1192#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01 1193#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0 1194 1195/* Bit definitions for LDO_SHORT_STATUS2 */ 1196#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08 1197#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3 1198#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04 1199#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2 1200#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02 1201#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1 1202#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01 1203#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0 1204 1205/* Registers for function PMU_CONTROL */ 1206#define PALMAS_DEV_CTRL 0x0 1207#define PALMAS_POWER_CTRL 0x1 1208#define PALMAS_VSYS_LO 0x2 1209#define PALMAS_VSYS_MON 0x3 1210#define PALMAS_VBAT_MON 0x4 1211#define PALMAS_WATCHDOG 0x5 1212#define PALMAS_BOOT_STATUS 0x6 1213#define PALMAS_BATTERY_BOUNCE 0x7 1214#define PALMAS_BACKUP_BATTERY_CTRL 0x8 1215#define PALMAS_LONG_PRESS_KEY 0x9 1216#define PALMAS_OSC_THERM_CTRL 0xA 1217#define PALMAS_BATDEBOUNCING 0xB 1218#define PALMAS_SWOFF_HWRST 0xF 1219#define PALMAS_SWOFF_COLDRST 0x10 1220#define PALMAS_SWOFF_STATUS 0x11 1221#define PALMAS_PMU_CONFIG 0x12 1222#define PALMAS_SPARE 0x14 1223#define PALMAS_PMU_SECONDARY_INT 0x15 1224#define PALMAS_SW_REVISION 0x17 1225#define PALMAS_EXT_CHRG_CTRL 0x18 1226#define PALMAS_PMU_SECONDARY_INT2 0x19 1227 1228/* Bit definitions for DEV_CTRL */ 1229#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c 1230#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2 1231#define PALMAS_DEV_CTRL_SW_RST 0x02 1232#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1 1233#define PALMAS_DEV_CTRL_DEV_ON 0x01 1234#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0 1235 1236/* Bit definitions for POWER_CTRL */ 1237#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04 1238#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2 1239#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02 1240#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1 1241#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01 1242#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0 1243 1244/* Bit definitions for VSYS_LO */ 1245#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f 1246#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0 1247 1248/* Bit definitions for VSYS_MON */ 1249#define PALMAS_VSYS_MON_ENABLE 0x80 1250#define PALMAS_VSYS_MON_ENABLE_SHIFT 7 1251#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f 1252#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0 1253 1254/* Bit definitions for VBAT_MON */ 1255#define PALMAS_VBAT_MON_ENABLE 0x80 1256#define PALMAS_VBAT_MON_ENABLE_SHIFT 7 1257#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f 1258#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0 1259 1260/* Bit definitions for WATCHDOG */ 1261#define PALMAS_WATCHDOG_LOCK 0x20 1262#define PALMAS_WATCHDOG_LOCK_SHIFT 5 1263#define PALMAS_WATCHDOG_ENABLE 0x10 1264#define PALMAS_WATCHDOG_ENABLE_SHIFT 4 1265#define PALMAS_WATCHDOG_MODE 0x08 1266#define PALMAS_WATCHDOG_MODE_SHIFT 3 1267#define PALMAS_WATCHDOG_TIMER_MASK 0x07 1268#define PALMAS_WATCHDOG_TIMER_SHIFT 0 1269 1270/* Bit definitions for BOOT_STATUS */ 1271#define PALMAS_BOOT_STATUS_BOOT1 0x02 1272#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1 1273#define PALMAS_BOOT_STATUS_BOOT0 0x01 1274#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0 1275 1276/* Bit definitions for BATTERY_BOUNCE */ 1277#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f 1278#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0 1279 1280/* Bit definitions for BACKUP_BATTERY_CTRL */ 1281#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80 1282#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7 1283#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40 1284#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6 1285#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20 1286#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5 1287#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10 1288#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4 1289#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08 1290#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3 1291#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06 1292#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1 1293#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01 1294#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0 1295 1296/* Bit definitions for LONG_PRESS_KEY */ 1297#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80 1298#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7 1299#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10 1300#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4 1301#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c 1302#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2 1303#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03 1304#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0 1305 1306/* Bit definitions for OSC_THERM_CTRL */ 1307#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80 1308#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7 1309#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40 1310#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6 1311#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20 1312#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5 1313#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10 1314#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4 1315#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c 1316#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2 1317#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02 1318#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1 1319#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01 1320#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0 1321 1322/* Bit definitions for BATDEBOUNCING */ 1323#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80 1324#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7 1325#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78 1326#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3 1327#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07 1328#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0 1329 1330/* Bit definitions for SWOFF_HWRST */ 1331#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80 1332#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7 1333#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40 1334#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6 1335#define PALMAS_SWOFF_HWRST_WTD 0x20 1336#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5 1337#define PALMAS_SWOFF_HWRST_TSHUT 0x10 1338#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4 1339#define PALMAS_SWOFF_HWRST_RESET_IN 0x08 1340#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3 1341#define PALMAS_SWOFF_HWRST_SW_RST 0x04 1342#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2 1343#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02 1344#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1 1345#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01 1346#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0 1347 1348/* Bit definitions for SWOFF_COLDRST */ 1349#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80 1350#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7 1351#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40 1352#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6 1353#define PALMAS_SWOFF_COLDRST_WTD 0x20 1354#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5 1355#define PALMAS_SWOFF_COLDRST_TSHUT 0x10 1356#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4 1357#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08 1358#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3 1359#define PALMAS_SWOFF_COLDRST_SW_RST 0x04 1360#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2 1361#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02 1362#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1 1363#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01 1364#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0 1365 1366/* Bit definitions for SWOFF_STATUS */ 1367#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80 1368#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7 1369#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40 1370#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6 1371#define PALMAS_SWOFF_STATUS_WTD 0x20 1372#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5 1373#define PALMAS_SWOFF_STATUS_TSHUT 0x10 1374#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4 1375#define PALMAS_SWOFF_STATUS_RESET_IN 0x08 1376#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3 1377#define PALMAS_SWOFF_STATUS_SW_RST 0x04 1378#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2 1379#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02 1380#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1 1381#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01 1382#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0 1383 1384/* Bit definitions for PMU_CONFIG */ 1385#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40 1386#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6 1387#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30 1388#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4 1389#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c 1390#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2 1391#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02 1392#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1 1393#define PALMAS_PMU_CONFIG_AUTODEVON 0x01 1394#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0 1395 1396/* Bit definitions for SPARE */ 1397#define PALMAS_SPARE_SPARE_MASK 0xf8 1398#define PALMAS_SPARE_SPARE_SHIFT 3 1399#define PALMAS_SPARE_REGEN3_OD 0x04 1400#define PALMAS_SPARE_REGEN3_OD_SHIFT 2 1401#define PALMAS_SPARE_REGEN2_OD 0x02 1402#define PALMAS_SPARE_REGEN2_OD_SHIFT 1 1403#define PALMAS_SPARE_REGEN1_OD 0x01 1404#define PALMAS_SPARE_REGEN1_OD_SHIFT 0 1405 1406/* Bit definitions for PMU_SECONDARY_INT */ 1407#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80 1408#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7 1409#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40 1410#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6 1411#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20 1412#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5 1413#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10 1414#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4 1415#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08 1416#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3 1417#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04 1418#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2 1419#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02 1420#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1 1421#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01 1422#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0 1423 1424/* Bit definitions for SW_REVISION */ 1425#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff 1426#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0 1427 1428/* Bit definitions for EXT_CHRG_CTRL */ 1429#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80 1430#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7 1431#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40 1432#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6 1433#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08 1434#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3 1435#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04 1436#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2 1437#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02 1438#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1 1439#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01 1440#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0 1441 1442/* Bit definitions for PMU_SECONDARY_INT2 */ 1443#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20 1444#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5 1445#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10 1446#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4 1447#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02 1448#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1 1449#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01 1450#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0 1451 1452/* Registers for function RESOURCE */ 1453#define PALMAS_CLK32KG_CTRL 0x0 1454#define PALMAS_CLK32KGAUDIO_CTRL 0x1 1455#define PALMAS_REGEN1_CTRL 0x2 1456#define PALMAS_REGEN2_CTRL 0x3 1457#define PALMAS_SYSEN1_CTRL 0x4 1458#define PALMAS_SYSEN2_CTRL 0x5 1459#define PALMAS_NSLEEP_RES_ASSIGN 0x6 1460#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7 1461#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8 1462#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9 1463#define PALMAS_ENABLE1_RES_ASSIGN 0xA 1464#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB 1465#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC 1466#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD 1467#define PALMAS_ENABLE2_RES_ASSIGN 0xE 1468#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF 1469#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10 1470#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11 1471#define PALMAS_REGEN3_CTRL 0x12 1472 1473/* Bit definitions for CLK32KG_CTRL */ 1474#define PALMAS_CLK32KG_CTRL_STATUS 0x10 1475#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4 1476#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04 1477#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2 1478#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01 1479#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0 1480 1481/* Bit definitions for CLK32KGAUDIO_CTRL */ 1482#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10 1483#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4 1484#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08 1485#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3 1486#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04 1487#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2 1488#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01 1489#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0 1490 1491/* Bit definitions for REGEN1_CTRL */ 1492#define PALMAS_REGEN1_CTRL_STATUS 0x10 1493#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4 1494#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04 1495#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2 1496#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01 1497#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0 1498 1499/* Bit definitions for REGEN2_CTRL */ 1500#define PALMAS_REGEN2_CTRL_STATUS 0x10 1501#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4 1502#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04 1503#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2 1504#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01 1505#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0 1506 1507/* Bit definitions for SYSEN1_CTRL */ 1508#define PALMAS_SYSEN1_CTRL_STATUS 0x10 1509#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4 1510#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04 1511#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2 1512#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01 1513#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0 1514 1515/* Bit definitions for SYSEN2_CTRL */ 1516#define PALMAS_SYSEN2_CTRL_STATUS 0x10 1517#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4 1518#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04 1519#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2 1520#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01 1521#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0 1522 1523/* Bit definitions for NSLEEP_RES_ASSIGN */ 1524#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40 1525#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6 1526#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20 1527#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1528#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10 1529#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4 1530#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08 1531#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3 1532#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04 1533#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2 1534#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02 1535#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1 1536#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01 1537#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0 1538 1539/* Bit definitions for NSLEEP_SMPS_ASSIGN */ 1540#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80 1541#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7 1542#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40 1543#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6 1544#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20 1545#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5 1546#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10 1547#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4 1548#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08 1549#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3 1550#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04 1551#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2 1552#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02 1553#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1 1554#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01 1555#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0 1556 1557/* Bit definitions for NSLEEP_LDO_ASSIGN1 */ 1558#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80 1559#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7 1560#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40 1561#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6 1562#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20 1563#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5 1564#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10 1565#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4 1566#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08 1567#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3 1568#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04 1569#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2 1570#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02 1571#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1 1572#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01 1573#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0 1574 1575/* Bit definitions for NSLEEP_LDO_ASSIGN2 */ 1576#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04 1577#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2 1578#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02 1579#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1 1580#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01 1581#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0 1582 1583/* Bit definitions for ENABLE1_RES_ASSIGN */ 1584#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40 1585#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6 1586#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20 1587#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1588#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10 1589#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4 1590#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08 1591#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3 1592#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04 1593#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2 1594#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02 1595#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1 1596#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01 1597#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0 1598 1599/* Bit definitions for ENABLE1_SMPS_ASSIGN */ 1600#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80 1601#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7 1602#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40 1603#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6 1604#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20 1605#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5 1606#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10 1607#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4 1608#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08 1609#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3 1610#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04 1611#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2 1612#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02 1613#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1 1614#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01 1615#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0 1616 1617/* Bit definitions for ENABLE1_LDO_ASSIGN1 */ 1618#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80 1619#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7 1620#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40 1621#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6 1622#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20 1623#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5 1624#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10 1625#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4 1626#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08 1627#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3 1628#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04 1629#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2 1630#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02 1631#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1 1632#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01 1633#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0 1634 1635/* Bit definitions for ENABLE1_LDO_ASSIGN2 */ 1636#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04 1637#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2 1638#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02 1639#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1 1640#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01 1641#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0 1642 1643/* Bit definitions for ENABLE2_RES_ASSIGN */ 1644#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40 1645#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6 1646#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20 1647#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5 1648#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10 1649#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4 1650#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08 1651#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3 1652#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04 1653#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2 1654#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02 1655#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1 1656#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01 1657#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0 1658 1659/* Bit definitions for ENABLE2_SMPS_ASSIGN */ 1660#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80 1661#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7 1662#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40 1663#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6 1664#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20 1665#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5 1666#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10 1667#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4 1668#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08 1669#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3 1670#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04 1671#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2 1672#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02 1673#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1 1674#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01 1675#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0 1676 1677/* Bit definitions for ENABLE2_LDO_ASSIGN1 */ 1678#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80 1679#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7 1680#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40 1681#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6 1682#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20 1683#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5 1684#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10 1685#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4 1686#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08 1687#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3 1688#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04 1689#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2 1690#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02 1691#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1 1692#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01 1693#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0 1694 1695/* Bit definitions for ENABLE2_LDO_ASSIGN2 */ 1696#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04 1697#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2 1698#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02 1699#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1 1700#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01 1701#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0 1702 1703/* Bit definitions for REGEN3_CTRL */ 1704#define PALMAS_REGEN3_CTRL_STATUS 0x10 1705#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4 1706#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04 1707#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2 1708#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01 1709#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0 1710 1711/* Registers for function PAD_CONTROL */ 1712#define PALMAS_PU_PD_INPUT_CTRL1 0x0 1713#define PALMAS_PU_PD_INPUT_CTRL2 0x1 1714#define PALMAS_PU_PD_INPUT_CTRL3 0x2 1715#define PALMAS_OD_OUTPUT_CTRL 0x4 1716#define PALMAS_POLARITY_CTRL 0x5 1717#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6 1718#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7 1719#define PALMAS_I2C_SPI 0x8 1720#define PALMAS_PU_PD_INPUT_CTRL4 0x9 1721#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA 1722 1723/* Bit definitions for PU_PD_INPUT_CTRL1 */ 1724#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40 1725#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6 1726#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20 1727#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5 1728#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10 1729#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4 1730#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04 1731#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2 1732#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02 1733#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1 1734 1735/* Bit definitions for PU_PD_INPUT_CTRL2 */ 1736#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20 1737#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5 1738#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10 1739#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4 1740#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08 1741#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3 1742#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04 1743#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2 1744#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02 1745#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1 1746#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01 1747#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0 1748 1749/* Bit definitions for PU_PD_INPUT_CTRL3 */ 1750#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40 1751#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6 1752#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10 1753#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4 1754#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04 1755#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2 1756#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01 1757#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0 1758 1759/* Bit definitions for OD_OUTPUT_CTRL */ 1760#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80 1761#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7 1762#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40 1763#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6 1764#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20 1765#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5 1766#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08 1767#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3 1768 1769/* Bit definitions for POLARITY_CTRL */ 1770#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80 1771#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7 1772#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40 1773#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6 1774#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20 1775#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5 1776#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10 1777#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4 1778#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08 1779#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3 1780#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04 1781#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2 1782#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02 1783#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1 1784#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01 1785#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0 1786 1787/* Bit definitions for PRIMARY_SECONDARY_PAD1 */ 1788#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80 1789#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7 1790#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60 1791#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5 1792#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18 1793#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3 1794#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04 1795#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2 1796#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02 1797#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1 1798#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01 1799#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0 1800 1801/* Bit definitions for PRIMARY_SECONDARY_PAD2 */ 1802#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30 1803#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4 1804#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08 1805#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3 1806#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06 1807#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1 1808#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01 1809#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0 1810 1811/* Bit definitions for I2C_SPI */ 1812#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80 1813#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7 1814#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40 1815#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6 1816#define PALMAS_I2C_SPI_ID_I2C2 0x20 1817#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5 1818#define PALMAS_I2C_SPI_I2C_SPI 0x10 1819#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4 1820#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f 1821#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0 1822 1823/* Bit definitions for PU_PD_INPUT_CTRL4 */ 1824#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40 1825#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6 1826#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10 1827#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4 1828#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04 1829#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2 1830#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01 1831#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0 1832 1833/* Bit definitions for PRIMARY_SECONDARY_PAD3 */ 1834#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02 1835#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1 1836#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01 1837#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0 1838 1839/* Registers for function LED_PWM */ 1840#define PALMAS_LED_PERIOD_CTRL 0x0 1841#define PALMAS_LED_CTRL 0x1 1842#define PALMAS_PWM_CTRL1 0x2 1843#define PALMAS_PWM_CTRL2 0x3 1844 1845/* Bit definitions for LED_PERIOD_CTRL */ 1846#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38 1847#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3 1848#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07 1849#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0 1850 1851/* Bit definitions for LED_CTRL */ 1852#define PALMAS_LED_CTRL_LED_2_SEQ 0x20 1853#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5 1854#define PALMAS_LED_CTRL_LED_1_SEQ 0x10 1855#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4 1856#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c 1857#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2 1858#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03 1859#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0 1860 1861/* Bit definitions for PWM_CTRL1 */ 1862#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02 1863#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1 1864#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01 1865#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0 1866 1867/* Bit definitions for PWM_CTRL2 */ 1868#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff 1869#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0 1870 1871/* Registers for function INTERRUPT */ 1872#define PALMAS_INT1_STATUS 0x0 1873#define PALMAS_INT1_MASK 0x1 1874#define PALMAS_INT1_LINE_STATE 0x2 1875#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3 1876#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4 1877#define PALMAS_INT2_STATUS 0x5 1878#define PALMAS_INT2_MASK 0x6 1879#define PALMAS_INT2_LINE_STATE 0x7 1880#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8 1881#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9 1882#define PALMAS_INT3_STATUS 0xA 1883#define PALMAS_INT3_MASK 0xB 1884#define PALMAS_INT3_LINE_STATE 0xC 1885#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD 1886#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE 1887#define PALMAS_INT4_STATUS 0xF 1888#define PALMAS_INT4_MASK 0x10 1889#define PALMAS_INT4_LINE_STATE 0x11 1890#define PALMAS_INT4_EDGE_DETECT1 0x12 1891#define PALMAS_INT4_EDGE_DETECT2 0x13 1892#define PALMAS_INT_CTRL 0x14 1893 1894/* Bit definitions for INT1_STATUS */ 1895#define PALMAS_INT1_STATUS_VBAT_MON 0x80 1896#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7 1897#define PALMAS_INT1_STATUS_VSYS_MON 0x40 1898#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6 1899#define PALMAS_INT1_STATUS_HOTDIE 0x20 1900#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5 1901#define PALMAS_INT1_STATUS_PWRDOWN 0x10 1902#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4 1903#define PALMAS_INT1_STATUS_RPWRON 0x08 1904#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3 1905#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04 1906#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2 1907#define PALMAS_INT1_STATUS_PWRON 0x02 1908#define PALMAS_INT1_STATUS_PWRON_SHIFT 1 1909#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01 1910#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0 1911 1912/* Bit definitions for INT1_MASK */ 1913#define PALMAS_INT1_MASK_VBAT_MON 0x80 1914#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7 1915#define PALMAS_INT1_MASK_VSYS_MON 0x40 1916#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6 1917#define PALMAS_INT1_MASK_HOTDIE 0x20 1918#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5 1919#define PALMAS_INT1_MASK_PWRDOWN 0x10 1920#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4 1921#define PALMAS_INT1_MASK_RPWRON 0x08 1922#define PALMAS_INT1_MASK_RPWRON_SHIFT 3 1923#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04 1924#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2 1925#define PALMAS_INT1_MASK_PWRON 0x02 1926#define PALMAS_INT1_MASK_PWRON_SHIFT 1 1927#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01 1928#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0 1929 1930/* Bit definitions for INT1_LINE_STATE */ 1931#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80 1932#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7 1933#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40 1934#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6 1935#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20 1936#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5 1937#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10 1938#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4 1939#define PALMAS_INT1_LINE_STATE_RPWRON 0x08 1940#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3 1941#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 1942#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2 1943#define PALMAS_INT1_LINE_STATE_PWRON 0x02 1944#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1 1945#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01 1946#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0 1947 1948/* Bit definitions for INT2_STATUS */ 1949#define PALMAS_INT2_STATUS_VAC_ACOK 0x80 1950#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7 1951#define PALMAS_INT2_STATUS_SHORT 0x40 1952#define PALMAS_INT2_STATUS_SHORT_SHIFT 6 1953#define PALMAS_INT2_STATUS_FBI_BB 0x20 1954#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5 1955#define PALMAS_INT2_STATUS_RESET_IN 0x10 1956#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4 1957#define PALMAS_INT2_STATUS_BATREMOVAL 0x08 1958#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3 1959#define PALMAS_INT2_STATUS_WDT 0x04 1960#define PALMAS_INT2_STATUS_WDT_SHIFT 2 1961#define PALMAS_INT2_STATUS_RTC_TIMER 0x02 1962#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1 1963#define PALMAS_INT2_STATUS_RTC_ALARM 0x01 1964#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0 1965 1966/* Bit definitions for INT2_MASK */ 1967#define PALMAS_INT2_MASK_VAC_ACOK 0x80 1968#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7 1969#define PALMAS_INT2_MASK_SHORT 0x40 1970#define PALMAS_INT2_MASK_SHORT_SHIFT 6 1971#define PALMAS_INT2_MASK_FBI_BB 0x20 1972#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5 1973#define PALMAS_INT2_MASK_RESET_IN 0x10 1974#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4 1975#define PALMAS_INT2_MASK_BATREMOVAL 0x08 1976#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3 1977#define PALMAS_INT2_MASK_WDT 0x04 1978#define PALMAS_INT2_MASK_WDT_SHIFT 2 1979#define PALMAS_INT2_MASK_RTC_TIMER 0x02 1980#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1 1981#define PALMAS_INT2_MASK_RTC_ALARM 0x01 1982#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0 1983 1984/* Bit definitions for INT2_LINE_STATE */ 1985#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80 1986#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7 1987#define PALMAS_INT2_LINE_STATE_SHORT 0x40 1988#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6 1989#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20 1990#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5 1991#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10 1992#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4 1993#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08 1994#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3 1995#define PALMAS_INT2_LINE_STATE_WDT 0x04 1996#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2 1997#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02 1998#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1 1999#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01 2000#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0 2001 2002/* Bit definitions for INT3_STATUS */ 2003#define PALMAS_INT3_STATUS_VBUS 0x80 2004#define PALMAS_INT3_STATUS_VBUS_SHIFT 7 2005#define PALMAS_INT3_STATUS_VBUS_OTG 0x40 2006#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6 2007#define PALMAS_INT3_STATUS_ID 0x20 2008#define PALMAS_INT3_STATUS_ID_SHIFT 5 2009#define PALMAS_INT3_STATUS_ID_OTG 0x10 2010#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4 2011#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08 2012#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3 2013#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04 2014#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2 2015#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02 2016#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1 2017#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01 2018#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0 2019 2020/* Bit definitions for INT3_MASK */ 2021#define PALMAS_INT3_MASK_VBUS 0x80 2022#define PALMAS_INT3_MASK_VBUS_SHIFT 7 2023#define PALMAS_INT3_MASK_VBUS_OTG 0x40 2024#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6 2025#define PALMAS_INT3_MASK_ID 0x20 2026#define PALMAS_INT3_MASK_ID_SHIFT 5 2027#define PALMAS_INT3_MASK_ID_OTG 0x10 2028#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4 2029#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08 2030#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3 2031#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04 2032#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2 2033#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02 2034#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1 2035#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01 2036#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0 2037 2038/* Bit definitions for INT3_LINE_STATE */ 2039#define PALMAS_INT3_LINE_STATE_VBUS 0x80 2040#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7 2041#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40 2042#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6 2043#define PALMAS_INT3_LINE_STATE_ID 0x20 2044#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5 2045#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10 2046#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4 2047#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08 2048#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3 2049#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04 2050#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2 2051#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02 2052#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1 2053#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01 2054#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0 2055 2056/* Bit definitions for INT4_STATUS */ 2057#define PALMAS_INT4_STATUS_GPIO_7 0x80 2058#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7 2059#define PALMAS_INT4_STATUS_GPIO_6 0x40 2060#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6 2061#define PALMAS_INT4_STATUS_GPIO_5 0x20 2062#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5 2063#define PALMAS_INT4_STATUS_GPIO_4 0x10 2064#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4 2065#define PALMAS_INT4_STATUS_GPIO_3 0x08 2066#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3 2067#define PALMAS_INT4_STATUS_GPIO_2 0x04 2068#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2 2069#define PALMAS_INT4_STATUS_GPIO_1 0x02 2070#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1 2071#define PALMAS_INT4_STATUS_GPIO_0 0x01 2072#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0 2073 2074/* Bit definitions for INT4_MASK */ 2075#define PALMAS_INT4_MASK_GPIO_7 0x80 2076#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7 2077#define PALMAS_INT4_MASK_GPIO_6 0x40 2078#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6 2079#define PALMAS_INT4_MASK_GPIO_5 0x20 2080#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5 2081#define PALMAS_INT4_MASK_GPIO_4 0x10 2082#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4 2083#define PALMAS_INT4_MASK_GPIO_3 0x08 2084#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3 2085#define PALMAS_INT4_MASK_GPIO_2 0x04 2086#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2 2087#define PALMAS_INT4_MASK_GPIO_1 0x02 2088#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1 2089#define PALMAS_INT4_MASK_GPIO_0 0x01 2090#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0 2091 2092/* Bit definitions for INT4_LINE_STATE */ 2093#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80 2094#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7 2095#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40 2096#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6 2097#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20 2098#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5 2099#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10 2100#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4 2101#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08 2102#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3 2103#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04 2104#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2 2105#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02 2106#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1 2107#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01 2108#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0 2109 2110/* Bit definitions for INT4_EDGE_DETECT1 */ 2111#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 2112#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7 2113#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 2114#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6 2115#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 2116#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5 2117#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 2118#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4 2119#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 2120#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3 2121#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 2122#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2 2123#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 2124#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1 2125#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 2126#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0 2127 2128/* Bit definitions for INT4_EDGE_DETECT2 */ 2129#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80 2130#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7 2131#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40 2132#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6 2133#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 2134#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5 2135#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 2136#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4 2137#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 2138#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3 2139#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 2140#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2 2141#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 2142#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1 2143#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 2144#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0 2145 2146/* Bit definitions for INT_CTRL */ 2147#define PALMAS_INT_CTRL_INT_PENDING 0x04 2148#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2 2149#define PALMAS_INT_CTRL_INT_CLEAR 0x01 2150#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0 2151 2152/* Registers for function USB_OTG */ 2153#define PALMAS_USB_WAKEUP 0x3 2154#define PALMAS_USB_VBUS_CTRL_SET 0x4 2155#define PALMAS_USB_VBUS_CTRL_CLR 0x5 2156#define PALMAS_USB_ID_CTRL_SET 0x6 2157#define PALMAS_USB_ID_CTRL_CLEAR 0x7 2158#define PALMAS_USB_VBUS_INT_SRC 0x8 2159#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9 2160#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA 2161#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB 2162#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC 2163#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD 2164#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE 2165#define PALMAS_USB_ID_INT_SRC 0xF 2166#define PALMAS_USB_ID_INT_LATCH_SET 0x10 2167#define PALMAS_USB_ID_INT_LATCH_CLR 0x11 2168#define PALMAS_USB_ID_INT_EN_LO_SET 0x12 2169#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13 2170#define PALMAS_USB_ID_INT_EN_HI_SET 0x14 2171#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15 2172#define PALMAS_USB_OTG_ADP_CTRL 0x16 2173#define PALMAS_USB_OTG_ADP_HIGH 0x17 2174#define PALMAS_USB_OTG_ADP_LOW 0x18 2175#define PALMAS_USB_OTG_ADP_RISE 0x19 2176#define PALMAS_USB_OTG_REVISION 0x1A 2177 2178/* Bit definitions for USB_WAKEUP */ 2179#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01 2180#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0 2181 2182/* Bit definitions for USB_VBUS_CTRL_SET */ 2183#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80 2184#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7 2185#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20 2186#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5 2187#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10 2188#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4 2189#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08 2190#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3 2191#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04 2192#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2 2193 2194/* Bit definitions for USB_VBUS_CTRL_CLR */ 2195#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80 2196#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7 2197#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20 2198#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5 2199#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10 2200#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4 2201#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08 2202#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3 2203#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04 2204#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2 2205 2206/* Bit definitions for USB_ID_CTRL_SET */ 2207#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80 2208#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7 2209#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40 2210#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6 2211#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20 2212#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5 2213#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10 2214#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4 2215#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08 2216#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3 2217#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04 2218#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2 2219 2220/* Bit definitions for USB_ID_CTRL_CLEAR */ 2221#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80 2222#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7 2223#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40 2224#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6 2225#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20 2226#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5 2227#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10 2228#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4 2229#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08 2230#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3 2231#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04 2232#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2 2233 2234/* Bit definitions for USB_VBUS_INT_SRC */ 2235#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80 2236#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7 2237#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40 2238#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6 2239#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20 2240#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5 2241#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08 2242#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3 2243#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04 2244#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2 2245#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02 2246#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1 2247#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01 2248#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0 2249 2250/* Bit definitions for USB_VBUS_INT_LATCH_SET */ 2251#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80 2252#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7 2253#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40 2254#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6 2255#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20 2256#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5 2257#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10 2258#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4 2259#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08 2260#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3 2261#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04 2262#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2 2263#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02 2264#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1 2265#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01 2266#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0 2267 2268/* Bit definitions for USB_VBUS_INT_LATCH_CLR */ 2269#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80 2270#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7 2271#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40 2272#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6 2273#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20 2274#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5 2275#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10 2276#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4 2277#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08 2278#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3 2279#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04 2280#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2 2281#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02 2282#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1 2283#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01 2284#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0 2285 2286/* Bit definitions for USB_VBUS_INT_EN_LO_SET */ 2287#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80 2288#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7 2289#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40 2290#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6 2291#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20 2292#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5 2293#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08 2294#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3 2295#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04 2296#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2 2297#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02 2298#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1 2299#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01 2300#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0 2301 2302/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */ 2303#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80 2304#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7 2305#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40 2306#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6 2307#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20 2308#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5 2309#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08 2310#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3 2311#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04 2312#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2 2313#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02 2314#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1 2315#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01 2316#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0 2317 2318/* Bit definitions for USB_VBUS_INT_EN_HI_SET */ 2319#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80 2320#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7 2321#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40 2322#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6 2323#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20 2324#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5 2325#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10 2326#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4 2327#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08 2328#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3 2329#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04 2330#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2 2331#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02 2332#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1 2333#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01 2334#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0 2335 2336/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */ 2337#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80 2338#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7 2339#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40 2340#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6 2341#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20 2342#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5 2343#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10 2344#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4 2345#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08 2346#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3 2347#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04 2348#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2 2349#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02 2350#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1 2351#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01 2352#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0 2353 2354/* Bit definitions for USB_ID_INT_SRC */ 2355#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10 2356#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4 2357#define PALMAS_USB_ID_INT_SRC_ID_A 0x08 2358#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3 2359#define PALMAS_USB_ID_INT_SRC_ID_B 0x04 2360#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2 2361#define PALMAS_USB_ID_INT_SRC_ID_C 0x02 2362#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1 2363#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01 2364#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0 2365 2366/* Bit definitions for USB_ID_INT_LATCH_SET */ 2367#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10 2368#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4 2369#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08 2370#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3 2371#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04 2372#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2 2373#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02 2374#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1 2375#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01 2376#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0 2377 2378/* Bit definitions for USB_ID_INT_LATCH_CLR */ 2379#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10 2380#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4 2381#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08 2382#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3 2383#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04 2384#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2 2385#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02 2386#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1 2387#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01 2388#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0 2389 2390/* Bit definitions for USB_ID_INT_EN_LO_SET */ 2391#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10 2392#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4 2393#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08 2394#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3 2395#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04 2396#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2 2397#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02 2398#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1 2399#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01 2400#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0 2401 2402/* Bit definitions for USB_ID_INT_EN_LO_CLR */ 2403#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10 2404#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4 2405#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08 2406#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3 2407#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04 2408#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2 2409#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02 2410#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1 2411#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01 2412#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0 2413 2414/* Bit definitions for USB_ID_INT_EN_HI_SET */ 2415#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10 2416#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4 2417#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08 2418#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3 2419#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04 2420#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2 2421#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02 2422#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1 2423#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01 2424#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0 2425 2426/* Bit definitions for USB_ID_INT_EN_HI_CLR */ 2427#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10 2428#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4 2429#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08 2430#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3 2431#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04 2432#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2 2433#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02 2434#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1 2435#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01 2436#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0 2437 2438/* Bit definitions for USB_OTG_ADP_CTRL */ 2439#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04 2440#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2 2441#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03 2442#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0 2443 2444/* Bit definitions for USB_OTG_ADP_HIGH */ 2445#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff 2446#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0 2447 2448/* Bit definitions for USB_OTG_ADP_LOW */ 2449#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff 2450#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0 2451 2452/* Bit definitions for USB_OTG_ADP_RISE */ 2453#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff 2454#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0 2455 2456/* Bit definitions for USB_OTG_REVISION */ 2457#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01 2458#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0 2459 2460/* Registers for function VIBRATOR */ 2461#define PALMAS_VIBRA_CTRL 0x0 2462 2463/* Bit definitions for VIBRA_CTRL */ 2464#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06 2465#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1 2466#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01 2467#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0 2468 2469/* Registers for function GPIO */ 2470#define PALMAS_GPIO_DATA_IN 0x0 2471#define PALMAS_GPIO_DATA_DIR 0x1 2472#define PALMAS_GPIO_DATA_OUT 0x2 2473#define PALMAS_GPIO_DEBOUNCE_EN 0x3 2474#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4 2475#define PALMAS_GPIO_SET_DATA_OUT 0x5 2476#define PALMAS_PU_PD_GPIO_CTRL1 0x6 2477#define PALMAS_PU_PD_GPIO_CTRL2 0x7 2478#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8 2479 2480/* Bit definitions for GPIO_DATA_IN */ 2481#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80 2482#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7 2483#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40 2484#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6 2485#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20 2486#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5 2487#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10 2488#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4 2489#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08 2490#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3 2491#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04 2492#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2 2493#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02 2494#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1 2495#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01 2496#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0 2497 2498/* Bit definitions for GPIO_DATA_DIR */ 2499#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80 2500#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7 2501#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40 2502#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6 2503#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20 2504#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5 2505#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10 2506#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4 2507#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08 2508#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3 2509#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04 2510#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2 2511#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02 2512#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1 2513#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01 2514#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0 2515 2516/* Bit definitions for GPIO_DATA_OUT */ 2517#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80 2518#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7 2519#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40 2520#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6 2521#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20 2522#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5 2523#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10 2524#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4 2525#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08 2526#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3 2527#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04 2528#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2 2529#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02 2530#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1 2531#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01 2532#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0 2533 2534/* Bit definitions for GPIO_DEBOUNCE_EN */ 2535#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80 2536#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7 2537#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40 2538#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6 2539#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20 2540#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5 2541#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10 2542#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4 2543#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08 2544#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3 2545#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04 2546#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2 2547#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02 2548#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1 2549#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01 2550#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0 2551 2552/* Bit definitions for GPIO_CLEAR_DATA_OUT */ 2553#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80 2554#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7 2555#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40 2556#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6 2557#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20 2558#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5 2559#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10 2560#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4 2561#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08 2562#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3 2563#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04 2564#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2 2565#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02 2566#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1 2567#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01 2568#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0 2569 2570/* Bit definitions for GPIO_SET_DATA_OUT */ 2571#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80 2572#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7 2573#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40 2574#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6 2575#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20 2576#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5 2577#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10 2578#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4 2579#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08 2580#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3 2581#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04 2582#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2 2583#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02 2584#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1 2585#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01 2586#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0 2587 2588/* Bit definitions for PU_PD_GPIO_CTRL1 */ 2589#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40 2590#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6 2591#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20 2592#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5 2593#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10 2594#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4 2595#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08 2596#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3 2597#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04 2598#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2 2599#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01 2600#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0 2601 2602/* Bit definitions for PU_PD_GPIO_CTRL2 */ 2603#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40 2604#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6 2605#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20 2606#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5 2607#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10 2608#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4 2609#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08 2610#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3 2611#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04 2612#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2 2613#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02 2614#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1 2615#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01 2616#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0 2617 2618/* Bit definitions for OD_OUTPUT_GPIO_CTRL */ 2619#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20 2620#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5 2621#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04 2622#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2 2623#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02 2624#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1 2625 2626/* Registers for function GPADC */ 2627#define PALMAS_GPADC_CTRL1 0x0 2628#define PALMAS_GPADC_CTRL2 0x1 2629#define PALMAS_GPADC_RT_CTRL 0x2 2630#define PALMAS_GPADC_AUTO_CTRL 0x3 2631#define PALMAS_GPADC_STATUS 0x4 2632#define PALMAS_GPADC_RT_SELECT 0x5 2633#define PALMAS_GPADC_RT_CONV0_LSB 0x6 2634#define PALMAS_GPADC_RT_CONV0_MSB 0x7 2635#define PALMAS_GPADC_AUTO_SELECT 0x8 2636#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9 2637#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA 2638#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB 2639#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC 2640#define PALMAS_GPADC_SW_SELECT 0xD 2641#define PALMAS_GPADC_SW_CONV0_LSB 0xE 2642#define PALMAS_GPADC_SW_CONV0_MSB 0xF 2643#define PALMAS_GPADC_THRES_CONV0_LSB 0x10 2644#define PALMAS_GPADC_THRES_CONV0_MSB 0x11 2645#define PALMAS_GPADC_THRES_CONV1_LSB 0x12 2646#define PALMAS_GPADC_THRES_CONV1_MSB 0x13 2647#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14 2648#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15 2649 2650/* Bit definitions for GPADC_CTRL1 */ 2651#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0 2652#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6 2653#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30 2654#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4 2655#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c 2656#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2 2657#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02 2658#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1 2659#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01 2660#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0 2661 2662/* Bit definitions for GPADC_CTRL2 */ 2663#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06 2664#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1 2665 2666/* Bit definitions for GPADC_RT_CTRL */ 2667#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02 2668#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1 2669#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01 2670#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0 2671 2672/* Bit definitions for GPADC_AUTO_CTRL */ 2673#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80 2674#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7 2675#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40 2676#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6 2677#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20 2678#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5 2679#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10 2680#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4 2681#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f 2682#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0 2683 2684/* Bit definitions for GPADC_STATUS */ 2685#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10 2686#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4 2687 2688/* Bit definitions for GPADC_RT_SELECT */ 2689#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80 2690#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7 2691#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f 2692#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0 2693 2694/* Bit definitions for GPADC_RT_CONV0_LSB */ 2695#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff 2696#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0 2697 2698/* Bit definitions for GPADC_RT_CONV0_MSB */ 2699#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f 2700#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0 2701 2702/* Bit definitions for GPADC_AUTO_SELECT */ 2703#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0 2704#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4 2705#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f 2706#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0 2707 2708/* Bit definitions for GPADC_AUTO_CONV0_LSB */ 2709#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff 2710#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0 2711 2712/* Bit definitions for GPADC_AUTO_CONV0_MSB */ 2713#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f 2714#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0 2715 2716/* Bit definitions for GPADC_AUTO_CONV1_LSB */ 2717#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff 2718#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0 2719 2720/* Bit definitions for GPADC_AUTO_CONV1_MSB */ 2721#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f 2722#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0 2723 2724/* Bit definitions for GPADC_SW_SELECT */ 2725#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80 2726#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7 2727#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10 2728#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4 2729#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f 2730#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0 2731 2732/* Bit definitions for GPADC_SW_CONV0_LSB */ 2733#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff 2734#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0 2735 2736/* Bit definitions for GPADC_SW_CONV0_MSB */ 2737#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f 2738#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0 2739 2740/* Bit definitions for GPADC_THRES_CONV0_LSB */ 2741#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff 2742#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0 2743 2744/* Bit definitions for GPADC_THRES_CONV0_MSB */ 2745#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80 2746#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7 2747#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f 2748#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0 2749 2750/* Bit definitions for GPADC_THRES_CONV1_LSB */ 2751#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff 2752#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0 2753 2754/* Bit definitions for GPADC_THRES_CONV1_MSB */ 2755#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80 2756#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7 2757#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f 2758#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0 2759 2760/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */ 2761#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20 2762#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5 2763#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10 2764#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4 2765#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f 2766#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0 2767 2768/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */ 2769#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80 2770#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7 2771#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f 2772#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0 2773 2774/* Registers for function GPADC */ 2775#define PALMAS_GPADC_TRIM1 0x0 2776#define PALMAS_GPADC_TRIM2 0x1 2777#define PALMAS_GPADC_TRIM3 0x2 2778#define PALMAS_GPADC_TRIM4 0x3 2779#define PALMAS_GPADC_TRIM5 0x4 2780#define PALMAS_GPADC_TRIM6 0x5 2781#define PALMAS_GPADC_TRIM7 0x6 2782#define PALMAS_GPADC_TRIM8 0x7 2783#define PALMAS_GPADC_TRIM9 0x8 2784#define PALMAS_GPADC_TRIM10 0x9 2785#define PALMAS_GPADC_TRIM11 0xA 2786#define PALMAS_GPADC_TRIM12 0xB 2787#define PALMAS_GPADC_TRIM13 0xC 2788#define PALMAS_GPADC_TRIM14 0xD 2789#define PALMAS_GPADC_TRIM15 0xE 2790#define PALMAS_GPADC_TRIM16 0xF 2791 2792#endif /* __LINUX_MFD_PALMAS_H */