tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Copyright 2012 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15/**
16 * Interface definitions for the trio driver.
17 */
18
19#ifndef _SYS_HV_DRV_TRIO_INTF_H
20#define _SYS_HV_DRV_TRIO_INTF_H
21
22#include <arch/trio.h>
23
24/** The vendor ID for all Tilera processors. */
25#define TILERA_VENDOR_ID 0x1a41
26
27/** The device ID for the Gx36 processor. */
28#define TILERA_GX36_DEV_ID 0x0200
29
30/** Device ID for our internal bridge when running as RC. */
31#define TILERA_GX36_RC_DEV_ID 0x2000
32
33/** Maximum number of TRIO interfaces. */
34#define TILEGX_NUM_TRIO 2
35
36/** Gx36 has max 3 PCIe MACs per TRIO interface. */
37#define TILEGX_TRIO_PCIES 3
38
39/** Specify port properties for a PCIe MAC. */
40struct pcie_port_property
41{
42 /** If true, the link can be configured in PCIe root complex mode. */
43 uint8_t allow_rc: 1;
44
45 /** If true, the link can be configured in PCIe endpoint mode. */
46 uint8_t allow_ep: 1;
47
48 /** If true, the link can be configured in StreamIO mode. */
49 uint8_t allow_sio: 1;
50
51 /** If true, the link is allowed to support 1-lane operation. Software
52 * will not consider it an error if the link comes up as a x1 link. */
53 uint8_t allow_x1: 1;
54
55 /** If true, the link is allowed to support 2-lane operation. Software
56 * will not consider it an error if the link comes up as a x2 link. */
57 uint8_t allow_x2: 1;
58
59 /** If true, the link is allowed to support 4-lane operation. Software
60 * will not consider it an error if the link comes up as a x4 link. */
61 uint8_t allow_x4: 1;
62
63 /** If true, the link is allowed to support 8-lane operation. Software
64 * will not consider it an error if the link comes up as a x8 link. */
65 uint8_t allow_x8: 1;
66
67 /** Reserved. */
68 uint8_t reserved: 1;
69
70};
71
72/** Configurations can be issued to configure a char stream interrupt. */
73typedef enum pcie_stream_intr_config_sel_e
74{
75 /** Interrupt configuration for memory map regions. */
76 MEM_MAP_SEL,
77
78 /** Interrupt configuration for push DMAs. */
79 PUSH_DMA_SEL,
80
81 /** Interrupt configuration for pull DMAs. */
82 PULL_DMA_SEL,
83}
84pcie_stream_intr_config_sel_t;
85
86
87/** The mmap file offset (PA) of the TRIO config region. */
88#define HV_TRIO_CONFIG_OFFSET \
89 ((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG << \
90 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT)
91
92/** The maximum size of the TRIO config region. */
93#define HV_TRIO_CONFIG_SIZE \
94 (1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT)
95
96/** Size of the config region mapped into client. We can't use
97 * TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it
98 * will require the kernel to allocate 4GB VA space
99 * from the VMALLOC region which has a total range
100 * of 4GB.
101 */
102#define HV_TRIO_CONFIG_IOREMAP_SIZE \
103 ((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT)
104
105/** The mmap file offset (PA) of a scatter queue region. */
106#define HV_TRIO_SQ_OFFSET(queue) \
107 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ << \
108 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
109 ((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT))
110
111/** The maximum size of a scatter queue region. */
112#define HV_TRIO_SQ_SIZE \
113 (1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)
114
115
116/** The "hardware MMIO region" of the first PIO region. */
117#define HV_TRIO_FIRST_PIO_REGION 8
118
119/** The mmap file offset (PA) of a PIO region. */
120#define HV_TRIO_PIO_OFFSET(region) \
121 (((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \
122 << TRIO_PIO_REGIONS_ADDR__REGION_SHIFT)
123
124/** The maximum size of a PIO region. */
125#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH)
126
127
128/** The mmap file offset (PA) of a push DMA region. */
129#define HV_TRIO_PUSH_DMA_OFFSET(ring) \
130 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \
131 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
132 ((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT))
133
134/** The mmap file offset (PA) of a pull DMA region. */
135#define HV_TRIO_PULL_DMA_OFFSET(ring) \
136 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \
137 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
138 ((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT))
139
140/** The maximum size of a DMA region. */
141#define HV_TRIO_DMA_REGION_SIZE \
142 (1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)
143
144
145/** The mmap file offset (PA) of a Mem-Map interrupt region. */
146#define HV_TRIO_MEM_MAP_INTR_OFFSET(map) \
147 (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM << \
148 TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) | \
149 ((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT))
150
151/** The maximum size of a Mem-Map interrupt region. */
152#define HV_TRIO_MEM_MAP_INTR_SIZE \
153 (1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)
154
155
156/** A flag bit indicating a fixed resource allocation. */
157#define HV_TRIO_ALLOC_FIXED 0x01
158
159/** TRIO requires that all mappings have 4kB aligned start addresses. */
160#define HV_TRIO_PAGE_SHIFT 12
161
162/** TRIO requires that all mappings have 4kB aligned start addresses. */
163#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT)
164
165
166/* Specify all PCIe port properties for a TRIO. */
167struct pcie_trio_ports_property
168{
169 struct pcie_port_property ports[TILEGX_TRIO_PCIES];
170};
171
172/* Flags indicating traffic class. */
173#define HV_TRIO_FLAG_TC_SHIFT 4
174#define HV_TRIO_FLAG_TC_RMASK 0xf
175#define HV_TRIO_FLAG_TC(N) \
176 ((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT)
177
178/* Flags indicating virtual functions. */
179#define HV_TRIO_FLAG_VFUNC_SHIFT 8
180#define HV_TRIO_FLAG_VFUNC_RMASK 0xff
181#define HV_TRIO_FLAG_VFUNC(N) \
182 ((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT)
183
184
185/* Flag indicating an ordered PIO region. */
186#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16)
187
188/* Flags indicating special types of PIO regions. */
189#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17
190#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
191#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
192#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
193
194
195#endif /* _SYS_HV_DRV_TRIO_INTF_H */