tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * ti_hdmi_4xxx_ip.h
3 *
4 * HDMI header definition for DM81xx, DM38xx, TI OMAP4 etc processors.
5 *
6 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef _HDMI_TI_4xxx_H_
22#define _HDMI_TI_4xxx_H_
23
24#include <linux/string.h>
25#include <video/omapdss.h>
26#include "ti_hdmi.h"
27
28/* HDMI Wrapper */
29
30#define HDMI_WP_REVISION 0x0
31#define HDMI_WP_SYSCONFIG 0x10
32#define HDMI_WP_IRQSTATUS_RAW 0x24
33#define HDMI_WP_IRQSTATUS 0x28
34#define HDMI_WP_PWR_CTRL 0x40
35#define HDMI_WP_IRQENABLE_SET 0x2C
36#define HDMI_WP_VIDEO_CFG 0x50
37#define HDMI_WP_VIDEO_SIZE 0x60
38#define HDMI_WP_VIDEO_TIMING_H 0x68
39#define HDMI_WP_VIDEO_TIMING_V 0x6C
40#define HDMI_WP_WP_CLK 0x70
41#define HDMI_WP_AUDIO_CFG 0x80
42#define HDMI_WP_AUDIO_CFG2 0x84
43#define HDMI_WP_AUDIO_CTRL 0x88
44#define HDMI_WP_AUDIO_DATA 0x8C
45
46/* HDMI IP Core System */
47
48#define HDMI_CORE_SYS_VND_IDL 0x0
49#define HDMI_CORE_SYS_DEV_IDL 0x8
50#define HDMI_CORE_SYS_DEV_IDH 0xC
51#define HDMI_CORE_SYS_DEV_REV 0x10
52#define HDMI_CORE_SYS_SRST 0x14
53#define HDMI_CORE_CTRL1 0x20
54#define HDMI_CORE_SYS_SYS_STAT 0x24
55#define HDMI_CORE_SYS_DE_DLY 0xC8
56#define HDMI_CORE_SYS_DE_CTRL 0xCC
57#define HDMI_CORE_SYS_DE_TOP 0xD0
58#define HDMI_CORE_SYS_DE_CNTL 0xD8
59#define HDMI_CORE_SYS_DE_CNTH 0xDC
60#define HDMI_CORE_SYS_DE_LINL 0xE0
61#define HDMI_CORE_SYS_DE_LINH_1 0xE4
62#define HDMI_CORE_SYS_VID_ACEN 0x124
63#define HDMI_CORE_SYS_VID_MODE 0x128
64#define HDMI_CORE_SYS_INTR_STATE 0x1C0
65#define HDMI_CORE_SYS_INTR1 0x1C4
66#define HDMI_CORE_SYS_INTR2 0x1C8
67#define HDMI_CORE_SYS_INTR3 0x1CC
68#define HDMI_CORE_SYS_INTR4 0x1D0
69#define HDMI_CORE_SYS_UMASK1 0x1D4
70#define HDMI_CORE_SYS_TMDS_CTRL 0x208
71
72#define HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC 0x1
73#define HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC 0x1
74#define HDMI_CORE_CTRL1_BSEL_24BITBUS 0x1
75#define HDMI_CORE_CTRL1_EDGE_RISINGEDGE 0x1
76
77/* HDMI DDC E-DID */
78#define HDMI_CORE_DDC_ADDR 0x3B4
79#define HDMI_CORE_DDC_SEGM 0x3B8
80#define HDMI_CORE_DDC_OFFSET 0x3BC
81#define HDMI_CORE_DDC_COUNT1 0x3C0
82#define HDMI_CORE_DDC_COUNT2 0x3C4
83#define HDMI_CORE_DDC_STATUS 0x3C8
84#define HDMI_CORE_DDC_CMD 0x3CC
85#define HDMI_CORE_DDC_DATA 0x3D0
86
87/* HDMI IP Core Audio Video */
88
89#define HDMI_CORE_AV_ACR_CTRL 0x4
90#define HDMI_CORE_AV_FREQ_SVAL 0x8
91#define HDMI_CORE_AV_N_SVAL1 0xC
92#define HDMI_CORE_AV_N_SVAL2 0x10
93#define HDMI_CORE_AV_N_SVAL3 0x14
94#define HDMI_CORE_AV_CTS_SVAL1 0x18
95#define HDMI_CORE_AV_CTS_SVAL2 0x1C
96#define HDMI_CORE_AV_CTS_SVAL3 0x20
97#define HDMI_CORE_AV_CTS_HVAL1 0x24
98#define HDMI_CORE_AV_CTS_HVAL2 0x28
99#define HDMI_CORE_AV_CTS_HVAL3 0x2C
100#define HDMI_CORE_AV_AUD_MODE 0x50
101#define HDMI_CORE_AV_SPDIF_CTRL 0x54
102#define HDMI_CORE_AV_HW_SPDIF_FS 0x60
103#define HDMI_CORE_AV_SWAP_I2S 0x64
104#define HDMI_CORE_AV_SPDIF_ERTH 0x6C
105#define HDMI_CORE_AV_I2S_IN_MAP 0x70
106#define HDMI_CORE_AV_I2S_IN_CTRL 0x74
107#define HDMI_CORE_AV_I2S_CHST0 0x78
108#define HDMI_CORE_AV_I2S_CHST1 0x7C
109#define HDMI_CORE_AV_I2S_CHST2 0x80
110#define HDMI_CORE_AV_I2S_CHST4 0x84
111#define HDMI_CORE_AV_I2S_CHST5 0x88
112#define HDMI_CORE_AV_ASRC 0x8C
113#define HDMI_CORE_AV_I2S_IN_LEN 0x90
114#define HDMI_CORE_AV_HDMI_CTRL 0xBC
115#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0
116#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC
117#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0
118#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4
119#define HDMI_CORE_AV_TEST_TXCTRL 0xF0
120#define HDMI_CORE_AV_DPD 0xF4
121#define HDMI_CORE_AV_PB_CTRL1 0xF8
122#define HDMI_CORE_AV_PB_CTRL2 0xFC
123#define HDMI_CORE_AV_AVI_TYPE 0x100
124#define HDMI_CORE_AV_AVI_VERS 0x104
125#define HDMI_CORE_AV_AVI_LEN 0x108
126#define HDMI_CORE_AV_AVI_CHSUM 0x10C
127#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)
128#define HDMI_CORE_AV_SPD_TYPE 0x180
129#define HDMI_CORE_AV_SPD_VERS 0x184
130#define HDMI_CORE_AV_SPD_LEN 0x188
131#define HDMI_CORE_AV_SPD_CHSUM 0x18C
132#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)
133#define HDMI_CORE_AV_AUDIO_TYPE 0x200
134#define HDMI_CORE_AV_AUDIO_VERS 0x204
135#define HDMI_CORE_AV_AUDIO_LEN 0x208
136#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C
137#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)
138#define HDMI_CORE_AV_MPEG_TYPE 0x280
139#define HDMI_CORE_AV_MPEG_VERS 0x284
140#define HDMI_CORE_AV_MPEG_LEN 0x288
141#define HDMI_CORE_AV_MPEG_CHSUM 0x28C
142#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)
143#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)
144#define HDMI_CORE_AV_CP_BYTE1 0x37C
145#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)
146#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC
147
148#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4
149#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4
150#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4
151#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4
152
153#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15
154#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27
155#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10
156#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27
157#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31
158#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31
159
160/* PLL */
161
162#define PLLCTRL_PLL_CONTROL 0x0
163#define PLLCTRL_PLL_STATUS 0x4
164#define PLLCTRL_PLL_GO 0x8
165#define PLLCTRL_CFG1 0xC
166#define PLLCTRL_CFG2 0x10
167#define PLLCTRL_CFG3 0x14
168#define PLLCTRL_CFG4 0x20
169
170/* HDMI PHY */
171
172#define HDMI_TXPHY_TX_CTRL 0x0
173#define HDMI_TXPHY_DIGITAL_CTRL 0x4
174#define HDMI_TXPHY_POWER_CTRL 0x8
175#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
176
177#define REG_FLD_MOD(base, idx, val, start, end) \
178 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
179 val, start, end))
180#define REG_GET(base, idx, start, end) \
181 FLD_GET(hdmi_read_reg(base, idx), start, end)
182
183enum hdmi_phy_pwr {
184 HDMI_PHYPWRCMD_OFF = 0,
185 HDMI_PHYPWRCMD_LDOON = 1,
186 HDMI_PHYPWRCMD_TXON = 2
187};
188
189enum hdmi_core_inputbus_width {
190 HDMI_INPUT_8BIT = 0,
191 HDMI_INPUT_10BIT = 1,
192 HDMI_INPUT_12BIT = 2
193};
194
195enum hdmi_core_dither_trunc {
196 HDMI_OUTPUTTRUNCATION_8BIT = 0,
197 HDMI_OUTPUTTRUNCATION_10BIT = 1,
198 HDMI_OUTPUTTRUNCATION_12BIT = 2,
199 HDMI_OUTPUTDITHER_8BIT = 3,
200 HDMI_OUTPUTDITHER_10BIT = 4,
201 HDMI_OUTPUTDITHER_12BIT = 5
202};
203
204enum hdmi_core_deepcolor_ed {
205 HDMI_DEEPCOLORPACKECTDISABLE = 0,
206 HDMI_DEEPCOLORPACKECTENABLE = 1
207};
208
209enum hdmi_core_packet_mode {
210 HDMI_PACKETMODERESERVEDVALUE = 0,
211 HDMI_PACKETMODE24BITPERPIXEL = 4,
212 HDMI_PACKETMODE30BITPERPIXEL = 5,
213 HDMI_PACKETMODE36BITPERPIXEL = 6,
214 HDMI_PACKETMODE48BITPERPIXEL = 7
215};
216
217enum hdmi_core_tclkselclkmult {
218 HDMI_FPLL05IDCK = 0,
219 HDMI_FPLL10IDCK = 1,
220 HDMI_FPLL20IDCK = 2,
221 HDMI_FPLL40IDCK = 3
222};
223
224enum hdmi_core_packet_ctrl {
225 HDMI_PACKETENABLE = 1,
226 HDMI_PACKETDISABLE = 0,
227 HDMI_PACKETREPEATON = 1,
228 HDMI_PACKETREPEATOFF = 0
229};
230
231/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
232enum hdmi_core_infoframe {
233 HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
234 HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
235 HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
236 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
237 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
238 HDMI_INFOFRAME_AVI_DB1B_NO = 0,
239 HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
240 HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
241 HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
242 HDMI_INFOFRAME_AVI_DB1S_0 = 0,
243 HDMI_INFOFRAME_AVI_DB1S_1 = 1,
244 HDMI_INFOFRAME_AVI_DB1S_2 = 2,
245 HDMI_INFOFRAME_AVI_DB2C_NO = 0,
246 HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
247 HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
248 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
249 HDMI_INFOFRAME_AVI_DB2M_NO = 0,
250 HDMI_INFOFRAME_AVI_DB2M_43 = 1,
251 HDMI_INFOFRAME_AVI_DB2M_169 = 2,
252 HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
253 HDMI_INFOFRAME_AVI_DB2R_43 = 9,
254 HDMI_INFOFRAME_AVI_DB2R_169 = 10,
255 HDMI_INFOFRAME_AVI_DB2R_149 = 11,
256 HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
257 HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
258 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
259 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
260 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
261 HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
262 HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
263 HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
264 HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
265 HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
266 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
267 HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
268 HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
269 HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
270 HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
271 HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
272 HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
273 HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
274 HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
275 HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
276 HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
277};
278
279enum hdmi_packing_mode {
280 HDMI_PACK_10b_RGB_YUV444 = 0,
281 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
282 HDMI_PACK_20b_YUV422 = 2,
283 HDMI_PACK_ALREADYPACKED = 7
284};
285
286enum hdmi_core_audio_layout {
287 HDMI_AUDIO_LAYOUT_2CH = 0,
288 HDMI_AUDIO_LAYOUT_8CH = 1
289};
290
291enum hdmi_core_cts_mode {
292 HDMI_AUDIO_CTS_MODE_HW = 0,
293 HDMI_AUDIO_CTS_MODE_SW = 1
294};
295
296enum hdmi_stereo_channels {
297 HDMI_AUDIO_STEREO_NOCHANNELS = 0,
298 HDMI_AUDIO_STEREO_ONECHANNEL = 1,
299 HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
300 HDMI_AUDIO_STEREO_THREECHANNELS = 3,
301 HDMI_AUDIO_STEREO_FOURCHANNELS = 4
302};
303
304enum hdmi_audio_type {
305 HDMI_AUDIO_TYPE_LPCM = 0,
306 HDMI_AUDIO_TYPE_IEC = 1
307};
308
309enum hdmi_audio_justify {
310 HDMI_AUDIO_JUSTIFY_LEFT = 0,
311 HDMI_AUDIO_JUSTIFY_RIGHT = 1
312};
313
314enum hdmi_audio_sample_order {
315 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
316 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
317};
318
319enum hdmi_audio_samples_perword {
320 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
321 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
322};
323
324enum hdmi_audio_sample_size {
325 HDMI_AUDIO_SAMPLE_16BITS = 0,
326 HDMI_AUDIO_SAMPLE_24BITS = 1
327};
328
329enum hdmi_audio_transf_mode {
330 HDMI_AUDIO_TRANSF_DMA = 0,
331 HDMI_AUDIO_TRANSF_IRQ = 1
332};
333
334enum hdmi_audio_blk_strt_end_sig {
335 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
336 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
337};
338
339enum hdmi_audio_i2s_config {
340 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
341 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
342 HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
343 HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
344 HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
345 HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
346 HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
347 HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
348 HDMI_AUDIO_I2S_SD0_EN = 1,
349 HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
350 HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
351 HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
352};
353
354enum hdmi_audio_mclk_mode {
355 HDMI_AUDIO_MCLK_128FS = 0,
356 HDMI_AUDIO_MCLK_256FS = 1,
357 HDMI_AUDIO_MCLK_384FS = 2,
358 HDMI_AUDIO_MCLK_512FS = 3,
359 HDMI_AUDIO_MCLK_768FS = 4,
360 HDMI_AUDIO_MCLK_1024FS = 5,
361 HDMI_AUDIO_MCLK_1152FS = 6,
362 HDMI_AUDIO_MCLK_192FS = 7
363};
364
365struct hdmi_core_video_config {
366 enum hdmi_core_inputbus_width ip_bus_width;
367 enum hdmi_core_dither_trunc op_dither_truc;
368 enum hdmi_core_deepcolor_ed deep_color_pkt;
369 enum hdmi_core_packet_mode pkt_mode;
370 enum hdmi_core_hdmi_dvi hdmi_dvi;
371 enum hdmi_core_tclkselclkmult tclk_sel_clkmult;
372};
373
374struct hdmi_core_packet_enable_repeat {
375 u32 audio_pkt;
376 u32 audio_pkt_repeat;
377 u32 avi_infoframe;
378 u32 avi_infoframe_repeat;
379 u32 gen_cntrl_pkt;
380 u32 gen_cntrl_pkt_repeat;
381 u32 generic_pkt;
382 u32 generic_pkt_repeat;
383};
384
385struct hdmi_video_format {
386 enum hdmi_packing_mode packing_mode;
387 u32 y_res; /* Line per panel */
388 u32 x_res; /* pixel per line */
389};
390
391struct hdmi_audio_format {
392 enum hdmi_stereo_channels stereo_channels;
393 u8 active_chnnls_msk;
394 enum hdmi_audio_type type;
395 enum hdmi_audio_justify justification;
396 enum hdmi_audio_sample_order sample_order;
397 enum hdmi_audio_samples_perword samples_per_word;
398 enum hdmi_audio_sample_size sample_size;
399 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
400};
401
402struct hdmi_audio_dma {
403 u8 transfer_size;
404 u8 block_size;
405 enum hdmi_audio_transf_mode mode;
406 u16 fifo_threshold;
407};
408
409struct hdmi_core_audio_i2s_config {
410 u8 in_length_bits;
411 u8 justification;
412 u8 sck_edge_mode;
413 u8 vbit;
414 u8 direction;
415 u8 shift;
416 u8 active_sds;
417};
418
419struct hdmi_core_audio_config {
420 struct hdmi_core_audio_i2s_config i2s_cfg;
421 struct snd_aes_iec958 *iec60958_cfg;
422 bool fs_override;
423 u32 n;
424 u32 cts;
425 u32 aud_par_busclk;
426 enum hdmi_core_audio_layout layout;
427 enum hdmi_core_cts_mode cts_mode;
428 bool use_mclk;
429 enum hdmi_audio_mclk_mode mclk_mode;
430 bool en_acr_pkt;
431 bool en_dsd_audio;
432 bool en_parallel_aud_input;
433 bool en_spdif;
434};
435
436#endif