tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Carveout for multimedia usecases
11 * It should be the last 48MB of the first 512MB memory part
12 * In theory, it should not even exist. That zone should be reserved
13 * dynamically during the .reserve callback.
14 */
15/memreserve/ 0x9d000000 0x03000000;
16
17/include/ "skeleton.dtsi"
18
19/ {
20 compatible = "ti,omap4430", "ti,omap4";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 };
29
30 cpus {
31 cpu@0 {
32 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
34 };
35 cpu@1 {
36 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
38 };
39 };
40
41 gic: interrupt-controller@48241000 {
42 compatible = "arm,cortex-a9-gic";
43 interrupt-controller;
44 #interrupt-cells = <3>;
45 reg = <0x48241000 0x1000>,
46 <0x48240100 0x0100>;
47 };
48
49 L2: l2-cache-controller@48242000 {
50 compatible = "arm,pl310-cache";
51 reg = <0x48242000 0x1000>;
52 cache-unified;
53 cache-level = <2>;
54 };
55
56 local-timer@0x48240600 {
57 compatible = "arm,cortex-a9-twd-timer";
58 reg = <0x48240600 0x20>;
59 interrupts = <1 13 0x304>;
60 };
61
62 /*
63 * The soc node represents the soc top level view. It is uses for IPs
64 * that are not memory mapped in the MPU view or for the MPU itself.
65 */
66 soc {
67 compatible = "ti,omap-infra";
68 mpu {
69 compatible = "ti,omap4-mpu";
70 ti,hwmods = "mpu";
71 };
72
73 dsp {
74 compatible = "ti,omap3-c64";
75 ti,hwmods = "dsp";
76 };
77
78 iva {
79 compatible = "ti,ivahd";
80 ti,hwmods = "iva";
81 };
82 };
83
84 /*
85 * XXX: Use a flat representation of the OMAP4 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
89 * hierarchy.
90 */
91 ocp {
92 compatible = "ti,omap4-l3-noc", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97
98 omap4_pmx_core: pinmux@4a100040 {
99 compatible = "ti,omap4-padconf", "pinctrl-single";
100 reg = <0x4a100040 0x0196>;
101 #address-cells = <1>;
102 #size-cells = <0>;
103 pinctrl-single,register-width = <16>;
104 pinctrl-single,function-mask = <0x7fff>;
105 };
106 omap4_pmx_wkup: pinmux@4a31e040 {
107 compatible = "ti,omap4-padconf", "pinctrl-single";
108 reg = <0x4a31e040 0x0038>;
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-single,register-width = <16>;
112 pinctrl-single,function-mask = <0x7fff>;
113 };
114
115 gpio1: gpio@4a310000 {
116 compatible = "ti,omap4-gpio";
117 reg = <0x4a310000 0x200>;
118 interrupts = <0 29 0x4>;
119 ti,hwmods = "gpio1";
120 gpio-controller;
121 #gpio-cells = <2>;
122 interrupt-controller;
123 #interrupt-cells = <1>;
124 };
125
126 gpio2: gpio@48055000 {
127 compatible = "ti,omap4-gpio";
128 reg = <0x48055000 0x200>;
129 interrupts = <0 30 0x4>;
130 ti,hwmods = "gpio2";
131 gpio-controller;
132 #gpio-cells = <2>;
133 interrupt-controller;
134 #interrupt-cells = <1>;
135 };
136
137 gpio3: gpio@48057000 {
138 compatible = "ti,omap4-gpio";
139 reg = <0x48057000 0x200>;
140 interrupts = <0 31 0x4>;
141 ti,hwmods = "gpio3";
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <1>;
146 };
147
148 gpio4: gpio@48059000 {
149 compatible = "ti,omap4-gpio";
150 reg = <0x48059000 0x200>;
151 interrupts = <0 32 0x4>;
152 ti,hwmods = "gpio4";
153 gpio-controller;
154 #gpio-cells = <2>;
155 interrupt-controller;
156 #interrupt-cells = <1>;
157 };
158
159 gpio5: gpio@4805b000 {
160 compatible = "ti,omap4-gpio";
161 reg = <0x4805b000 0x200>;
162 interrupts = <0 33 0x4>;
163 ti,hwmods = "gpio5";
164 gpio-controller;
165 #gpio-cells = <2>;
166 interrupt-controller;
167 #interrupt-cells = <1>;
168 };
169
170 gpio6: gpio@4805d000 {
171 compatible = "ti,omap4-gpio";
172 reg = <0x4805d000 0x200>;
173 interrupts = <0 34 0x4>;
174 ti,hwmods = "gpio6";
175 gpio-controller;
176 #gpio-cells = <2>;
177 interrupt-controller;
178 #interrupt-cells = <1>;
179 };
180
181 uart1: serial@4806a000 {
182 compatible = "ti,omap4-uart";
183 reg = <0x4806a000 0x100>;
184 interrupts = <0 72 0x4>;
185 ti,hwmods = "uart1";
186 clock-frequency = <48000000>;
187 };
188
189 uart2: serial@4806c000 {
190 compatible = "ti,omap4-uart";
191 reg = <0x4806c000 0x100>;
192 interrupts = <0 73 0x4>;
193 ti,hwmods = "uart2";
194 clock-frequency = <48000000>;
195 };
196
197 uart3: serial@48020000 {
198 compatible = "ti,omap4-uart";
199 reg = <0x48020000 0x100>;
200 interrupts = <0 74 0x4>;
201 ti,hwmods = "uart3";
202 clock-frequency = <48000000>;
203 };
204
205 uart4: serial@4806e000 {
206 compatible = "ti,omap4-uart";
207 reg = <0x4806e000 0x100>;
208 interrupts = <0 70 0x4>;
209 ti,hwmods = "uart4";
210 clock-frequency = <48000000>;
211 };
212
213 i2c1: i2c@48070000 {
214 compatible = "ti,omap4-i2c";
215 reg = <0x48070000 0x100>;
216 interrupts = <0 56 0x4>;
217 #address-cells = <1>;
218 #size-cells = <0>;
219 ti,hwmods = "i2c1";
220 };
221
222 i2c2: i2c@48072000 {
223 compatible = "ti,omap4-i2c";
224 reg = <0x48072000 0x100>;
225 interrupts = <0 57 0x4>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 ti,hwmods = "i2c2";
229 };
230
231 i2c3: i2c@48060000 {
232 compatible = "ti,omap4-i2c";
233 reg = <0x48060000 0x100>;
234 interrupts = <0 61 0x4>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237 ti,hwmods = "i2c3";
238 };
239
240 i2c4: i2c@48350000 {
241 compatible = "ti,omap4-i2c";
242 reg = <0x48350000 0x100>;
243 interrupts = <0 62 0x4>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 ti,hwmods = "i2c4";
247 };
248
249 mcspi1: spi@48098000 {
250 compatible = "ti,omap4-mcspi";
251 reg = <0x48098000 0x200>;
252 interrupts = <0 65 0x4>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 ti,hwmods = "mcspi1";
256 ti,spi-num-cs = <4>;
257 };
258
259 mcspi2: spi@4809a000 {
260 compatible = "ti,omap4-mcspi";
261 reg = <0x4809a000 0x200>;
262 interrupts = <0 66 0x4>;
263 #address-cells = <1>;
264 #size-cells = <0>;
265 ti,hwmods = "mcspi2";
266 ti,spi-num-cs = <2>;
267 };
268
269 mcspi3: spi@480b8000 {
270 compatible = "ti,omap4-mcspi";
271 reg = <0x480b8000 0x200>;
272 interrupts = <0 91 0x4>;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 ti,hwmods = "mcspi3";
276 ti,spi-num-cs = <2>;
277 };
278
279 mcspi4: spi@480ba000 {
280 compatible = "ti,omap4-mcspi";
281 reg = <0x480ba000 0x200>;
282 interrupts = <0 48 0x4>;
283 #address-cells = <1>;
284 #size-cells = <0>;
285 ti,hwmods = "mcspi4";
286 ti,spi-num-cs = <1>;
287 };
288
289 mmc1: mmc@4809c000 {
290 compatible = "ti,omap4-hsmmc";
291 reg = <0x4809c000 0x400>;
292 interrupts = <0 83 0x4>;
293 ti,hwmods = "mmc1";
294 ti,dual-volt;
295 ti,needs-special-reset;
296 };
297
298 mmc2: mmc@480b4000 {
299 compatible = "ti,omap4-hsmmc";
300 reg = <0x480b4000 0x400>;
301 interrupts = <0 86 0x4>;
302 ti,hwmods = "mmc2";
303 ti,needs-special-reset;
304 };
305
306 mmc3: mmc@480ad000 {
307 compatible = "ti,omap4-hsmmc";
308 reg = <0x480ad000 0x400>;
309 interrupts = <0 94 0x4>;
310 ti,hwmods = "mmc3";
311 ti,needs-special-reset;
312 };
313
314 mmc4: mmc@480d1000 {
315 compatible = "ti,omap4-hsmmc";
316 reg = <0x480d1000 0x400>;
317 interrupts = <0 96 0x4>;
318 ti,hwmods = "mmc4";
319 ti,needs-special-reset;
320 };
321
322 mmc5: mmc@480d5000 {
323 compatible = "ti,omap4-hsmmc";
324 reg = <0x480d5000 0x400>;
325 interrupts = <0 59 0x4>;
326 ti,hwmods = "mmc5";
327 ti,needs-special-reset;
328 };
329
330 wdt2: wdt@4a314000 {
331 compatible = "ti,omap4-wdt", "ti,omap3-wdt";
332 reg = <0x4a314000 0x80>;
333 interrupts = <0 80 0x4>;
334 ti,hwmods = "wd_timer2";
335 };
336
337 mcpdm: mcpdm@40132000 {
338 compatible = "ti,omap4-mcpdm";
339 reg = <0x40132000 0x7f>, /* MPU private access */
340 <0x49032000 0x7f>; /* L3 Interconnect */
341 reg-names = "mpu", "dma";
342 interrupts = <0 112 0x4>;
343 interrupt-parent = <&gic>;
344 ti,hwmods = "mcpdm";
345 };
346
347 dmic: dmic@4012e000 {
348 compatible = "ti,omap4-dmic";
349 reg = <0x4012e000 0x7f>, /* MPU private access */
350 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>;
353 interrupt-parent = <&gic>;
354 ti,hwmods = "dmic";
355 };
356
357 mcbsp1: mcbsp@40122000 {
358 compatible = "ti,omap4-mcbsp";
359 reg = <0x40122000 0xff>, /* MPU private access */
360 <0x49022000 0xff>; /* L3 Interconnect */
361 reg-names = "mpu", "dma";
362 interrupts = <0 17 0x4>;
363 interrupt-names = "common";
364 interrupt-parent = <&gic>;
365 ti,buffer-size = <128>;
366 ti,hwmods = "mcbsp1";
367 };
368
369 mcbsp2: mcbsp@40124000 {
370 compatible = "ti,omap4-mcbsp";
371 reg = <0x40124000 0xff>, /* MPU private access */
372 <0x49024000 0xff>; /* L3 Interconnect */
373 reg-names = "mpu", "dma";
374 interrupts = <0 22 0x4>;
375 interrupt-names = "common";
376 interrupt-parent = <&gic>;
377 ti,buffer-size = <128>;
378 ti,hwmods = "mcbsp2";
379 };
380
381 mcbsp3: mcbsp@40126000 {
382 compatible = "ti,omap4-mcbsp";
383 reg = <0x40126000 0xff>, /* MPU private access */
384 <0x49026000 0xff>; /* L3 Interconnect */
385 reg-names = "mpu", "dma";
386 interrupts = <0 23 0x4>;
387 interrupt-names = "common";
388 interrupt-parent = <&gic>;
389 ti,buffer-size = <128>;
390 ti,hwmods = "mcbsp3";
391 };
392
393 mcbsp4: mcbsp@48096000 {
394 compatible = "ti,omap4-mcbsp";
395 reg = <0x48096000 0xff>; /* L4 Interconnect */
396 reg-names = "mpu";
397 interrupts = <0 16 0x4>;
398 interrupt-names = "common";
399 interrupt-parent = <&gic>;
400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4";
402 };
403
404 keypad: keypad@4a31c000 {
405 compatible = "ti,omap4-keypad";
406 reg = <0x4a31c000 0x80>;
407 interrupts = <0 120 0x4>;
408 reg-names = "mpu";
409 ti,hwmods = "kbd";
410 };
411
412 emif1: emif@4c000000 {
413 compatible = "ti,emif-4d";
414 reg = <0x4c000000 0x100>;
415 interrupts = <0 110 0x4>;
416 ti,hwmods = "emif1";
417 phy-type = <1>;
418 hw-caps-read-idle-ctrl;
419 hw-caps-ll-interface;
420 hw-caps-temp-alert;
421 };
422
423 emif2: emif@4d000000 {
424 compatible = "ti,emif-4d";
425 reg = <0x4d000000 0x100>;
426 interrupts = <0 111 0x4>;
427 ti,hwmods = "emif2";
428 phy-type = <1>;
429 hw-caps-read-idle-ctrl;
430 hw-caps-ll-interface;
431 hw-caps-temp-alert;
432 };
433
434 ocp2scp {
435 compatible = "ti,omap-ocp2scp";
436 #address-cells = <1>;
437 #size-cells = <1>;
438 ranges;
439 ti,hwmods = "ocp2scp_usb_phy";
440 };
441 };
442};