tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
3 *
4 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
5 */
6
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/errno.h>
10#include <linux/tty.h>
11#include <linux/tty_flip.h>
12#include <linux/major.h>
13#include <linux/circ_buf.h>
14#include <linux/serial.h>
15#include <linux/sysrq.h>
16#include <linux/console.h>
17#include <linux/spinlock.h>
18#include <linux/slab.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/irq.h>
23#include <linux/io.h>
24
25#warning "Please try migrate to use new driver SCCNXP and report the status" \
26 "in the linux-serial mailing list."
27
28#if defined(CONFIG_MAGIC_SYSRQ)
29#define SUPPORT_SYSRQ
30#endif
31
32#include <linux/serial_core.h>
33
34#define SC26XX_MAJOR 204
35#define SC26XX_MINOR_START 205
36#define SC26XX_NR 2
37
38struct uart_sc26xx_port {
39 struct uart_port port[2];
40 u8 dsr_mask[2];
41 u8 cts_mask[2];
42 u8 dcd_mask[2];
43 u8 ri_mask[2];
44 u8 dtr_mask[2];
45 u8 rts_mask[2];
46 u8 imr;
47};
48
49/* register common to both ports */
50#define RD_ISR 0x14
51#define RD_IPR 0x34
52
53#define WR_ACR 0x10
54#define WR_IMR 0x14
55#define WR_OPCR 0x34
56#define WR_OPR_SET 0x38
57#define WR_OPR_CLR 0x3C
58
59/* access common register */
60#define READ_SC(p, r) readb((p)->membase + RD_##r)
61#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
62
63/* register per port */
64#define RD_PORT_MRx 0x00
65#define RD_PORT_SR 0x04
66#define RD_PORT_RHR 0x0c
67
68#define WR_PORT_MRx 0x00
69#define WR_PORT_CSR 0x04
70#define WR_PORT_CR 0x08
71#define WR_PORT_THR 0x0c
72
73/* SR bits */
74#define SR_BREAK (1 << 7)
75#define SR_FRAME (1 << 6)
76#define SR_PARITY (1 << 5)
77#define SR_OVERRUN (1 << 4)
78#define SR_TXRDY (1 << 2)
79#define SR_RXRDY (1 << 0)
80
81#define CR_RES_MR (1 << 4)
82#define CR_RES_RX (2 << 4)
83#define CR_RES_TX (3 << 4)
84#define CR_STRT_BRK (6 << 4)
85#define CR_STOP_BRK (7 << 4)
86#define CR_DIS_TX (1 << 3)
87#define CR_ENA_TX (1 << 2)
88#define CR_DIS_RX (1 << 1)
89#define CR_ENA_RX (1 << 0)
90
91/* ISR bits */
92#define ISR_RXRDYB (1 << 5)
93#define ISR_TXRDYB (1 << 4)
94#define ISR_RXRDYA (1 << 1)
95#define ISR_TXRDYA (1 << 0)
96
97/* IMR bits */
98#define IMR_RXRDY (1 << 1)
99#define IMR_TXRDY (1 << 0)
100
101/* access port register */
102static inline u8 read_sc_port(struct uart_port *p, u8 reg)
103{
104 return readb(p->membase + p->line * 0x20 + reg);
105}
106
107static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
108{
109 writeb(val, p->membase + p->line * 0x20 + reg);
110}
111
112#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
113#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
114
115static void sc26xx_enable_irq(struct uart_port *port, int mask)
116{
117 struct uart_sc26xx_port *up;
118 int line = port->line;
119
120 port -= line;
121 up = container_of(port, struct uart_sc26xx_port, port[0]);
122
123 up->imr |= mask << (line * 4);
124 WRITE_SC(port, IMR, up->imr);
125}
126
127static void sc26xx_disable_irq(struct uart_port *port, int mask)
128{
129 struct uart_sc26xx_port *up;
130 int line = port->line;
131
132 port -= line;
133 up = container_of(port, struct uart_sc26xx_port, port[0]);
134
135 up->imr &= ~(mask << (line * 4));
136 WRITE_SC(port, IMR, up->imr);
137}
138
139static struct tty_struct *receive_chars(struct uart_port *port)
140{
141 struct tty_struct *tty = NULL;
142 int limit = 10000;
143 unsigned char ch;
144 char flag;
145 u8 status;
146
147 if (port->state != NULL) /* Unopened serial console */
148 tty = port->state->port.tty;
149
150 while (limit-- > 0) {
151 status = READ_SC_PORT(port, SR);
152 if (!(status & SR_RXRDY))
153 break;
154 ch = READ_SC_PORT(port, RHR);
155
156 flag = TTY_NORMAL;
157 port->icount.rx++;
158
159 if (unlikely(status & (SR_BREAK | SR_FRAME |
160 SR_PARITY | SR_OVERRUN))) {
161 if (status & SR_BREAK) {
162 status &= ~(SR_PARITY | SR_FRAME);
163 port->icount.brk++;
164 if (uart_handle_break(port))
165 continue;
166 } else if (status & SR_PARITY)
167 port->icount.parity++;
168 else if (status & SR_FRAME)
169 port->icount.frame++;
170 if (status & SR_OVERRUN)
171 port->icount.overrun++;
172
173 status &= port->read_status_mask;
174 if (status & SR_BREAK)
175 flag = TTY_BREAK;
176 else if (status & SR_PARITY)
177 flag = TTY_PARITY;
178 else if (status & SR_FRAME)
179 flag = TTY_FRAME;
180 }
181
182 if (uart_handle_sysrq_char(port, ch))
183 continue;
184
185 if (status & port->ignore_status_mask)
186 continue;
187
188 tty_insert_flip_char(tty, ch, flag);
189 }
190 return tty;
191}
192
193static void transmit_chars(struct uart_port *port)
194{
195 struct circ_buf *xmit;
196
197 if (!port->state)
198 return;
199
200 xmit = &port->state->xmit;
201 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
202 sc26xx_disable_irq(port, IMR_TXRDY);
203 return;
204 }
205 while (!uart_circ_empty(xmit)) {
206 if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
207 break;
208
209 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
210 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
211 port->icount.tx++;
212 }
213 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
214 uart_write_wakeup(port);
215}
216
217static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
218{
219 struct uart_sc26xx_port *up = dev_id;
220 struct tty_struct *tty;
221 unsigned long flags;
222 u8 isr;
223
224 spin_lock_irqsave(&up->port[0].lock, flags);
225
226 tty = NULL;
227 isr = READ_SC(&up->port[0], ISR);
228 if (isr & ISR_TXRDYA)
229 transmit_chars(&up->port[0]);
230 if (isr & ISR_RXRDYA)
231 tty = receive_chars(&up->port[0]);
232
233 spin_unlock(&up->port[0].lock);
234
235 if (tty)
236 tty_flip_buffer_push(tty);
237
238 spin_lock(&up->port[1].lock);
239
240 tty = NULL;
241 if (isr & ISR_TXRDYB)
242 transmit_chars(&up->port[1]);
243 if (isr & ISR_RXRDYB)
244 tty = receive_chars(&up->port[1]);
245
246 spin_unlock_irqrestore(&up->port[1].lock, flags);
247
248 if (tty)
249 tty_flip_buffer_push(tty);
250
251 return IRQ_HANDLED;
252}
253
254/* port->lock is not held. */
255static unsigned int sc26xx_tx_empty(struct uart_port *port)
256{
257 return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
258}
259
260/* port->lock held by caller. */
261static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
262{
263 struct uart_sc26xx_port *up;
264 int line = port->line;
265
266 port -= line;
267 up = container_of(port, struct uart_sc26xx_port, port[0]);
268
269 if (up->dtr_mask[line]) {
270 if (mctrl & TIOCM_DTR)
271 WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
272 else
273 WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
274 }
275 if (up->rts_mask[line]) {
276 if (mctrl & TIOCM_RTS)
277 WRITE_SC(port, OPR_SET, up->rts_mask[line]);
278 else
279 WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
280 }
281}
282
283/* port->lock is held by caller and interrupts are disabled. */
284static unsigned int sc26xx_get_mctrl(struct uart_port *port)
285{
286 struct uart_sc26xx_port *up;
287 int line = port->line;
288 unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
289 u8 ipr;
290
291 port -= line;
292 up = container_of(port, struct uart_sc26xx_port, port[0]);
293 ipr = READ_SC(port, IPR) ^ 0xff;
294
295 if (up->dsr_mask[line]) {
296 mctrl &= ~TIOCM_DSR;
297 mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
298 }
299 if (up->cts_mask[line]) {
300 mctrl &= ~TIOCM_CTS;
301 mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
302 }
303 if (up->dcd_mask[line]) {
304 mctrl &= ~TIOCM_CAR;
305 mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
306 }
307 if (up->ri_mask[line]) {
308 mctrl &= ~TIOCM_RNG;
309 mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
310 }
311 return mctrl;
312}
313
314/* port->lock held by caller. */
315static void sc26xx_stop_tx(struct uart_port *port)
316{
317 return;
318}
319
320/* port->lock held by caller. */
321static void sc26xx_start_tx(struct uart_port *port)
322{
323 struct circ_buf *xmit = &port->state->xmit;
324
325 while (!uart_circ_empty(xmit)) {
326 if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
327 sc26xx_enable_irq(port, IMR_TXRDY);
328 break;
329 }
330 WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
331 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
332 port->icount.tx++;
333 }
334}
335
336/* port->lock held by caller. */
337static void sc26xx_stop_rx(struct uart_port *port)
338{
339}
340
341/* port->lock held by caller. */
342static void sc26xx_enable_ms(struct uart_port *port)
343{
344}
345
346/* port->lock is not held. */
347static void sc26xx_break_ctl(struct uart_port *port, int break_state)
348{
349 if (break_state == -1)
350 WRITE_SC_PORT(port, CR, CR_STRT_BRK);
351 else
352 WRITE_SC_PORT(port, CR, CR_STOP_BRK);
353}
354
355/* port->lock is not held. */
356static int sc26xx_startup(struct uart_port *port)
357{
358 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
359 WRITE_SC(port, OPCR, 0);
360
361 /* reset tx and rx */
362 WRITE_SC_PORT(port, CR, CR_RES_RX);
363 WRITE_SC_PORT(port, CR, CR_RES_TX);
364
365 /* start rx/tx */
366 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
367
368 /* enable irqs */
369 sc26xx_enable_irq(port, IMR_RXRDY);
370 return 0;
371}
372
373/* port->lock is not held. */
374static void sc26xx_shutdown(struct uart_port *port)
375{
376 /* disable interrupst */
377 sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
378
379 /* stop tx/rx */
380 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
381}
382
383/* port->lock is not held. */
384static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
385 struct ktermios *old)
386{
387 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
388 unsigned int quot = uart_get_divisor(port, baud);
389 unsigned int iflag, cflag;
390 unsigned long flags;
391 u8 mr1, mr2, csr;
392
393 spin_lock_irqsave(&port->lock, flags);
394
395 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
396 udelay(2);
397
398 WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
399
400 iflag = termios->c_iflag;
401 cflag = termios->c_cflag;
402
403 port->read_status_mask = SR_OVERRUN;
404 if (iflag & INPCK)
405 port->read_status_mask |= SR_PARITY | SR_FRAME;
406 if (iflag & (BRKINT | PARMRK))
407 port->read_status_mask |= SR_BREAK;
408
409 port->ignore_status_mask = 0;
410 if (iflag & IGNBRK)
411 port->ignore_status_mask |= SR_BREAK;
412 if ((cflag & CREAD) == 0)
413 port->ignore_status_mask |= SR_BREAK | SR_FRAME |
414 SR_PARITY | SR_OVERRUN;
415
416 switch (cflag & CSIZE) {
417 case CS5:
418 mr1 = 0x00;
419 break;
420 case CS6:
421 mr1 = 0x01;
422 break;
423 case CS7:
424 mr1 = 0x02;
425 break;
426 default:
427 case CS8:
428 mr1 = 0x03;
429 break;
430 }
431 mr2 = 0x07;
432 if (cflag & CSTOPB)
433 mr2 = 0x0f;
434 if (cflag & PARENB) {
435 if (cflag & PARODD)
436 mr1 |= (1 << 2);
437 } else
438 mr1 |= (2 << 3);
439
440 switch (baud) {
441 case 50:
442 csr = 0x00;
443 break;
444 case 110:
445 csr = 0x11;
446 break;
447 case 134:
448 csr = 0x22;
449 break;
450 case 200:
451 csr = 0x33;
452 break;
453 case 300:
454 csr = 0x44;
455 break;
456 case 600:
457 csr = 0x55;
458 break;
459 case 1200:
460 csr = 0x66;
461 break;
462 case 2400:
463 csr = 0x88;
464 break;
465 case 4800:
466 csr = 0x99;
467 break;
468 default:
469 case 9600:
470 csr = 0xbb;
471 break;
472 case 19200:
473 csr = 0xcc;
474 break;
475 }
476
477 WRITE_SC_PORT(port, CR, CR_RES_MR);
478 WRITE_SC_PORT(port, MRx, mr1);
479 WRITE_SC_PORT(port, MRx, mr2);
480
481 WRITE_SC(port, ACR, 0x80);
482 WRITE_SC_PORT(port, CSR, csr);
483
484 /* reset tx and rx */
485 WRITE_SC_PORT(port, CR, CR_RES_RX);
486 WRITE_SC_PORT(port, CR, CR_RES_TX);
487
488 WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
489 while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
490 udelay(2);
491
492 /* XXX */
493 uart_update_timeout(port, cflag,
494 (port->uartclk / (16 * quot)));
495
496 spin_unlock_irqrestore(&port->lock, flags);
497}
498
499static const char *sc26xx_type(struct uart_port *port)
500{
501 return "SC26XX";
502}
503
504static void sc26xx_release_port(struct uart_port *port)
505{
506}
507
508static int sc26xx_request_port(struct uart_port *port)
509{
510 return 0;
511}
512
513static void sc26xx_config_port(struct uart_port *port, int flags)
514{
515}
516
517static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
518{
519 return -EINVAL;
520}
521
522static struct uart_ops sc26xx_ops = {
523 .tx_empty = sc26xx_tx_empty,
524 .set_mctrl = sc26xx_set_mctrl,
525 .get_mctrl = sc26xx_get_mctrl,
526 .stop_tx = sc26xx_stop_tx,
527 .start_tx = sc26xx_start_tx,
528 .stop_rx = sc26xx_stop_rx,
529 .enable_ms = sc26xx_enable_ms,
530 .break_ctl = sc26xx_break_ctl,
531 .startup = sc26xx_startup,
532 .shutdown = sc26xx_shutdown,
533 .set_termios = sc26xx_set_termios,
534 .type = sc26xx_type,
535 .release_port = sc26xx_release_port,
536 .request_port = sc26xx_request_port,
537 .config_port = sc26xx_config_port,
538 .verify_port = sc26xx_verify_port,
539};
540
541static struct uart_port *sc26xx_port;
542
543#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
544static void sc26xx_console_putchar(struct uart_port *port, char c)
545{
546 unsigned long flags;
547 int limit = 1000000;
548
549 spin_lock_irqsave(&port->lock, flags);
550
551 while (limit-- > 0) {
552 if (READ_SC_PORT(port, SR) & SR_TXRDY) {
553 WRITE_SC_PORT(port, THR, c);
554 break;
555 }
556 udelay(2);
557 }
558
559 spin_unlock_irqrestore(&port->lock, flags);
560}
561
562static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
563{
564 struct uart_port *port = sc26xx_port;
565 int i;
566
567 for (i = 0; i < n; i++) {
568 if (*s == '\n')
569 sc26xx_console_putchar(port, '\r');
570 sc26xx_console_putchar(port, *s++);
571 }
572}
573
574static int __init sc26xx_console_setup(struct console *con, char *options)
575{
576 struct uart_port *port = sc26xx_port;
577 int baud = 9600;
578 int bits = 8;
579 int parity = 'n';
580 int flow = 'n';
581
582 if (port->type != PORT_SC26XX)
583 return -1;
584
585 printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
586 if (options)
587 uart_parse_options(options, &baud, &parity, &bits, &flow);
588
589 return uart_set_options(port, con, baud, parity, bits, flow);
590}
591
592static struct uart_driver sc26xx_reg;
593static struct console sc26xx_console = {
594 .name = "ttySC",
595 .write = sc26xx_console_write,
596 .device = uart_console_device,
597 .setup = sc26xx_console_setup,
598 .flags = CON_PRINTBUFFER,
599 .index = -1,
600 .data = &sc26xx_reg,
601};
602#define SC26XX_CONSOLE &sc26xx_console
603#else
604#define SC26XX_CONSOLE NULL
605#endif
606
607static struct uart_driver sc26xx_reg = {
608 .owner = THIS_MODULE,
609 .driver_name = "SC26xx",
610 .dev_name = "ttySC",
611 .major = SC26XX_MAJOR,
612 .minor = SC26XX_MINOR_START,
613 .nr = SC26XX_NR,
614 .cons = SC26XX_CONSOLE,
615};
616
617static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
618{
619 unsigned int bit = (flags >> bitpos) & 15;
620
621 return bit ? (1 << (bit - 1)) : 0;
622}
623
624static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
625 int line, unsigned int data)
626{
627 up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
628 up->rts_mask[line] = sc26xx_flags2mask(data, 4);
629 up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
630 up->cts_mask[line] = sc26xx_flags2mask(data, 12);
631 up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
632 up->ri_mask[line] = sc26xx_flags2mask(data, 20);
633}
634
635static int __devinit sc26xx_probe(struct platform_device *dev)
636{
637 struct resource *res;
638 struct uart_sc26xx_port *up;
639 unsigned int *sc26xx_data = dev->dev.platform_data;
640 int err;
641
642 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
643 if (!res)
644 return -ENODEV;
645
646 up = kzalloc(sizeof *up, GFP_KERNEL);
647 if (unlikely(!up))
648 return -ENOMEM;
649
650 up->port[0].line = 0;
651 up->port[0].ops = &sc26xx_ops;
652 up->port[0].type = PORT_SC26XX;
653 up->port[0].uartclk = (29491200 / 16); /* arbitrary */
654
655 up->port[0].mapbase = res->start;
656 up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
657 up->port[0].iotype = UPIO_MEM;
658 up->port[0].irq = platform_get_irq(dev, 0);
659
660 up->port[0].dev = &dev->dev;
661
662 sc26xx_init_masks(up, 0, sc26xx_data[0]);
663
664 sc26xx_port = &up->port[0];
665
666 up->port[1].line = 1;
667 up->port[1].ops = &sc26xx_ops;
668 up->port[1].type = PORT_SC26XX;
669 up->port[1].uartclk = (29491200 / 16); /* arbitrary */
670
671 up->port[1].mapbase = up->port[0].mapbase;
672 up->port[1].membase = up->port[0].membase;
673 up->port[1].iotype = UPIO_MEM;
674 up->port[1].irq = up->port[0].irq;
675
676 up->port[1].dev = &dev->dev;
677
678 sc26xx_init_masks(up, 1, sc26xx_data[1]);
679
680 err = uart_register_driver(&sc26xx_reg);
681 if (err)
682 goto out_free_port;
683
684 sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
685
686 err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
687 if (err)
688 goto out_unregister_driver;
689
690 err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
691 if (err)
692 goto out_remove_port0;
693
694 err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
695 if (err)
696 goto out_remove_ports;
697
698 dev_set_drvdata(&dev->dev, up);
699 return 0;
700
701out_remove_ports:
702 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
703out_remove_port0:
704 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
705
706out_unregister_driver:
707 uart_unregister_driver(&sc26xx_reg);
708
709out_free_port:
710 kfree(up);
711 sc26xx_port = NULL;
712 return err;
713}
714
715
716static int __exit sc26xx_driver_remove(struct platform_device *dev)
717{
718 struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
719
720 free_irq(up->port[0].irq, up);
721
722 uart_remove_one_port(&sc26xx_reg, &up->port[0]);
723 uart_remove_one_port(&sc26xx_reg, &up->port[1]);
724
725 uart_unregister_driver(&sc26xx_reg);
726
727 kfree(up);
728 sc26xx_port = NULL;
729
730 dev_set_drvdata(&dev->dev, NULL);
731 return 0;
732}
733
734static struct platform_driver sc26xx_driver = {
735 .probe = sc26xx_probe,
736 .remove = __devexit_p(sc26xx_driver_remove),
737 .driver = {
738 .name = "SC26xx",
739 .owner = THIS_MODULE,
740 },
741};
742
743module_platform_driver(sc26xx_driver);
744
745MODULE_AUTHOR("Thomas Bogendörfer");
746MODULE_DESCRIPTION("SC681/SC2692 serial driver");
747MODULE_VERSION("1.0");
748MODULE_LICENSE("GPL");
749MODULE_ALIAS("platform:SC26xx");