tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2006 Chris Dearman (chris@mips.com),
3 */
4#include <linux/init.h>
5#include <linux/kernel.h>
6#include <linux/sched.h>
7#include <linux/mm.h>
8
9#include <asm/mipsregs.h>
10#include <asm/bcache.h>
11#include <asm/cacheops.h>
12#include <asm/page.h>
13#include <asm/pgtable.h>
14#include <asm/mmu_context.h>
15#include <asm/r4kcache.h>
16
17/*
18 * MIPS32/MIPS64 L2 cache handling
19 */
20
21/*
22 * Writeback and invalidate the secondary cache before DMA.
23 */
24static void mips_sc_wback_inv(unsigned long addr, unsigned long size)
25{
26 blast_scache_range(addr, addr + size);
27}
28
29/*
30 * Invalidate the secondary cache before DMA.
31 */
32static void mips_sc_inv(unsigned long addr, unsigned long size)
33{
34 unsigned long lsize = cpu_scache_line_size();
35 unsigned long almask = ~(lsize - 1);
36
37 cache_op(Hit_Writeback_Inv_SD, addr & almask);
38 cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);
39 blast_inv_scache_range(addr, addr + size);
40}
41
42static void mips_sc_enable(void)
43{
44 /* L2 cache is permanently enabled */
45}
46
47static void mips_sc_disable(void)
48{
49 /* L2 cache is permanently enabled */
50}
51
52static struct bcache_ops mips_sc_ops = {
53 .bc_enable = mips_sc_enable,
54 .bc_disable = mips_sc_disable,
55 .bc_wback_inv = mips_sc_wback_inv,
56 .bc_inv = mips_sc_inv
57};
58
59/*
60 * Check if the L2 cache controller is activated on a particular platform.
61 * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
62 * cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the
63 * cache being disabled. However there is no guarantee for this to be
64 * true on all platforms. In an act of stupidity the spec defined bits
65 * 12..15 as implementation defined so below function will eventually have
66 * to be replaced by a platform specific probe.
67 */
68static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
69{
70 unsigned int config2 = read_c0_config2();
71 unsigned int tmp;
72
73 /* Check the bypass bit (L2B) */
74 switch (c->cputype) {
75 case CPU_34K:
76 case CPU_74K:
77 case CPU_1004K:
78 case CPU_BMIPS5000:
79 if (config2 & (1 << 12))
80 return 0;
81 }
82
83 tmp = (config2 >> 4) & 0x0f;
84 if (0 < tmp && tmp <= 7)
85 c->scache.linesz = 2 << tmp;
86 else
87 return 0;
88 return 1;
89}
90
91static inline int __init mips_sc_probe(void)
92{
93 struct cpuinfo_mips *c = ¤t_cpu_data;
94 unsigned int config1, config2;
95 unsigned int tmp;
96
97 /* Mark as not present until probe completed */
98 c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
99
100 /* Ignore anything but MIPSxx processors */
101 if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
102 c->isa_level != MIPS_CPU_ISA_M32R2 &&
103 c->isa_level != MIPS_CPU_ISA_M64R1 &&
104 c->isa_level != MIPS_CPU_ISA_M64R2)
105 return 0;
106
107 /* Does this MIPS32/MIPS64 CPU have a config2 register? */
108 config1 = read_c0_config1();
109 if (!(config1 & MIPS_CONF_M))
110 return 0;
111
112 config2 = read_c0_config2();
113
114 if (!mips_sc_is_activated(c))
115 return 0;
116
117 tmp = (config2 >> 8) & 0x0f;
118 if (0 <= tmp && tmp <= 7)
119 c->scache.sets = 64 << tmp;
120 else
121 return 0;
122
123 tmp = (config2 >> 0) & 0x0f;
124 if (0 <= tmp && tmp <= 7)
125 c->scache.ways = tmp + 1;
126 else
127 return 0;
128
129 c->scache.waysize = c->scache.sets * c->scache.linesz;
130 c->scache.waybit = __ffs(c->scache.waysize);
131
132 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
133
134 return 1;
135}
136
137int __cpuinit mips_sc_init(void)
138{
139 int found = mips_sc_probe();
140 if (found) {
141 mips_sc_enable();
142 bcops = &mips_sc_ops;
143 }
144 return found;
145}