tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/include/mfd/ucb1x00.h
3 *
4 * Copyright (C) 2001 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 */
10#ifndef UCB1200_H
11#define UCB1200_H
12
13#include <linux/mfd/mcp.h>
14#include <linux/gpio.h>
15#include <linux/mutex.h>
16
17#define UCB_IO_DATA 0x00
18#define UCB_IO_DIR 0x01
19
20#define UCB_IO_0 (1 << 0)
21#define UCB_IO_1 (1 << 1)
22#define UCB_IO_2 (1 << 2)
23#define UCB_IO_3 (1 << 3)
24#define UCB_IO_4 (1 << 4)
25#define UCB_IO_5 (1 << 5)
26#define UCB_IO_6 (1 << 6)
27#define UCB_IO_7 (1 << 7)
28#define UCB_IO_8 (1 << 8)
29#define UCB_IO_9 (1 << 9)
30
31#define UCB_IE_RIS 0x02
32#define UCB_IE_FAL 0x03
33#define UCB_IE_STATUS 0x04
34#define UCB_IE_CLEAR 0x04
35#define UCB_IE_ADC (1 << 11)
36#define UCB_IE_TSPX (1 << 12)
37#define UCB_IE_TSMX (1 << 13)
38#define UCB_IE_TCLIP (1 << 14)
39#define UCB_IE_ACLIP (1 << 15)
40
41#define UCB_IRQ_TSPX 12
42
43#define UCB_TC_A 0x05
44#define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
45#define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
46
47#define UCB_TC_B 0x06
48#define UCB_TC_B_VOICE_ENA (1 << 3)
49#define UCB_TC_B_CLIP (1 << 4)
50#define UCB_TC_B_ATT (1 << 6)
51#define UCB_TC_B_SIDE_ENA (1 << 11)
52#define UCB_TC_B_MUTE (1 << 13)
53#define UCB_TC_B_IN_ENA (1 << 14)
54#define UCB_TC_B_OUT_ENA (1 << 15)
55
56#define UCB_AC_A 0x07
57#define UCB_AC_B 0x08
58#define UCB_AC_B_LOOP (1 << 8)
59#define UCB_AC_B_MUTE (1 << 13)
60#define UCB_AC_B_IN_ENA (1 << 14)
61#define UCB_AC_B_OUT_ENA (1 << 15)
62
63#define UCB_TS_CR 0x09
64#define UCB_TS_CR_TSMX_POW (1 << 0)
65#define UCB_TS_CR_TSPX_POW (1 << 1)
66#define UCB_TS_CR_TSMY_POW (1 << 2)
67#define UCB_TS_CR_TSPY_POW (1 << 3)
68#define UCB_TS_CR_TSMX_GND (1 << 4)
69#define UCB_TS_CR_TSPX_GND (1 << 5)
70#define UCB_TS_CR_TSMY_GND (1 << 6)
71#define UCB_TS_CR_TSPY_GND (1 << 7)
72#define UCB_TS_CR_MODE_INT (0 << 8)
73#define UCB_TS_CR_MODE_PRES (1 << 8)
74#define UCB_TS_CR_MODE_POS (2 << 8)
75#define UCB_TS_CR_BIAS_ENA (1 << 11)
76#define UCB_TS_CR_TSPX_LOW (1 << 12)
77#define UCB_TS_CR_TSMX_LOW (1 << 13)
78
79#define UCB_ADC_CR 0x0a
80#define UCB_ADC_SYNC_ENA (1 << 0)
81#define UCB_ADC_VREFBYP_CON (1 << 1)
82#define UCB_ADC_INP_TSPX (0 << 2)
83#define UCB_ADC_INP_TSMX (1 << 2)
84#define UCB_ADC_INP_TSPY (2 << 2)
85#define UCB_ADC_INP_TSMY (3 << 2)
86#define UCB_ADC_INP_AD0 (4 << 2)
87#define UCB_ADC_INP_AD1 (5 << 2)
88#define UCB_ADC_INP_AD2 (6 << 2)
89#define UCB_ADC_INP_AD3 (7 << 2)
90#define UCB_ADC_EXT_REF (1 << 5)
91#define UCB_ADC_START (1 << 7)
92#define UCB_ADC_ENA (1 << 15)
93
94#define UCB_ADC_DATA 0x0b
95#define UCB_ADC_DAT_VAL (1 << 15)
96#define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
97
98#define UCB_ID 0x0c
99#define UCB_ID_1200 0x1004
100#define UCB_ID_1300 0x1005
101#define UCB_ID_TC35143 0x9712
102
103#define UCB_MODE 0x0d
104#define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
105#define UCB_MODE_AUD_OFF_CAN (1 << 13)
106
107enum ucb1x00_reset {
108 UCB_RST_PROBE,
109 UCB_RST_RESUME,
110 UCB_RST_SUSPEND,
111 UCB_RST_REMOVE,
112 UCB_RST_PROBE_FAIL,
113};
114
115struct ucb1x00_plat_data {
116 void (*reset)(enum ucb1x00_reset);
117 unsigned irq_base;
118 int gpio_base;
119 unsigned can_wakeup;
120};
121
122struct ucb1x00 {
123 raw_spinlock_t irq_lock;
124 struct mcp *mcp;
125 unsigned int irq;
126 int irq_base;
127 struct mutex adc_mutex;
128 spinlock_t io_lock;
129 u16 id;
130 u16 io_dir;
131 u16 io_out;
132 u16 adc_cr;
133 u16 irq_fal_enbl;
134 u16 irq_ris_enbl;
135 u16 irq_mask;
136 u16 irq_wake;
137 struct device dev;
138 struct list_head node;
139 struct list_head devs;
140 struct gpio_chip gpio;
141};
142
143struct ucb1x00_driver;
144
145struct ucb1x00_dev {
146 struct list_head dev_node;
147 struct list_head drv_node;
148 struct ucb1x00 *ucb;
149 struct ucb1x00_driver *drv;
150 void *priv;
151};
152
153struct ucb1x00_driver {
154 struct list_head node;
155 struct list_head devs;
156 int (*add)(struct ucb1x00_dev *dev);
157 void (*remove)(struct ucb1x00_dev *dev);
158 int (*suspend)(struct ucb1x00_dev *dev);
159 int (*resume)(struct ucb1x00_dev *dev);
160};
161
162#define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
163
164int ucb1x00_register_driver(struct ucb1x00_driver *);
165void ucb1x00_unregister_driver(struct ucb1x00_driver *);
166
167/**
168 * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
169 * @ucb: UCB1x00 structure describing chip
170 *
171 * Return the SIB clock rate in Hz.
172 */
173static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
174{
175 return mcp_get_sclk_rate(ucb->mcp);
176}
177
178/**
179 * ucb1x00_enable - enable the UCB1x00 SIB clock
180 * @ucb: UCB1x00 structure describing chip
181 *
182 * Enable the SIB clock. This can be called multiple times.
183 */
184static inline void ucb1x00_enable(struct ucb1x00 *ucb)
185{
186 mcp_enable(ucb->mcp);
187}
188
189/**
190 * ucb1x00_disable - disable the UCB1x00 SIB clock
191 * @ucb: UCB1x00 structure describing chip
192 *
193 * Disable the SIB clock. The SIB clock will only be disabled
194 * when the number of ucb1x00_enable calls match the number of
195 * ucb1x00_disable calls.
196 */
197static inline void ucb1x00_disable(struct ucb1x00 *ucb)
198{
199 mcp_disable(ucb->mcp);
200}
201
202/**
203 * ucb1x00_reg_write - write a UCB1x00 register
204 * @ucb: UCB1x00 structure describing chip
205 * @reg: UCB1x00 4-bit register index to write
206 * @val: UCB1x00 16-bit value to write
207 *
208 * Write the UCB1x00 register @reg with value @val. The SIB
209 * clock must be running for this function to return.
210 */
211static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
212{
213 mcp_reg_write(ucb->mcp, reg, val);
214}
215
216/**
217 * ucb1x00_reg_read - read a UCB1x00 register
218 * @ucb: UCB1x00 structure describing chip
219 * @reg: UCB1x00 4-bit register index to write
220 *
221 * Read the UCB1x00 register @reg and return its value. The SIB
222 * clock must be running for this function to return.
223 */
224static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
225{
226 return mcp_reg_read(ucb->mcp, reg);
227}
228/**
229 * ucb1x00_set_audio_divisor -
230 * @ucb: UCB1x00 structure describing chip
231 * @div: SIB clock divisor
232 */
233static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
234{
235 mcp_set_audio_divisor(ucb->mcp, div);
236}
237
238/**
239 * ucb1x00_set_telecom_divisor -
240 * @ucb: UCB1x00 structure describing chip
241 * @div: SIB clock divisor
242 */
243static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
244{
245 mcp_set_telecom_divisor(ucb->mcp, div);
246}
247
248void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
249void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
250unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
251
252#define UCB_NOSYNC (0)
253#define UCB_SYNC (1)
254
255unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
256void ucb1x00_adc_enable(struct ucb1x00 *ucb);
257void ucb1x00_adc_disable(struct ucb1x00 *ucb);
258
259#endif