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linux
1/*
2 * uartlite.c: Serial driver for Xilinx uartlite serial controller
3 *
4 * Copyright (C) 2006 Peter Korsgaard <jacmet@sunsite.dk>
5 * Copyright (C) 2007 Secret Lab Technologies Ltd.
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12#include <linux/platform_device.h>
13#include <linux/module.h>
14#include <linux/console.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/delay.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <asm/io.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_device.h>
26#include <linux/of_platform.h>
27
28#define ULITE_NAME "ttyUL"
29#define ULITE_MAJOR 204
30#define ULITE_MINOR 187
31#define ULITE_NR_UARTS 4
32
33/* ---------------------------------------------------------------------
34 * Register definitions
35 *
36 * For register details see datasheet:
37 * http://www.xilinx.com/support/documentation/ip_documentation/opb_uartlite.pdf
38 */
39
40#define ULITE_RX 0x00
41#define ULITE_TX 0x04
42#define ULITE_STATUS 0x08
43#define ULITE_CONTROL 0x0c
44
45#define ULITE_REGION 16
46
47#define ULITE_STATUS_RXVALID 0x01
48#define ULITE_STATUS_RXFULL 0x02
49#define ULITE_STATUS_TXEMPTY 0x04
50#define ULITE_STATUS_TXFULL 0x08
51#define ULITE_STATUS_IE 0x10
52#define ULITE_STATUS_OVERRUN 0x20
53#define ULITE_STATUS_FRAME 0x40
54#define ULITE_STATUS_PARITY 0x80
55
56#define ULITE_CONTROL_RST_TX 0x01
57#define ULITE_CONTROL_RST_RX 0x02
58#define ULITE_CONTROL_IE 0x10
59
60
61static struct uart_port ulite_ports[ULITE_NR_UARTS];
62
63/* ---------------------------------------------------------------------
64 * Core UART driver operations
65 */
66
67static int ulite_receive(struct uart_port *port, int stat)
68{
69 struct tty_struct *tty = port->state->port.tty;
70 unsigned char ch = 0;
71 char flag = TTY_NORMAL;
72
73 if ((stat & (ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
74 | ULITE_STATUS_FRAME)) == 0)
75 return 0;
76
77 /* stats */
78 if (stat & ULITE_STATUS_RXVALID) {
79 port->icount.rx++;
80 ch = ioread32be(port->membase + ULITE_RX);
81
82 if (stat & ULITE_STATUS_PARITY)
83 port->icount.parity++;
84 }
85
86 if (stat & ULITE_STATUS_OVERRUN)
87 port->icount.overrun++;
88
89 if (stat & ULITE_STATUS_FRAME)
90 port->icount.frame++;
91
92
93 /* drop byte with parity error if IGNPAR specificed */
94 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY)
95 stat &= ~ULITE_STATUS_RXVALID;
96
97 stat &= port->read_status_mask;
98
99 if (stat & ULITE_STATUS_PARITY)
100 flag = TTY_PARITY;
101
102
103 stat &= ~port->ignore_status_mask;
104
105 if (stat & ULITE_STATUS_RXVALID)
106 tty_insert_flip_char(tty, ch, flag);
107
108 if (stat & ULITE_STATUS_FRAME)
109 tty_insert_flip_char(tty, 0, TTY_FRAME);
110
111 if (stat & ULITE_STATUS_OVERRUN)
112 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
113
114 return 1;
115}
116
117static int ulite_transmit(struct uart_port *port, int stat)
118{
119 struct circ_buf *xmit = &port->state->xmit;
120
121 if (stat & ULITE_STATUS_TXFULL)
122 return 0;
123
124 if (port->x_char) {
125 iowrite32be(port->x_char, port->membase + ULITE_TX);
126 port->x_char = 0;
127 port->icount.tx++;
128 return 1;
129 }
130
131 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
132 return 0;
133
134 iowrite32be(xmit->buf[xmit->tail], port->membase + ULITE_TX);
135 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1);
136 port->icount.tx++;
137
138 /* wake up */
139 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
140 uart_write_wakeup(port);
141
142 return 1;
143}
144
145static irqreturn_t ulite_isr(int irq, void *dev_id)
146{
147 struct uart_port *port = dev_id;
148 int busy, n = 0;
149
150 do {
151 int stat = ioread32be(port->membase + ULITE_STATUS);
152 busy = ulite_receive(port, stat);
153 busy |= ulite_transmit(port, stat);
154 n++;
155 } while (busy);
156
157 /* work done? */
158 if (n > 1) {
159 tty_flip_buffer_push(port->state->port.tty);
160 return IRQ_HANDLED;
161 } else {
162 return IRQ_NONE;
163 }
164}
165
166static unsigned int ulite_tx_empty(struct uart_port *port)
167{
168 unsigned long flags;
169 unsigned int ret;
170
171 spin_lock_irqsave(&port->lock, flags);
172 ret = ioread32be(port->membase + ULITE_STATUS);
173 spin_unlock_irqrestore(&port->lock, flags);
174
175 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0;
176}
177
178static unsigned int ulite_get_mctrl(struct uart_port *port)
179{
180 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
181}
182
183static void ulite_set_mctrl(struct uart_port *port, unsigned int mctrl)
184{
185 /* N/A */
186}
187
188static void ulite_stop_tx(struct uart_port *port)
189{
190 /* N/A */
191}
192
193static void ulite_start_tx(struct uart_port *port)
194{
195 ulite_transmit(port, ioread32be(port->membase + ULITE_STATUS));
196}
197
198static void ulite_stop_rx(struct uart_port *port)
199{
200 /* don't forward any more data (like !CREAD) */
201 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
202 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
203}
204
205static void ulite_enable_ms(struct uart_port *port)
206{
207 /* N/A */
208}
209
210static void ulite_break_ctl(struct uart_port *port, int ctl)
211{
212 /* N/A */
213}
214
215static int ulite_startup(struct uart_port *port)
216{
217 int ret;
218
219 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED, "uartlite", port);
220 if (ret)
221 return ret;
222
223 iowrite32be(ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX,
224 port->membase + ULITE_CONTROL);
225 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
226
227 return 0;
228}
229
230static void ulite_shutdown(struct uart_port *port)
231{
232 iowrite32be(0, port->membase + ULITE_CONTROL);
233 ioread32be(port->membase + ULITE_CONTROL); /* dummy */
234 free_irq(port->irq, port);
235}
236
237static void ulite_set_termios(struct uart_port *port, struct ktermios *termios,
238 struct ktermios *old)
239{
240 unsigned long flags;
241 unsigned int baud;
242
243 spin_lock_irqsave(&port->lock, flags);
244
245 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN
246 | ULITE_STATUS_TXFULL;
247
248 if (termios->c_iflag & INPCK)
249 port->read_status_mask |=
250 ULITE_STATUS_PARITY | ULITE_STATUS_FRAME;
251
252 port->ignore_status_mask = 0;
253 if (termios->c_iflag & IGNPAR)
254 port->ignore_status_mask |= ULITE_STATUS_PARITY
255 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
256
257 /* ignore all characters if CREAD is not set */
258 if ((termios->c_cflag & CREAD) == 0)
259 port->ignore_status_mask |=
260 ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY
261 | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN;
262
263 /* update timeout */
264 baud = uart_get_baud_rate(port, termios, old, 0, 460800);
265 uart_update_timeout(port, termios->c_cflag, baud);
266
267 spin_unlock_irqrestore(&port->lock, flags);
268}
269
270static const char *ulite_type(struct uart_port *port)
271{
272 return port->type == PORT_UARTLITE ? "uartlite" : NULL;
273}
274
275static void ulite_release_port(struct uart_port *port)
276{
277 release_mem_region(port->mapbase, ULITE_REGION);
278 iounmap(port->membase);
279 port->membase = NULL;
280}
281
282static int ulite_request_port(struct uart_port *port)
283{
284 pr_debug("ulite console: port=%p; port->mapbase=%llx\n",
285 port, (unsigned long long) port->mapbase);
286
287 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) {
288 dev_err(port->dev, "Memory region busy\n");
289 return -EBUSY;
290 }
291
292 port->membase = ioremap(port->mapbase, ULITE_REGION);
293 if (!port->membase) {
294 dev_err(port->dev, "Unable to map registers\n");
295 release_mem_region(port->mapbase, ULITE_REGION);
296 return -EBUSY;
297 }
298
299 return 0;
300}
301
302static void ulite_config_port(struct uart_port *port, int flags)
303{
304 if (!ulite_request_port(port))
305 port->type = PORT_UARTLITE;
306}
307
308static int ulite_verify_port(struct uart_port *port, struct serial_struct *ser)
309{
310 /* we don't want the core code to modify any port params */
311 return -EINVAL;
312}
313
314#ifdef CONFIG_CONSOLE_POLL
315static int ulite_get_poll_char(struct uart_port *port)
316{
317 if (!(ioread32be(port->membase + ULITE_STATUS)
318 & ULITE_STATUS_RXVALID))
319 return NO_POLL_CHAR;
320
321 return ioread32be(port->membase + ULITE_RX);
322}
323
324static void ulite_put_poll_char(struct uart_port *port, unsigned char ch)
325{
326 while (ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_TXFULL)
327 cpu_relax();
328
329 /* write char to device */
330 iowrite32be(ch, port->membase + ULITE_TX);
331}
332#endif
333
334static struct uart_ops ulite_ops = {
335 .tx_empty = ulite_tx_empty,
336 .set_mctrl = ulite_set_mctrl,
337 .get_mctrl = ulite_get_mctrl,
338 .stop_tx = ulite_stop_tx,
339 .start_tx = ulite_start_tx,
340 .stop_rx = ulite_stop_rx,
341 .enable_ms = ulite_enable_ms,
342 .break_ctl = ulite_break_ctl,
343 .startup = ulite_startup,
344 .shutdown = ulite_shutdown,
345 .set_termios = ulite_set_termios,
346 .type = ulite_type,
347 .release_port = ulite_release_port,
348 .request_port = ulite_request_port,
349 .config_port = ulite_config_port,
350 .verify_port = ulite_verify_port,
351#ifdef CONFIG_CONSOLE_POLL
352 .poll_get_char = ulite_get_poll_char,
353 .poll_put_char = ulite_put_poll_char,
354#endif
355};
356
357/* ---------------------------------------------------------------------
358 * Console driver operations
359 */
360
361#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
362static void ulite_console_wait_tx(struct uart_port *port)
363{
364 int i;
365 u8 val;
366
367 /* Spin waiting for TX fifo to have space available */
368 for (i = 0; i < 100000; i++) {
369 val = ioread32be(port->membase + ULITE_STATUS);
370 if ((val & ULITE_STATUS_TXFULL) == 0)
371 break;
372 cpu_relax();
373 }
374}
375
376static void ulite_console_putchar(struct uart_port *port, int ch)
377{
378 ulite_console_wait_tx(port);
379 iowrite32be(ch, port->membase + ULITE_TX);
380}
381
382static void ulite_console_write(struct console *co, const char *s,
383 unsigned int count)
384{
385 struct uart_port *port = &ulite_ports[co->index];
386 unsigned long flags;
387 unsigned int ier;
388 int locked = 1;
389
390 if (oops_in_progress) {
391 locked = spin_trylock_irqsave(&port->lock, flags);
392 } else
393 spin_lock_irqsave(&port->lock, flags);
394
395 /* save and disable interrupt */
396 ier = ioread32be(port->membase + ULITE_STATUS) & ULITE_STATUS_IE;
397 iowrite32be(0, port->membase + ULITE_CONTROL);
398
399 uart_console_write(port, s, count, ulite_console_putchar);
400
401 ulite_console_wait_tx(port);
402
403 /* restore interrupt state */
404 if (ier)
405 iowrite32be(ULITE_CONTROL_IE, port->membase + ULITE_CONTROL);
406
407 if (locked)
408 spin_unlock_irqrestore(&port->lock, flags);
409}
410
411static int __devinit ulite_console_setup(struct console *co, char *options)
412{
413 struct uart_port *port;
414 int baud = 9600;
415 int bits = 8;
416 int parity = 'n';
417 int flow = 'n';
418
419 if (co->index < 0 || co->index >= ULITE_NR_UARTS)
420 return -EINVAL;
421
422 port = &ulite_ports[co->index];
423
424 /* Has the device been initialized yet? */
425 if (!port->mapbase) {
426 pr_debug("console on ttyUL%i not present\n", co->index);
427 return -ENODEV;
428 }
429
430 /* not initialized yet? */
431 if (!port->membase) {
432 if (ulite_request_port(port))
433 return -ENODEV;
434 }
435
436 if (options)
437 uart_parse_options(options, &baud, &parity, &bits, &flow);
438
439 return uart_set_options(port, co, baud, parity, bits, flow);
440}
441
442static struct uart_driver ulite_uart_driver;
443
444static struct console ulite_console = {
445 .name = ULITE_NAME,
446 .write = ulite_console_write,
447 .device = uart_console_device,
448 .setup = ulite_console_setup,
449 .flags = CON_PRINTBUFFER,
450 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
451 .data = &ulite_uart_driver,
452};
453
454static int __init ulite_console_init(void)
455{
456 register_console(&ulite_console);
457 return 0;
458}
459
460console_initcall(ulite_console_init);
461
462#endif /* CONFIG_SERIAL_UARTLITE_CONSOLE */
463
464static struct uart_driver ulite_uart_driver = {
465 .owner = THIS_MODULE,
466 .driver_name = "uartlite",
467 .dev_name = ULITE_NAME,
468 .major = ULITE_MAJOR,
469 .minor = ULITE_MINOR,
470 .nr = ULITE_NR_UARTS,
471#ifdef CONFIG_SERIAL_UARTLITE_CONSOLE
472 .cons = &ulite_console,
473#endif
474};
475
476/* ---------------------------------------------------------------------
477 * Port assignment functions (mapping devices to uart_port structures)
478 */
479
480/** ulite_assign: register a uartlite device with the driver
481 *
482 * @dev: pointer to device structure
483 * @id: requested id number. Pass -1 for automatic port assignment
484 * @base: base address of uartlite registers
485 * @irq: irq number for uartlite
486 *
487 * Returns: 0 on success, <0 otherwise
488 */
489static int __devinit ulite_assign(struct device *dev, int id, u32 base, int irq)
490{
491 struct uart_port *port;
492 int rc;
493
494 /* if id = -1; then scan for a free id and use that */
495 if (id < 0) {
496 for (id = 0; id < ULITE_NR_UARTS; id++)
497 if (ulite_ports[id].mapbase == 0)
498 break;
499 }
500 if (id < 0 || id >= ULITE_NR_UARTS) {
501 dev_err(dev, "%s%i too large\n", ULITE_NAME, id);
502 return -EINVAL;
503 }
504
505 if ((ulite_ports[id].mapbase) && (ulite_ports[id].mapbase != base)) {
506 dev_err(dev, "cannot assign to %s%i; it is already in use\n",
507 ULITE_NAME, id);
508 return -EBUSY;
509 }
510
511 port = &ulite_ports[id];
512
513 spin_lock_init(&port->lock);
514 port->fifosize = 16;
515 port->regshift = 2;
516 port->iotype = UPIO_MEM;
517 port->iobase = 1; /* mark port in use */
518 port->mapbase = base;
519 port->membase = NULL;
520 port->ops = &ulite_ops;
521 port->irq = irq;
522 port->flags = UPF_BOOT_AUTOCONF;
523 port->dev = dev;
524 port->type = PORT_UNKNOWN;
525 port->line = id;
526
527 dev_set_drvdata(dev, port);
528
529 /* Register the port */
530 rc = uart_add_one_port(&ulite_uart_driver, port);
531 if (rc) {
532 dev_err(dev, "uart_add_one_port() failed; err=%i\n", rc);
533 port->mapbase = 0;
534 dev_set_drvdata(dev, NULL);
535 return rc;
536 }
537
538 return 0;
539}
540
541/** ulite_release: register a uartlite device with the driver
542 *
543 * @dev: pointer to device structure
544 */
545static int __devexit ulite_release(struct device *dev)
546{
547 struct uart_port *port = dev_get_drvdata(dev);
548 int rc = 0;
549
550 if (port) {
551 rc = uart_remove_one_port(&ulite_uart_driver, port);
552 dev_set_drvdata(dev, NULL);
553 port->mapbase = 0;
554 }
555
556 return rc;
557}
558
559/* ---------------------------------------------------------------------
560 * Platform bus binding
561 */
562
563#if defined(CONFIG_OF)
564/* Match table for of_platform binding */
565static struct of_device_id ulite_of_match[] __devinitdata = {
566 { .compatible = "xlnx,opb-uartlite-1.00.b", },
567 { .compatible = "xlnx,xps-uartlite-1.00.a", },
568 {}
569};
570MODULE_DEVICE_TABLE(of, ulite_of_match);
571#endif /* CONFIG_OF */
572
573static int __devinit ulite_probe(struct platform_device *pdev)
574{
575 struct resource *res, *res2;
576 int id = pdev->id;
577#ifdef CONFIG_OF
578 const __be32 *prop;
579
580 prop = of_get_property(pdev->dev.of_node, "port-number", NULL);
581 if (prop)
582 id = be32_to_cpup(prop);
583#endif
584
585 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
586 if (!res)
587 return -ENODEV;
588
589 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
590 if (!res2)
591 return -ENODEV;
592
593 return ulite_assign(&pdev->dev, id, res->start, res2->start);
594}
595
596static int __devexit ulite_remove(struct platform_device *pdev)
597{
598 return ulite_release(&pdev->dev);
599}
600
601/* work with hotplug and coldplug */
602MODULE_ALIAS("platform:uartlite");
603
604static struct platform_driver ulite_platform_driver = {
605 .probe = ulite_probe,
606 .remove = __devexit_p(ulite_remove),
607 .driver = {
608 .owner = THIS_MODULE,
609 .name = "uartlite",
610 .of_match_table = of_match_ptr(ulite_of_match),
611 },
612};
613
614/* ---------------------------------------------------------------------
615 * Module setup/teardown
616 */
617
618int __init ulite_init(void)
619{
620 int ret;
621
622 pr_debug("uartlite: calling uart_register_driver()\n");
623 ret = uart_register_driver(&ulite_uart_driver);
624 if (ret)
625 goto err_uart;
626
627 pr_debug("uartlite: calling platform_driver_register()\n");
628 ret = platform_driver_register(&ulite_platform_driver);
629 if (ret)
630 goto err_plat;
631
632 return 0;
633
634err_plat:
635 uart_unregister_driver(&ulite_uart_driver);
636err_uart:
637 printk(KERN_ERR "registering uartlite driver failed: err=%i", ret);
638 return ret;
639}
640
641void __exit ulite_exit(void)
642{
643 platform_driver_unregister(&ulite_platform_driver);
644 uart_unregister_driver(&ulite_uart_driver);
645}
646
647module_init(ulite_init);
648module_exit(ulite_exit);
649
650MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
651MODULE_DESCRIPTION("Xilinx uartlite serial driver");
652MODULE_LICENSE("GPL");