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1#ifndef __ASM_ALPHA_FPU_H
2#define __ASM_ALPHA_FPU_H
3
4#include <asm/special_insns.h>
5
6/*
7 * Alpha floating-point control register defines:
8 */
9#define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */
10#define FPCR_DNZ (1UL<<48) /* denorms to zero */
11#define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */
12#define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */
13#define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */
14#define FPCR_INV (1UL<<52) /* invalid operation */
15#define FPCR_DZE (1UL<<53) /* division by zero */
16#define FPCR_OVF (1UL<<54) /* overflow */
17#define FPCR_UNF (1UL<<55) /* underflow */
18#define FPCR_INE (1UL<<56) /* inexact */
19#define FPCR_IOV (1UL<<57) /* integer overflow */
20#define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */
21#define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */
22#define FPCR_INED (1UL<<62) /* inexact disable (opt.) */
23#define FPCR_SUM (1UL<<63) /* summary bit */
24
25#define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */
26#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */
27#define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */
28#define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */
29#define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */
30#define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT)
31
32#define FPCR_MASK 0xffff800000000000L
33
34/*
35 * IEEE trap enables are implemented in software. These per-thread
36 * bits are stored in the "ieee_state" field of "struct thread_info".
37 * Thus, the bits are defined so as not to conflict with the
38 * floating-point enable bit (which is architected). On top of that,
39 * we want to make these bits compatible with OSF/1 so
40 * ieee_set_fp_control() etc. can be implemented easily and
41 * compatibly. The corresponding definitions are in
42 * /usr/include/machine/fpu.h under OSF/1.
43 */
44#define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */
45#define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */
46#define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */
47#define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */
48#define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */
49#define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */
50#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\
51 IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\
52 IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO)
53
54/* Denorm and Underflow flushing */
55#define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */
56#define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */
57
58#define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ)
59
60/* status bits coming from fpcr: */
61#define IEEE_STATUS_INV (1UL<<17)
62#define IEEE_STATUS_DZE (1UL<<18)
63#define IEEE_STATUS_OVF (1UL<<19)
64#define IEEE_STATUS_UNF (1UL<<20)
65#define IEEE_STATUS_INE (1UL<<21)
66#define IEEE_STATUS_DNO (1UL<<22)
67
68#define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \
69 IEEE_STATUS_OVF | IEEE_STATUS_UNF | \
70 IEEE_STATUS_INE | IEEE_STATUS_DNO)
71
72#define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \
73 IEEE_STATUS_MASK | IEEE_MAP_MASK)
74
75#define IEEE_CURRENT_RM_SHIFT 32
76#define IEEE_CURRENT_RM_MASK (3UL<<IEEE_CURRENT_RM_SHIFT)
77
78#define IEEE_STATUS_TO_EXCSUM_SHIFT 16
79
80#define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */
81
82/*
83 * Convert the software IEEE trap enable and status bits into the
84 * hardware fpcr format.
85 *
86 * Digital Unix engineers receive my thanks for not defining the
87 * software bits identical to the hardware bits. The chip designers
88 * receive my thanks for making all the not-implemented fpcr bits
89 * RAZ forcing us to use system calls to read/write this value.
90 */
91
92static inline unsigned long
93ieee_swcr_to_fpcr(unsigned long sw)
94{
95 unsigned long fp;
96 fp = (sw & IEEE_STATUS_MASK) << 35;
97 fp |= (sw & IEEE_MAP_DMZ) << 36;
98 fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0);
99 fp |= (~sw & (IEEE_TRAP_ENABLE_INV
100 | IEEE_TRAP_ENABLE_DZE
101 | IEEE_TRAP_ENABLE_OVF)) << 48;
102 fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57;
103 fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
104 fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41;
105 return fp;
106}
107
108static inline unsigned long
109ieee_fpcr_to_swcr(unsigned long fp)
110{
111 unsigned long sw;
112 sw = (fp >> 35) & IEEE_STATUS_MASK;
113 sw |= (fp >> 36) & IEEE_MAP_DMZ;
114 sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV
115 | IEEE_TRAP_ENABLE_DZE
116 | IEEE_TRAP_ENABLE_OVF);
117 sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE);
118 sw |= (fp >> 47) & IEEE_MAP_UMZ;
119 sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO;
120 return sw;
121}
122
123#ifdef __KERNEL__
124
125/* The following two functions don't need trapb/excb instructions
126 around the mf_fpcr/mt_fpcr instructions because (a) the kernel
127 never generates arithmetic faults and (b) call_pal instructions
128 are implied trap barriers. */
129
130static inline unsigned long
131rdfpcr(void)
132{
133 unsigned long tmp, ret;
134
135#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
136 __asm__ __volatile__ (
137 "ftoit $f0,%0\n\t"
138 "mf_fpcr $f0\n\t"
139 "ftoit $f0,%1\n\t"
140 "itoft %0,$f0"
141 : "=r"(tmp), "=r"(ret));
142#else
143 __asm__ __volatile__ (
144 "stt $f0,%0\n\t"
145 "mf_fpcr $f0\n\t"
146 "stt $f0,%1\n\t"
147 "ldt $f0,%0"
148 : "=m"(tmp), "=m"(ret));
149#endif
150
151 return ret;
152}
153
154static inline void
155wrfpcr(unsigned long val)
156{
157 unsigned long tmp;
158
159#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
160 __asm__ __volatile__ (
161 "ftoit $f0,%0\n\t"
162 "itoft %1,$f0\n\t"
163 "mt_fpcr $f0\n\t"
164 "itoft %0,$f0"
165 : "=&r"(tmp) : "r"(val));
166#else
167 __asm__ __volatile__ (
168 "stt $f0,%0\n\t"
169 "ldt $f0,%1\n\t"
170 "mt_fpcr $f0\n\t"
171 "ldt $f0,%0"
172 : "=m"(tmp) : "m"(val));
173#endif
174}
175
176static inline unsigned long
177swcr_update_status(unsigned long swcr, unsigned long fpcr)
178{
179 /* EV6 implements most of the bits in hardware. Collect
180 the acrued exception bits from the real fpcr. */
181 if (implver() == IMPLVER_EV6) {
182 swcr &= ~IEEE_STATUS_MASK;
183 swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
184 }
185 return swcr;
186}
187
188extern unsigned long alpha_read_fp_reg (unsigned long reg);
189extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
190extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
191extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
192
193#endif /* __KERNEL__ */
194
195#endif /* __ASM_ALPHA_FPU_H */