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1/*
2 * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
3 * AVR32 systems.)
4 *
5 * Copyright (C) 2007 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef DW_DMAC_H
13#define DW_DMAC_H
14
15#include <linux/dmaengine.h>
16
17/**
18 * struct dw_dma_platform_data - Controller configuration parameters
19 * @nr_channels: Number of channels supported by hardware (max 8)
20 * @is_private: The device channels should be marked as private and not for
21 * by the general purpose DMA channel allocator.
22 */
23struct dw_dma_platform_data {
24 unsigned int nr_channels;
25 bool is_private;
26#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
27#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
28 unsigned char chan_allocation_order;
29#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
30#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
31 unsigned char chan_priority;
32};
33
34/* bursts size */
35enum dw_dma_msize {
36 DW_DMA_MSIZE_1,
37 DW_DMA_MSIZE_4,
38 DW_DMA_MSIZE_8,
39 DW_DMA_MSIZE_16,
40 DW_DMA_MSIZE_32,
41 DW_DMA_MSIZE_64,
42 DW_DMA_MSIZE_128,
43 DW_DMA_MSIZE_256,
44};
45
46/**
47 * struct dw_dma_slave - Controller-specific information about a slave
48 *
49 * @dma_dev: required DMA master device
50 * @cfg_hi: Platform-specific initializer for the CFG_HI register
51 * @cfg_lo: Platform-specific initializer for the CFG_LO register
52 * @src_master: src master for transfers on allocated channel.
53 * @dst_master: dest master for transfers on allocated channel.
54 */
55struct dw_dma_slave {
56 struct device *dma_dev;
57 u32 cfg_hi;
58 u32 cfg_lo;
59 u8 src_master;
60 u8 dst_master;
61};
62
63/* Platform-configurable bits in CFG_HI */
64#define DWC_CFGH_FCMODE (1 << 0)
65#define DWC_CFGH_FIFO_MODE (1 << 1)
66#define DWC_CFGH_PROTCTL(x) ((x) << 2)
67#define DWC_CFGH_SRC_PER(x) ((x) << 7)
68#define DWC_CFGH_DST_PER(x) ((x) << 11)
69
70/* Platform-configurable bits in CFG_LO */
71#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
72#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
73#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
74#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
75#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
76#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
77#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
78#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
79#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
80#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
81
82/* DMA API extensions */
83struct dw_cyclic_desc {
84 struct dw_desc **desc;
85 unsigned long periods;
86 void (*period_callback)(void *param);
87 void *period_callback_param;
88};
89
90struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
91 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
92 enum dma_transfer_direction direction);
93void dw_dma_cyclic_free(struct dma_chan *chan);
94int dw_dma_cyclic_start(struct dma_chan *chan);
95void dw_dma_cyclic_stop(struct dma_chan *chan);
96
97dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
98
99dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
100
101#endif /* DW_DMAC_H */