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1/* OLPC machine specific definitions */
2
3#ifndef _ASM_X86_OLPC_H
4#define _ASM_X86_OLPC_H
5
6#include <asm/geode.h>
7
8struct olpc_platform_t {
9 int flags;
10 uint32_t boardrev;
11 int ecver;
12};
13
14#define OLPC_F_PRESENT 0x01
15#define OLPC_F_DCON 0x02
16#define OLPC_F_EC_WIDE_SCI 0x04
17
18#ifdef CONFIG_OLPC
19
20extern struct olpc_platform_t olpc_platform_info;
21
22/*
23 * OLPC board IDs contain the major build number within the mask 0x0ff0,
24 * and the minor build number within 0x000f. Pre-builds have a minor
25 * number less than 8, and normal builds start at 8. For example, 0x0B10
26 * is a PreB1, and 0x0C18 is a C1.
27 */
28
29static inline uint32_t olpc_board(uint8_t id)
30{
31 return (id << 4) | 0x8;
32}
33
34static inline uint32_t olpc_board_pre(uint8_t id)
35{
36 return id << 4;
37}
38
39static inline int machine_is_olpc(void)
40{
41 return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0;
42}
43
44/*
45 * The DCON is OLPC's Display Controller. It has a number of unique
46 * features that we might want to take advantage of..
47 */
48static inline int olpc_has_dcon(void)
49{
50 return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
51}
52
53/*
54 * The "Mass Production" version of OLPC's XO is identified as being model
55 * C2. During the prototype phase, the following models (in chronological
56 * order) were created: A1, B1, B2, B3, B4, C1. The A1 through B2 models
57 * were based on Geode GX CPUs, and models after that were based upon
58 * Geode LX CPUs. There were also some hand-assembled models floating
59 * around, referred to as PreB1, PreB2, etc.
60 */
61static inline int olpc_board_at_least(uint32_t rev)
62{
63 return olpc_platform_info.boardrev >= rev;
64}
65
66extern void olpc_ec_wakeup_set(u16 value);
67extern void olpc_ec_wakeup_clear(u16 value);
68extern bool olpc_ec_wakeup_available(void);
69
70extern int olpc_ec_mask_write(u16 bits);
71extern int olpc_ec_sci_query(u16 *sci_value);
72
73#else
74
75static inline int machine_is_olpc(void)
76{
77 return 0;
78}
79
80static inline int olpc_has_dcon(void)
81{
82 return 0;
83}
84
85static inline void olpc_ec_wakeup_set(u16 value) { }
86static inline void olpc_ec_wakeup_clear(u16 value) { }
87
88static inline bool olpc_ec_wakeup_available(void)
89{
90 return false;
91}
92
93#endif
94
95#ifdef CONFIG_OLPC_XO1_PM
96extern void do_olpc_suspend_lowlevel(void);
97extern void olpc_xo1_pm_wakeup_set(u16 value);
98extern void olpc_xo1_pm_wakeup_clear(u16 value);
99#endif
100
101extern int pci_olpc_init(void);
102
103/* EC related functions */
104
105extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
106 unsigned char *outbuf, size_t outlen);
107
108/* EC commands */
109
110#define EC_FIRMWARE_REV 0x08
111#define EC_WRITE_SCI_MASK 0x1b
112#define EC_WAKE_UP_WLAN 0x24
113#define EC_WLAN_LEAVE_RESET 0x25
114#define EC_READ_EB_MODE 0x2a
115#define EC_SET_SCI_INHIBIT 0x32
116#define EC_SET_SCI_INHIBIT_RELEASE 0x34
117#define EC_WLAN_ENTER_RESET 0x35
118#define EC_WRITE_EXT_SCI_MASK 0x38
119#define EC_SCI_QUERY 0x84
120#define EC_EXT_SCI_QUERY 0x85
121
122/* SCI source values */
123
124#define EC_SCI_SRC_EMPTY 0x00
125#define EC_SCI_SRC_GAME 0x01
126#define EC_SCI_SRC_BATTERY 0x02
127#define EC_SCI_SRC_BATSOC 0x04
128#define EC_SCI_SRC_BATERR 0x08
129#define EC_SCI_SRC_EBOOK 0x10 /* XO-1 only */
130#define EC_SCI_SRC_WLAN 0x20 /* XO-1 only */
131#define EC_SCI_SRC_ACPWR 0x40
132#define EC_SCI_SRC_BATCRIT 0x80
133#define EC_SCI_SRC_GPWAKE 0x100 /* XO-1.5 only */
134#define EC_SCI_SRC_ALL 0x1FF
135
136/* GPIO assignments */
137
138#define OLPC_GPIO_MIC_AC 1
139#define OLPC_GPIO_DCON_STAT0 5
140#define OLPC_GPIO_DCON_STAT1 6
141#define OLPC_GPIO_DCON_IRQ 7
142#define OLPC_GPIO_THRM_ALRM geode_gpio(10)
143#define OLPC_GPIO_DCON_LOAD 11
144#define OLPC_GPIO_DCON_BLANK 12
145#define OLPC_GPIO_SMB_CLK 14
146#define OLPC_GPIO_SMB_DATA 15
147#define OLPC_GPIO_WORKAUX geode_gpio(24)
148#define OLPC_GPIO_LID 26
149#define OLPC_GPIO_ECSCI 27
150
151#endif /* _ASM_X86_OLPC_H */