tjh.dev
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1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright SUSE Linux Products GmbH 2010
16 *
17 * Authors: Alexander Graf <agraf@suse.de>
18 */
19
20/* Real mode helpers */
21
22#if defined(CONFIG_PPC_BOOK3S_64)
23
24#define GET_SHADOW_VCPU(reg) \
25 mr reg, r13
26#define MTMSR_EERI(reg) mtmsrd (reg),1
27
28#elif defined(CONFIG_PPC_BOOK3S_32)
29
30#define GET_SHADOW_VCPU(reg) \
31 tophys(reg, r2); \
32 lwz reg, (THREAD + THREAD_KVM_SVCPU)(reg); \
33 tophys(reg, reg)
34#define MTMSR_EERI(reg) mtmsr (reg)
35
36#endif
37
38/* Disable for nested KVM */
39#define USE_QUICK_LAST_INST
40
41
42/* Get helper functions for subarch specific functionality */
43
44#if defined(CONFIG_PPC_BOOK3S_64)
45#include "book3s_64_slb.S"
46#elif defined(CONFIG_PPC_BOOK3S_32)
47#include "book3s_32_sr.S"
48#endif
49
50/******************************************************************************
51 * *
52 * Entry code *
53 * *
54 *****************************************************************************/
55
56.global kvmppc_handler_trampoline_enter
57kvmppc_handler_trampoline_enter:
58
59 /* Required state:
60 *
61 * MSR = ~IR|DR
62 * R1 = host R1
63 * R2 = host R2
64 * R4 = guest shadow MSR
65 * R5 = normal host MSR
66 * R6 = current host MSR (EE, IR, DR off)
67 * LR = highmem guest exit code
68 * all other volatile GPRS = free
69 * SVCPU[CR] = guest CR
70 * SVCPU[XER] = guest XER
71 * SVCPU[CTR] = guest CTR
72 * SVCPU[LR] = guest LR
73 */
74
75 /* r3 = shadow vcpu */
76 GET_SHADOW_VCPU(r3)
77
78 /* Save guest exit handler address and MSR */
79 mflr r0
80 PPC_STL r0, HSTATE_VMHANDLER(r3)
81 PPC_STL r5, HSTATE_HOST_MSR(r3)
82
83 /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
84 PPC_STL r1, HSTATE_HOST_R1(r3)
85 PPC_STL r2, HSTATE_HOST_R2(r3)
86
87 /* Activate guest mode, so faults get handled by KVM */
88 li r11, KVM_GUEST_MODE_GUEST
89 stb r11, HSTATE_IN_GUEST(r3)
90
91 /* Switch to guest segment. This is subarch specific. */
92 LOAD_GUEST_SEGMENTS
93
94#ifdef CONFIG_PPC_BOOK3S_64
95 /* Some guests may need to have dcbz set to 32 byte length.
96 *
97 * Usually we ensure that by patching the guest's instructions
98 * to trap on dcbz and emulate it in the hypervisor.
99 *
100 * If we can, we should tell the CPU to use 32 byte dcbz though,
101 * because that's a lot faster.
102 */
103 lbz r0, HSTATE_RESTORE_HID5(r3)
104 cmpwi r0, 0
105 beq no_dcbz32_on
106
107 mfspr r0,SPRN_HID5
108 ori r0, r0, 0x80 /* XXX HID5_dcbz32 = 0x80 */
109 mtspr SPRN_HID5,r0
110no_dcbz32_on:
111
112#endif /* CONFIG_PPC_BOOK3S_64 */
113
114 /* Enter guest */
115
116 PPC_LL r8, SVCPU_CTR(r3)
117 PPC_LL r9, SVCPU_LR(r3)
118 lwz r10, SVCPU_CR(r3)
119 lwz r11, SVCPU_XER(r3)
120
121 mtctr r8
122 mtlr r9
123 mtcr r10
124 mtxer r11
125
126 /* Move SRR0 and SRR1 into the respective regs */
127 PPC_LL r9, SVCPU_PC(r3)
128 /* First clear RI in our current MSR value */
129 li r0, MSR_RI
130 andc r6, r6, r0
131
132 PPC_LL r0, SVCPU_R0(r3)
133 PPC_LL r1, SVCPU_R1(r3)
134 PPC_LL r2, SVCPU_R2(r3)
135 PPC_LL r5, SVCPU_R5(r3)
136 PPC_LL r7, SVCPU_R7(r3)
137 PPC_LL r8, SVCPU_R8(r3)
138 PPC_LL r10, SVCPU_R10(r3)
139 PPC_LL r11, SVCPU_R11(r3)
140 PPC_LL r12, SVCPU_R12(r3)
141 PPC_LL r13, SVCPU_R13(r3)
142
143 MTMSR_EERI(r6)
144 mtsrr0 r9
145 mtsrr1 r4
146
147 PPC_LL r4, SVCPU_R4(r3)
148 PPC_LL r6, SVCPU_R6(r3)
149 PPC_LL r9, SVCPU_R9(r3)
150 PPC_LL r3, (SVCPU_R3)(r3)
151
152 RFI
153kvmppc_handler_trampoline_enter_end:
154
155
156
157/******************************************************************************
158 * *
159 * Exit code *
160 * *
161 *****************************************************************************/
162
163.global kvmppc_handler_trampoline_exit
164kvmppc_handler_trampoline_exit:
165
166.global kvmppc_interrupt
167kvmppc_interrupt:
168
169 /* Register usage at this point:
170 *
171 * SPRG_SCRATCH0 = guest R13
172 * R12 = exit handler id
173 * R13 = shadow vcpu (32-bit) or PACA (64-bit)
174 * HSTATE.SCRATCH0 = guest R12
175 * HSTATE.SCRATCH1 = guest CR
176 *
177 */
178
179 /* Save registers */
180
181 PPC_STL r0, SVCPU_R0(r13)
182 PPC_STL r1, SVCPU_R1(r13)
183 PPC_STL r2, SVCPU_R2(r13)
184 PPC_STL r3, SVCPU_R3(r13)
185 PPC_STL r4, SVCPU_R4(r13)
186 PPC_STL r5, SVCPU_R5(r13)
187 PPC_STL r6, SVCPU_R6(r13)
188 PPC_STL r7, SVCPU_R7(r13)
189 PPC_STL r8, SVCPU_R8(r13)
190 PPC_STL r9, SVCPU_R9(r13)
191 PPC_STL r10, SVCPU_R10(r13)
192 PPC_STL r11, SVCPU_R11(r13)
193
194 /* Restore R1/R2 so we can handle faults */
195 PPC_LL r1, HSTATE_HOST_R1(r13)
196 PPC_LL r2, HSTATE_HOST_R2(r13)
197
198 /* Save guest PC and MSR */
199#ifdef CONFIG_PPC64
200BEGIN_FTR_SECTION
201 andi. r0, r12, 0x2
202 cmpwi cr1, r0, 0
203 beq 1f
204 mfspr r3,SPRN_HSRR0
205 mfspr r4,SPRN_HSRR1
206 andi. r12,r12,0x3ffd
207 b 2f
208END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
209#endif
2101: mfsrr0 r3
211 mfsrr1 r4
2122:
213 PPC_STL r3, SVCPU_PC(r13)
214 PPC_STL r4, SVCPU_SHADOW_SRR1(r13)
215
216 /* Get scratch'ed off registers */
217 GET_SCRATCH0(r9)
218 PPC_LL r8, HSTATE_SCRATCH0(r13)
219 lwz r7, HSTATE_SCRATCH1(r13)
220
221 PPC_STL r9, SVCPU_R13(r13)
222 PPC_STL r8, SVCPU_R12(r13)
223 stw r7, SVCPU_CR(r13)
224
225 /* Save more register state */
226
227 mfxer r5
228 mfdar r6
229 mfdsisr r7
230 mfctr r8
231 mflr r9
232
233 stw r5, SVCPU_XER(r13)
234 PPC_STL r6, SVCPU_FAULT_DAR(r13)
235 stw r7, SVCPU_FAULT_DSISR(r13)
236 PPC_STL r8, SVCPU_CTR(r13)
237 PPC_STL r9, SVCPU_LR(r13)
238
239 /*
240 * In order for us to easily get the last instruction,
241 * we got the #vmexit at, we exploit the fact that the
242 * virtual layout is still the same here, so we can just
243 * ld from the guest's PC address
244 */
245
246 /* We only load the last instruction when it's safe */
247 cmpwi r12, BOOK3S_INTERRUPT_DATA_STORAGE
248 beq ld_last_inst
249 cmpwi r12, BOOK3S_INTERRUPT_PROGRAM
250 beq ld_last_inst
251 cmpwi r12, BOOK3S_INTERRUPT_SYSCALL
252 beq ld_last_prev_inst
253 cmpwi r12, BOOK3S_INTERRUPT_ALIGNMENT
254 beq- ld_last_inst
255#ifdef CONFIG_PPC64
256BEGIN_FTR_SECTION
257 cmpwi r12, BOOK3S_INTERRUPT_H_EMUL_ASSIST
258 beq- ld_last_inst
259END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
260#endif
261
262 b no_ld_last_inst
263
264ld_last_prev_inst:
265 addi r3, r3, -4
266
267ld_last_inst:
268 /* Save off the guest instruction we're at */
269
270 /* In case lwz faults */
271 li r0, KVM_INST_FETCH_FAILED
272
273#ifdef USE_QUICK_LAST_INST
274
275 /* Set guest mode to 'jump over instruction' so if lwz faults
276 * we'll just continue at the next IP. */
277 li r9, KVM_GUEST_MODE_SKIP
278 stb r9, HSTATE_IN_GUEST(r13)
279
280 /* 1) enable paging for data */
281 mfmsr r9
282 ori r11, r9, MSR_DR /* Enable paging for data */
283 mtmsr r11
284 sync
285 /* 2) fetch the instruction */
286 lwz r0, 0(r3)
287 /* 3) disable paging again */
288 mtmsr r9
289 sync
290
291#endif
292 stw r0, SVCPU_LAST_INST(r13)
293
294no_ld_last_inst:
295
296 /* Unset guest mode */
297 li r9, KVM_GUEST_MODE_NONE
298 stb r9, HSTATE_IN_GUEST(r13)
299
300 /* Switch back to host MMU */
301 LOAD_HOST_SEGMENTS
302
303#ifdef CONFIG_PPC_BOOK3S_64
304
305 lbz r5, HSTATE_RESTORE_HID5(r13)
306 cmpwi r5, 0
307 beq no_dcbz32_off
308
309 li r4, 0
310 mfspr r5,SPRN_HID5
311 rldimi r5,r4,6,56
312 mtspr SPRN_HID5,r5
313
314no_dcbz32_off:
315
316#endif /* CONFIG_PPC_BOOK3S_64 */
317
318 /*
319 * For some interrupts, we need to call the real Linux
320 * handler, so it can do work for us. This has to happen
321 * as if the interrupt arrived from the kernel though,
322 * so let's fake it here where most state is restored.
323 *
324 * Having set up SRR0/1 with the address where we want
325 * to continue with relocation on (potentially in module
326 * space), we either just go straight there with rfi[d],
327 * or we jump to an interrupt handler if there is an
328 * interrupt to be handled first. In the latter case,
329 * the rfi[d] at the end of the interrupt handler will
330 * get us back to where we want to continue.
331 */
332
333 /* Register usage at this point:
334 *
335 * R1 = host R1
336 * R2 = host R2
337 * R10 = raw exit handler id
338 * R12 = exit handler id
339 * R13 = shadow vcpu (32-bit) or PACA (64-bit)
340 * SVCPU.* = guest *
341 *
342 */
343
344 PPC_LL r6, HSTATE_HOST_MSR(r13)
345 PPC_LL r8, HSTATE_VMHANDLER(r13)
346
347#ifdef CONFIG_PPC64
348BEGIN_FTR_SECTION
349 beq cr1, 1f
350 mtspr SPRN_HSRR1, r6
351 mtspr SPRN_HSRR0, r8
352END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
353#endif
3541: /* Restore host msr -> SRR1 */
355 mtsrr1 r6
356 /* Load highmem handler address */
357 mtsrr0 r8
358
359 /* RFI into the highmem handler, or jump to interrupt handler */
360 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
361 beqa BOOK3S_INTERRUPT_EXTERNAL
362 cmpwi r12, BOOK3S_INTERRUPT_DECREMENTER
363 beqa BOOK3S_INTERRUPT_DECREMENTER
364 cmpwi r12, BOOK3S_INTERRUPT_PERFMON
365 beqa BOOK3S_INTERRUPT_PERFMON
366
367 RFI
368kvmppc_handler_trampoline_exit_end: