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Linux kernel mirror (for testing)
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linux
1/*
2 * bfin_sport.h - interface to Blackfin SPORTs
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __BFIN_SPORT_H__
10#define __BFIN_SPORT_H__
11
12/* Sport mode: it can be set to TDM, i2s or others */
13#define NORM_MODE 0x0
14#define TDM_MODE 0x1
15#define I2S_MODE 0x2
16#define NDSO_MODE 0x3
17
18/* Data format, normal, a-law or u-law */
19#define NORM_FORMAT 0x0
20#define ALAW_FORMAT 0x2
21#define ULAW_FORMAT 0x3
22
23/* Function driver which use sport must initialize the structure */
24struct sport_config {
25 /* TDM (multichannels), I2S or other mode */
26 unsigned int mode:3;
27 unsigned int polled; /* use poll instead of irq when set */
28
29 /* if TDM mode is selected, channels must be set */
30 int channels; /* Must be in 8 units */
31 unsigned int frame_delay:4; /* Delay between frame sync pulse and first bit */
32
33 /* I2S mode */
34 unsigned int right_first:1; /* Right stereo channel first */
35
36 /* In mormal mode, the following item need to be set */
37 unsigned int lsb_first:1; /* order of transmit or receive data */
38 unsigned int fsync:1; /* Frame sync required */
39 unsigned int data_indep:1; /* data independent frame sync generated */
40 unsigned int act_low:1; /* Active low TFS */
41 unsigned int late_fsync:1; /* Late frame sync */
42 unsigned int tckfe:1;
43 unsigned int sec_en:1; /* Secondary side enabled */
44
45 /* Choose clock source */
46 unsigned int int_clk:1; /* Internal or external clock */
47
48 /* If external clock is used, the following fields are ignored */
49 int serial_clk;
50 int fsync_clk;
51
52 unsigned int data_format:2; /* Normal, u-law or a-law */
53
54 int word_len; /* How length of the word in bits, 3-32 bits */
55 int dma_enabled;
56};
57
58/* Userspace interface */
59#define SPORT_IOC_MAGIC 'P'
60#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
61#define SPORT_IOC_GET_SYSTEMCLOCK _IOR('P', 0x02, unsigned long)
62#define SPORT_IOC_SET_BAUDRATE _IOW('P', 0x03, unsigned long)
63
64#ifdef __KERNEL__
65
66#include <linux/types.h>
67
68/*
69 * All Blackfin system MMRs are padded to 32bits even if the register
70 * itself is only 16bits. So use a helper macro to streamline this.
71 */
72#define __BFP(m) u16 m; u16 __pad_##m
73struct sport_register {
74 __BFP(tcr1);
75 __BFP(tcr2);
76 __BFP(tclkdiv);
77 __BFP(tfsdiv);
78 union {
79 u32 tx32;
80 u16 tx16;
81 };
82 u32 __pad_tx;
83 union {
84 u32 rx32; /* use the anomaly wrapper below */
85 u16 rx16;
86 };
87 u32 __pad_rx;
88 __BFP(rcr1);
89 __BFP(rcr2);
90 __BFP(rclkdiv);
91 __BFP(rfsdiv);
92 __BFP(stat);
93 __BFP(chnl);
94 __BFP(mcmc1);
95 __BFP(mcmc2);
96 u32 mtcs0;
97 u32 mtcs1;
98 u32 mtcs2;
99 u32 mtcs3;
100 u32 mrcs0;
101 u32 mrcs1;
102 u32 mrcs2;
103 u32 mrcs3;
104};
105#undef __BFP
106
107struct bfin_snd_platform_data {
108 const unsigned short *pin_req;
109};
110
111#define bfin_read_sport_rx32(base) \
112({ \
113 struct sport_register *__mmrs = (void *)base; \
114 u32 __ret; \
115 unsigned long flags; \
116 if (ANOMALY_05000473) \
117 local_irq_save(flags); \
118 __ret = __mmrs->rx32; \
119 if (ANOMALY_05000473) \
120 local_irq_restore(flags); \
121 __ret; \
122})
123
124#endif
125
126/* SPORT_TCR1 Masks */
127#define TSPEN 0x0001 /* TX enable */
128#define ITCLK 0x0002 /* Internal TX Clock Select */
129#define TDTYPE 0x000C /* TX Data Formatting Select */
130#define DTYPE_NORM 0x0000 /* Data Format Normal */
131#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
132#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
133#define TLSBIT 0x0010 /* TX Bit Order */
134#define ITFS 0x0200 /* Internal TX Frame Sync Select */
135#define TFSR 0x0400 /* TX Frame Sync Required Select */
136#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
137#define LTFS 0x1000 /* Low TX Frame Sync Select */
138#define LATFS 0x2000 /* Late TX Frame Sync Select */
139#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
140
141/* SPORT_TCR2 Masks */
142#define SLEN 0x001F /* SPORT TX Word Length (2 - 31) */
143#define DP_SLEN(x) BFIN_DEPOSIT(SLEN, x)
144#define EX_SLEN(x) BFIN_EXTRACT(SLEN, x)
145#define TXSE 0x0100 /* TX Secondary Enable */
146#define TSFSE 0x0200 /* TX Stereo Frame Sync Enable */
147#define TRFST 0x0400 /* TX Right-First Data Order */
148
149/* SPORT_RCR1 Masks */
150#define RSPEN 0x0001 /* RX enable */
151#define IRCLK 0x0002 /* Internal RX Clock Select */
152#define RDTYPE 0x000C /* RX Data Formatting Select */
153/* DTYPE_* defined above */
154#define RLSBIT 0x0010 /* RX Bit Order */
155#define IRFS 0x0200 /* Internal RX Frame Sync Select */
156#define RFSR 0x0400 /* RX Frame Sync Required Select */
157#define LRFS 0x1000 /* Low RX Frame Sync Select */
158#define LARFS 0x2000 /* Late RX Frame Sync Select */
159#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
160
161/* SPORT_RCR2 Masks */
162/* SLEN defined above */
163#define RXSE 0x0100 /* RX Secondary Enable */
164#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
165#define RRFST 0x0400 /* Right-First Data Order */
166
167/* SPORT_STAT Masks */
168#define RXNE 0x0001 /* RX FIFO Not Empty Status */
169#define RUVF 0x0002 /* RX Underflow Status */
170#define ROVF 0x0004 /* RX Overflow Status */
171#define TXF 0x0008 /* TX FIFO Full Status */
172#define TUVF 0x0010 /* TX Underflow Status */
173#define TOVF 0x0020 /* TX Overflow Status */
174#define TXHRE 0x0040 /* TX Hold Register Empty */
175
176/* SPORT_MCMC1 Masks */
177#define SP_WOFF 0x03FF /* Multichannel Window Offset Field */
178#define DP_SP_WOFF(x) BFIN_DEPOSIT(SP_WOFF, x)
179#define EX_SP_WOFF(x) BFIN_EXTRACT(SP_WOFF, x)
180#define SP_WSIZE 0xF000 /* Multichannel Window Size Field */
181#define DP_SP_WSIZE(x) BFIN_DEPOSIT(SP_WSIZE, x)
182#define EX_SP_WSIZE(x) BFIN_EXTRACT(SP_WSIZE, x)
183
184/* SPORT_MCMC2 Masks */
185#define MCCRM 0x0003 /* Multichannel Clock Recovery Mode */
186#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
187#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
188#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
189#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
190#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
191#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
192#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
193#define MFD 0xF000 /* Multichannel Frame Delay */
194#define DP_MFD(x) BFIN_DEPOSIT(MFD, x)
195#define EX_MFD(x) BFIN_EXTRACT(MFD, x)
196
197#endif