tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2009-2011 Wind River Systems, Inc.
3 * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
19 * functions in one PCI endpoint functions. This driver simply
20 * registers the platform devices in this iomemregion and exports a few
21 * functions to access common registers
22 */
23
24#ifndef __STA2X11_MFD_H
25#define __STA2X11_MFD_H
26#include <linux/types.h>
27#include <linux/pci.h>
28
29/*
30 * The MFD PCI block includes the GPIO peripherals and other register blocks.
31 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
32 */
33#define GSTA_GPIO_PER_BLOCK 32
34#define GSTA_NR_BLOCKS 4
35#define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
36
37/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
38struct sta2x11_gpio_pdata {
39 unsigned pinconfig[GSTA_NR_GPIO];
40};
41
42/* Macros below lifted from sh_pfc.h, with minor differences */
43#define PINMUX_TYPE_NONE 0
44#define PINMUX_TYPE_FUNCTION 1
45#define PINMUX_TYPE_OUTPUT_LOW 2
46#define PINMUX_TYPE_OUTPUT_HIGH 3
47#define PINMUX_TYPE_INPUT 4
48#define PINMUX_TYPE_INPUT_PULLUP 5
49#define PINMUX_TYPE_INPUT_PULLDOWN 6
50
51/* Give names to GPIO pins, like PXA does, taken from the manual */
52#define STA2X11_GPIO0 0
53#define STA2X11_GPIO1 1
54#define STA2X11_GPIO2 2
55#define STA2X11_GPIO3 3
56#define STA2X11_GPIO4 4
57#define STA2X11_GPIO5 5
58#define STA2X11_GPIO6 6
59#define STA2X11_GPIO7 7
60#define STA2X11_GPIO8_RGBOUT_RED7 8
61#define STA2X11_GPIO9_RGBOUT_RED6 9
62#define STA2X11_GPIO10_RGBOUT_RED5 10
63#define STA2X11_GPIO11_RGBOUT_RED4 11
64#define STA2X11_GPIO12_RGBOUT_RED3 12
65#define STA2X11_GPIO13_RGBOUT_RED2 13
66#define STA2X11_GPIO14_RGBOUT_RED1 14
67#define STA2X11_GPIO15_RGBOUT_RED0 15
68#define STA2X11_GPIO16_RGBOUT_GREEN7 16
69#define STA2X11_GPIO17_RGBOUT_GREEN6 17
70#define STA2X11_GPIO18_RGBOUT_GREEN5 18
71#define STA2X11_GPIO19_RGBOUT_GREEN4 19
72#define STA2X11_GPIO20_RGBOUT_GREEN3 20
73#define STA2X11_GPIO21_RGBOUT_GREEN2 21
74#define STA2X11_GPIO22_RGBOUT_GREEN1 22
75#define STA2X11_GPIO23_RGBOUT_GREEN0 23
76#define STA2X11_GPIO24_RGBOUT_BLUE7 24
77#define STA2X11_GPIO25_RGBOUT_BLUE6 25
78#define STA2X11_GPIO26_RGBOUT_BLUE5 26
79#define STA2X11_GPIO27_RGBOUT_BLUE4 27
80#define STA2X11_GPIO28_RGBOUT_BLUE3 28
81#define STA2X11_GPIO29_RGBOUT_BLUE2 29
82#define STA2X11_GPIO30_RGBOUT_BLUE1 30
83#define STA2X11_GPIO31_RGBOUT_BLUE0 31
84#define STA2X11_GPIO32_RGBOUT_VSYNCH 32
85#define STA2X11_GPIO33_RGBOUT_HSYNCH 33
86#define STA2X11_GPIO34_RGBOUT_DEN 34
87#define STA2X11_GPIO35_ETH_CRS_DV 35
88#define STA2X11_GPIO36_ETH_TXD1 36
89#define STA2X11_GPIO37_ETH_TXD0 37
90#define STA2X11_GPIO38_ETH_TX_EN 38
91#define STA2X11_GPIO39_MDIO 39
92#define STA2X11_GPIO40_ETH_REF_CLK 40
93#define STA2X11_GPIO41_ETH_RXD1 41
94#define STA2X11_GPIO42_ETH_RXD0 42
95#define STA2X11_GPIO43_MDC 43
96#define STA2X11_GPIO44_CAN_TX 44
97#define STA2X11_GPIO45_CAN_RX 45
98#define STA2X11_GPIO46_MLB_DAT 46
99#define STA2X11_GPIO47_MLB_SIG 47
100#define STA2X11_GPIO48_SPI0_CLK 48
101#define STA2X11_GPIO49_SPI0_TXD 49
102#define STA2X11_GPIO50_SPI0_RXD 50
103#define STA2X11_GPIO51_SPI0_FRM 51
104#define STA2X11_GPIO52_SPI1_CLK 52
105#define STA2X11_GPIO53_SPI1_TXD 53
106#define STA2X11_GPIO54_SPI1_RXD 54
107#define STA2X11_GPIO55_SPI1_FRM 55
108#define STA2X11_GPIO56_SPI2_CLK 56
109#define STA2X11_GPIO57_SPI2_TXD 57
110#define STA2X11_GPIO58_SPI2_RXD 58
111#define STA2X11_GPIO59_SPI2_FRM 59
112#define STA2X11_GPIO60_I2C0_SCL 60
113#define STA2X11_GPIO61_I2C0_SDA 61
114#define STA2X11_GPIO62_I2C1_SCL 62
115#define STA2X11_GPIO63_I2C1_SDA 63
116#define STA2X11_GPIO64_I2C2_SCL 64
117#define STA2X11_GPIO65_I2C2_SDA 65
118#define STA2X11_GPIO66_I2C3_SCL 66
119#define STA2X11_GPIO67_I2C3_SDA 67
120#define STA2X11_GPIO68_MSP0_RCK 68
121#define STA2X11_GPIO69_MSP0_RXD 69
122#define STA2X11_GPIO70_MSP0_RFS 70
123#define STA2X11_GPIO71_MSP0_TCK 71
124#define STA2X11_GPIO72_MSP0_TXD 72
125#define STA2X11_GPIO73_MSP0_TFS 73
126#define STA2X11_GPIO74_MSP0_SCK 74
127#define STA2X11_GPIO75_MSP1_CK 75
128#define STA2X11_GPIO76_MSP1_RXD 76
129#define STA2X11_GPIO77_MSP1_FS 77
130#define STA2X11_GPIO78_MSP1_TXD 78
131#define STA2X11_GPIO79_MSP2_CK 79
132#define STA2X11_GPIO80_MSP2_RXD 80
133#define STA2X11_GPIO81_MSP2_FS 81
134#define STA2X11_GPIO82_MSP2_TXD 82
135#define STA2X11_GPIO83_MSP3_CK 83
136#define STA2X11_GPIO84_MSP3_RXD 84
137#define STA2X11_GPIO85_MSP3_FS 85
138#define STA2X11_GPIO86_MSP3_TXD 86
139#define STA2X11_GPIO87_MSP4_CK 87
140#define STA2X11_GPIO88_MSP4_RXD 88
141#define STA2X11_GPIO89_MSP4_FS 89
142#define STA2X11_GPIO90_MSP4_TXD 90
143#define STA2X11_GPIO91_MSP5_CK 91
144#define STA2X11_GPIO92_MSP5_RXD 92
145#define STA2X11_GPIO93_MSP5_FS 93
146#define STA2X11_GPIO94_MSP5_TXD 94
147#define STA2X11_GPIO95_SDIO3_DAT3 95
148#define STA2X11_GPIO96_SDIO3_DAT2 96
149#define STA2X11_GPIO97_SDIO3_DAT1 97
150#define STA2X11_GPIO98_SDIO3_DAT0 98
151#define STA2X11_GPIO99_SDIO3_CLK 99
152#define STA2X11_GPIO100_SDIO3_CMD 100
153#define STA2X11_GPIO101 101
154#define STA2X11_GPIO102 102
155#define STA2X11_GPIO103 103
156#define STA2X11_GPIO104 104
157#define STA2X11_GPIO105_SDIO2_DAT3 105
158#define STA2X11_GPIO106_SDIO2_DAT2 106
159#define STA2X11_GPIO107_SDIO2_DAT1 107
160#define STA2X11_GPIO108_SDIO2_DAT0 108
161#define STA2X11_GPIO109_SDIO2_CLK 109
162#define STA2X11_GPIO110_SDIO2_CMD 110
163#define STA2X11_GPIO111 111
164#define STA2X11_GPIO112 112
165#define STA2X11_GPIO113 113
166#define STA2X11_GPIO114 114
167#define STA2X11_GPIO115_SDIO1_DAT3 115
168#define STA2X11_GPIO116_SDIO1_DAT2 116
169#define STA2X11_GPIO117_SDIO1_DAT1 117
170#define STA2X11_GPIO118_SDIO1_DAT0 118
171#define STA2X11_GPIO119_SDIO1_CLK 119
172#define STA2X11_GPIO120_SDIO1_CMD 120
173#define STA2X11_GPIO121 121
174#define STA2X11_GPIO122 122
175#define STA2X11_GPIO123 123
176#define STA2X11_GPIO124 124
177#define STA2X11_GPIO125_UART2_TXD 125
178#define STA2X11_GPIO126_UART2_RXD 126
179#define STA2X11_GPIO127_UART3_TXD 127
180
181/*
182 * The APB bridge has its own registers, needed by our users as well.
183 * They are accessed with the following read/mask/write function.
184 */
185u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
186
187/* CAN and MLB */
188#define APBREG_BSR 0x00 /* Bridge Status Reg */
189#define APBREG_PAER 0x08 /* Peripherals Address Error Reg */
190#define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
191#define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
192#define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
193#define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
194#define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
195
196#define APBREG_CAN (1 << 1)
197#define APBREG_MLB (1 << 3)
198
199/* SARAC */
200#define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */
201#define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */
202#define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
203#define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
204#define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
205#define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
206#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
207
208#define APBREG_SARAC (1 << 2)
209
210/*
211 * The system controller has its own registers. Some of these are accessed
212 * by out users as well, using the following read/mask/write/function
213 */
214u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
215
216#define SCTL_SCCTL 0x00 /* System controller control register */
217#define SCTL_ARMCFG 0x04 /* ARM configuration register */
218#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
219#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
220#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
221#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
222#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
223#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
224#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
225#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
226#define SCTL_SCGRST 0x28 /* Peripheral global reset */
227#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
228#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
229#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
230#define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */
231#define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */
232#define SCTL_SCINTREN 0x44 /* Interrupt enable */
233#define SCTL_SCRISR 0x48 /* RAW interrupt status */
234#define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
235#define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
236#define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */
237#define SCTL_SCRSTSTA 0x58 /* Reset status register */
238
239#define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0)
240#define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
241#define SCTL_SCRESCTRL1_USB_HRST (1 << 2)
242#define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3)
243#define SCTL_SCRESCTRL1_SATAII (1 << 4)
244#define SCTL_SCRESCTRL1_VIP (1 << 5)
245#define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6)
246#define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7)
247#define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8)
248#define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9)
249#define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10)
250#define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11)
251#define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12)
252#define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13)
253#define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14)
254#define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15)
255#define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16)
256#define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17)
257#define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18)
258#define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19)
259#define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20)
260#define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21)
261#define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22)
262#define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23)
263#define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24)
264#define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25)
265#define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26)
266#define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27)
267#define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
268#define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29)
269#define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30)
270#define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31)
271
272#define SCTL_SCPEREN0_UART0 (1 << 0)
273#define SCTL_SCPEREN0_UART1 (1 << 1)
274#define SCTL_SCPEREN0_UART2 (1 << 2)
275#define SCTL_SCPEREN0_UART3 (1 << 3)
276#define SCTL_SCPEREN0_MSP0 (1 << 4)
277#define SCTL_SCPEREN0_MSP1 (1 << 5)
278#define SCTL_SCPEREN0_MSP2 (1 << 6)
279#define SCTL_SCPEREN0_MSP3 (1 << 7)
280#define SCTL_SCPEREN0_MSP4 (1 << 8)
281#define SCTL_SCPEREN0_MSP5 (1 << 9)
282#define SCTL_SCPEREN0_SPI0 (1 << 10)
283#define SCTL_SCPEREN0_SPI1 (1 << 11)
284#define SCTL_SCPEREN0_SPI2 (1 << 12)
285#define SCTL_SCPEREN0_I2C0 (1 << 13)
286#define SCTL_SCPEREN0_I2C1 (1 << 14)
287#define SCTL_SCPEREN0_I2C2 (1 << 15)
288#define SCTL_SCPEREN0_I2C3 (1 << 16)
289#define SCTL_SCPEREN0_SVDO_LVDS (1 << 17)
290#define SCTL_SCPEREN0_USB_HOST (1 << 18)
291#define SCTL_SCPEREN0_USB_OTG (1 << 19)
292#define SCTL_SCPEREN0_MCI0 (1 << 20)
293#define SCTL_SCPEREN0_MCI1 (1 << 21)
294#define SCTL_SCPEREN0_MCI2 (1 << 22)
295#define SCTL_SCPEREN0_MCI3 (1 << 23)
296#define SCTL_SCPEREN0_SATA (1 << 24)
297#define SCTL_SCPEREN0_ETHERNET (1 << 25)
298#define SCTL_SCPEREN0_VIC (1 << 26)
299#define SCTL_SCPEREN0_DMA_AUDIO (1 << 27)
300#define SCTL_SCPEREN0_DMA_SOC (1 << 28)
301#define SCTL_SCPEREN0_RAM (1 << 29)
302#define SCTL_SCPEREN0_VIP (1 << 30)
303#define SCTL_SCPEREN0_ARM (1 << 31)
304
305#define SCTL_SCPEREN1_UART0 (1 << 0)
306#define SCTL_SCPEREN1_UART1 (1 << 1)
307#define SCTL_SCPEREN1_UART2 (1 << 2)
308#define SCTL_SCPEREN1_UART3 (1 << 3)
309#define SCTL_SCPEREN1_MSP0 (1 << 4)
310#define SCTL_SCPEREN1_MSP1 (1 << 5)
311#define SCTL_SCPEREN1_MSP2 (1 << 6)
312#define SCTL_SCPEREN1_MSP3 (1 << 7)
313#define SCTL_SCPEREN1_MSP4 (1 << 8)
314#define SCTL_SCPEREN1_MSP5 (1 << 9)
315#define SCTL_SCPEREN1_SPI0 (1 << 10)
316#define SCTL_SCPEREN1_SPI1 (1 << 11)
317#define SCTL_SCPEREN1_SPI2 (1 << 12)
318#define SCTL_SCPEREN1_I2C0 (1 << 13)
319#define SCTL_SCPEREN1_I2C1 (1 << 14)
320#define SCTL_SCPEREN1_I2C2 (1 << 15)
321#define SCTL_SCPEREN1_I2C3 (1 << 16)
322#define SCTL_SCPEREN1_USB_PHY (1 << 17)
323
324#endif /* __STA2X11_MFD_H */