tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/video/omap2/dss/dss_features.c
3 *
4 * Copyright (C) 2010 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <linux/kernel.h>
21#include <linux/types.h>
22#include <linux/err.h>
23#include <linux/slab.h>
24
25#include <video/omapdss.h>
26#include <plat/cpu.h>
27
28#include "dss.h"
29#include "dss_features.h"
30
31/* Defines a generic omap register field */
32struct dss_reg_field {
33 u8 start, end;
34};
35
36struct dss_param_range {
37 int min, max;
38};
39
40struct omap_dss_features {
41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields;
43
44 const enum dss_feat_id *features;
45 const int num_features;
46
47 const int num_mgrs;
48 const int num_ovls;
49 const enum omap_display_type *supported_displays;
50 const enum omap_color_mode *supported_color_modes;
51 const enum omap_overlay_caps *overlay_caps;
52 const char * const *clksrc_names;
53 const struct dss_param_range *dss_params;
54
55 const enum omap_dss_rotation_type supported_rotation_types;
56
57 const u32 buffer_size_unit;
58 const u32 burst_size_unit;
59};
60
61/* This struct is assigned to one of the below during initialization */
62static const struct omap_dss_features *omap_current_dss_features;
63
64static const struct dss_reg_field omap2_dss_reg_fields[] = {
65 [FEAT_REG_FIRHINC] = { 11, 0 },
66 [FEAT_REG_FIRVINC] = { 27, 16 },
67 [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 },
68 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 },
69 [FEAT_REG_FIFOSIZE] = { 8, 0 },
70 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
71 [FEAT_REG_VERTICALACCU] = { 25, 16 },
72 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
73 [FEAT_REG_DSIPLL_REGN] = { 0, 0 },
74 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },
75 [FEAT_REG_DSIPLL_REGM_DISPC] = { 0, 0 },
76 [FEAT_REG_DSIPLL_REGM_DSI] = { 0, 0 },
77};
78
79static const struct dss_reg_field omap3_dss_reg_fields[] = {
80 [FEAT_REG_FIRHINC] = { 12, 0 },
81 [FEAT_REG_FIRVINC] = { 28, 16 },
82 [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 },
83 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 },
84 [FEAT_REG_FIFOSIZE] = { 10, 0 },
85 [FEAT_REG_HORIZONTALACCU] = { 9, 0 },
86 [FEAT_REG_VERTICALACCU] = { 25, 16 },
87 [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 },
88 [FEAT_REG_DSIPLL_REGN] = { 7, 1 },
89 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },
90 [FEAT_REG_DSIPLL_REGM_DISPC] = { 22, 19 },
91 [FEAT_REG_DSIPLL_REGM_DSI] = { 26, 23 },
92};
93
94static const struct dss_reg_field omap4_dss_reg_fields[] = {
95 [FEAT_REG_FIRHINC] = { 12, 0 },
96 [FEAT_REG_FIRVINC] = { 28, 16 },
97 [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 },
98 [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 },
99 [FEAT_REG_FIFOSIZE] = { 15, 0 },
100 [FEAT_REG_HORIZONTALACCU] = { 10, 0 },
101 [FEAT_REG_VERTICALACCU] = { 26, 16 },
102 [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 },
103 [FEAT_REG_DSIPLL_REGN] = { 8, 1 },
104 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
105 [FEAT_REG_DSIPLL_REGM_DISPC] = { 25, 21 },
106 [FEAT_REG_DSIPLL_REGM_DSI] = { 30, 26 },
107};
108
109static const enum omap_display_type omap2_dss_supported_displays[] = {
110 /* OMAP_DSS_CHANNEL_LCD */
111 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI,
112
113 /* OMAP_DSS_CHANNEL_DIGIT */
114 OMAP_DISPLAY_TYPE_VENC,
115};
116
117static const enum omap_display_type omap3430_dss_supported_displays[] = {
118 /* OMAP_DSS_CHANNEL_LCD */
119 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
120 OMAP_DISPLAY_TYPE_SDI | OMAP_DISPLAY_TYPE_DSI,
121
122 /* OMAP_DSS_CHANNEL_DIGIT */
123 OMAP_DISPLAY_TYPE_VENC,
124};
125
126static const enum omap_display_type omap3630_dss_supported_displays[] = {
127 /* OMAP_DSS_CHANNEL_LCD */
128 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
129 OMAP_DISPLAY_TYPE_DSI,
130
131 /* OMAP_DSS_CHANNEL_DIGIT */
132 OMAP_DISPLAY_TYPE_VENC,
133};
134
135static const enum omap_display_type omap4_dss_supported_displays[] = {
136 /* OMAP_DSS_CHANNEL_LCD */
137 OMAP_DISPLAY_TYPE_DBI | OMAP_DISPLAY_TYPE_DSI,
138
139 /* OMAP_DSS_CHANNEL_DIGIT */
140 OMAP_DISPLAY_TYPE_VENC | OMAP_DISPLAY_TYPE_HDMI,
141
142 /* OMAP_DSS_CHANNEL_LCD2 */
143 OMAP_DISPLAY_TYPE_DPI | OMAP_DISPLAY_TYPE_DBI |
144 OMAP_DISPLAY_TYPE_DSI,
145};
146
147static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
148 /* OMAP_DSS_GFX */
149 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
150 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
151 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
152 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P,
153
154 /* OMAP_DSS_VIDEO1 */
155 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
156 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
157 OMAP_DSS_COLOR_UYVY,
158
159 /* OMAP_DSS_VIDEO2 */
160 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
161 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
162 OMAP_DSS_COLOR_UYVY,
163};
164
165static const enum omap_color_mode omap3_dss_supported_color_modes[] = {
166 /* OMAP_DSS_GFX */
167 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
168 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
169 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
170 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
171 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
172 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
173
174 /* OMAP_DSS_VIDEO1 */
175 OMAP_DSS_COLOR_RGB24U | OMAP_DSS_COLOR_RGB24P |
176 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_RGB16 |
177 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_UYVY,
178
179 /* OMAP_DSS_VIDEO2 */
180 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
181 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
182 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_YUV2 |
183 OMAP_DSS_COLOR_UYVY | OMAP_DSS_COLOR_ARGB32 |
184 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
185};
186
187static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
188 /* OMAP_DSS_GFX */
189 OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
190 OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
191 OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
192 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
193 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
194 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
195 OMAP_DSS_COLOR_ARGB16_1555 | OMAP_DSS_COLOR_RGBX16 |
196 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_XRGB16_1555,
197
198 /* OMAP_DSS_VIDEO1 */
199 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
200 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
201 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
202 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
203 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
204 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
205 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
206 OMAP_DSS_COLOR_RGBX32,
207
208 /* OMAP_DSS_VIDEO2 */
209 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
210 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
211 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
212 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
213 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
214 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
215 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
216 OMAP_DSS_COLOR_RGBX32,
217
218 /* OMAP_DSS_VIDEO3 */
219 OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
220 OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
221 OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
222 OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
223 OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
224 OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
225 OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
226 OMAP_DSS_COLOR_RGBX32,
227};
228
229static const enum omap_overlay_caps omap2_dss_overlay_caps[] = {
230 /* OMAP_DSS_GFX */
231 0,
232
233 /* OMAP_DSS_VIDEO1 */
234 OMAP_DSS_OVL_CAP_SCALE,
235
236 /* OMAP_DSS_VIDEO2 */
237 OMAP_DSS_OVL_CAP_SCALE,
238};
239
240static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = {
241 /* OMAP_DSS_GFX */
242 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
243
244 /* OMAP_DSS_VIDEO1 */
245 OMAP_DSS_OVL_CAP_SCALE,
246
247 /* OMAP_DSS_VIDEO2 */
248 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA,
249};
250
251static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = {
252 /* OMAP_DSS_GFX */
253 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
254
255 /* OMAP_DSS_VIDEO1 */
256 OMAP_DSS_OVL_CAP_SCALE,
257
258 /* OMAP_DSS_VIDEO2 */
259 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
260 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA,
261};
262
263static const enum omap_overlay_caps omap4_dss_overlay_caps[] = {
264 /* OMAP_DSS_GFX */
265 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA |
266 OMAP_DSS_OVL_CAP_ZORDER,
267
268 /* OMAP_DSS_VIDEO1 */
269 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
270 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
271
272 /* OMAP_DSS_VIDEO2 */
273 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
274 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
275
276 /* OMAP_DSS_VIDEO3 */
277 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA |
278 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER,
279};
280
281static const char * const omap2_dss_clk_source_names[] = {
282 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
283 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
284 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
285};
286
287static const char * const omap3_dss_clk_source_names[] = {
288 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
289 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
290 [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
291};
292
293static const char * const omap4_dss_clk_source_names[] = {
294 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
295 [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
296 [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
297 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
298 [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
299};
300
301static const struct dss_param_range omap2_dss_param_range[] = {
302 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
303 [FEAT_PARAM_DSS_PCD] = { 2, 255 },
304 [FEAT_PARAM_DSIPLL_REGN] = { 0, 0 },
305 [FEAT_PARAM_DSIPLL_REGM] = { 0, 0 },
306 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, 0 },
307 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, 0 },
308 [FEAT_PARAM_DSIPLL_FINT] = { 0, 0 },
309 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, 0 },
310 [FEAT_PARAM_DOWNSCALE] = { 1, 2 },
311 /*
312 * Assuming the line width buffer to be 768 pixels as OMAP2 DISPC
313 * scaler cannot scale a image with width more than 768.
314 */
315 [FEAT_PARAM_LINEWIDTH] = { 1, 768 },
316 [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
317 [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
318};
319
320static const struct dss_param_range omap3_dss_param_range[] = {
321 [FEAT_PARAM_DSS_FCK] = { 0, 173000000 },
322 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
323 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 7) - 1 },
324 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 11) - 1 },
325 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 4) - 1 },
326 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 4) - 1 },
327 [FEAT_PARAM_DSIPLL_FINT] = { 750000, 2100000 },
328 [FEAT_PARAM_DSIPLL_LPDIV] = { 1, (1 << 13) - 1},
329 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
330 [FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
331 [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
332 [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
333};
334
335static const struct dss_param_range omap4_dss_param_range[] = {
336 [FEAT_PARAM_DSS_FCK] = { 0, 186000000 },
337 [FEAT_PARAM_DSS_PCD] = { 1, 255 },
338 [FEAT_PARAM_DSIPLL_REGN] = { 0, (1 << 8) - 1 },
339 [FEAT_PARAM_DSIPLL_REGM] = { 0, (1 << 12) - 1 },
340 [FEAT_PARAM_DSIPLL_REGM_DISPC] = { 0, (1 << 5) - 1 },
341 [FEAT_PARAM_DSIPLL_REGM_DSI] = { 0, (1 << 5) - 1 },
342 [FEAT_PARAM_DSIPLL_FINT] = { 500000, 2500000 },
343 [FEAT_PARAM_DSIPLL_LPDIV] = { 0, (1 << 13) - 1 },
344 [FEAT_PARAM_DOWNSCALE] = { 1, 4 },
345 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
346 [FEAT_PARAM_MGR_WIDTH] = { 1, 2048 },
347 [FEAT_PARAM_MGR_HEIGHT] = { 1, 2048 },
348};
349
350static const enum dss_feat_id omap2_dss_feat_list[] = {
351 FEAT_LCDENABLEPOL,
352 FEAT_LCDENABLESIGNAL,
353 FEAT_PCKFREEENABLE,
354 FEAT_FUNCGATED,
355 FEAT_ROWREPEATENABLE,
356 FEAT_RESIZECONF,
357};
358
359static const enum dss_feat_id omap3430_dss_feat_list[] = {
360 FEAT_LCDENABLEPOL,
361 FEAT_LCDENABLESIGNAL,
362 FEAT_PCKFREEENABLE,
363 FEAT_FUNCGATED,
364 FEAT_LINEBUFFERSPLIT,
365 FEAT_ROWREPEATENABLE,
366 FEAT_RESIZECONF,
367 FEAT_DSI_PLL_FREQSEL,
368 FEAT_DSI_REVERSE_TXCLKESC,
369 FEAT_VENC_REQUIRES_TV_DAC_CLK,
370 FEAT_CPR,
371 FEAT_PRELOAD,
372 FEAT_FIR_COEF_V,
373 FEAT_ALPHA_FIXED_ZORDER,
374 FEAT_FIFO_MERGE,
375 FEAT_OMAP3_DSI_FIFO_BUG,
376};
377
378static const enum dss_feat_id omap3630_dss_feat_list[] = {
379 FEAT_LCDENABLEPOL,
380 FEAT_LCDENABLESIGNAL,
381 FEAT_PCKFREEENABLE,
382 FEAT_FUNCGATED,
383 FEAT_LINEBUFFERSPLIT,
384 FEAT_ROWREPEATENABLE,
385 FEAT_RESIZECONF,
386 FEAT_DSI_PLL_PWR_BUG,
387 FEAT_DSI_PLL_FREQSEL,
388 FEAT_CPR,
389 FEAT_PRELOAD,
390 FEAT_FIR_COEF_V,
391 FEAT_ALPHA_FIXED_ZORDER,
392 FEAT_FIFO_MERGE,
393 FEAT_OMAP3_DSI_FIFO_BUG,
394};
395
396static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
397 FEAT_MGR_LCD2,
398 FEAT_CORE_CLK_DIV,
399 FEAT_LCD_CLK_SRC,
400 FEAT_DSI_DCS_CMD_CONFIG_VC,
401 FEAT_DSI_VC_OCP_WIDTH,
402 FEAT_DSI_GNQ,
403 FEAT_HANDLE_UV_SEPARATE,
404 FEAT_ATTR2,
405 FEAT_CPR,
406 FEAT_PRELOAD,
407 FEAT_FIR_COEF_V,
408 FEAT_ALPHA_FREE_ZORDER,
409 FEAT_FIFO_MERGE,
410 FEAT_BURST_2D,
411};
412
413static const enum dss_feat_id omap4430_es2_0_1_2_dss_feat_list[] = {
414 FEAT_MGR_LCD2,
415 FEAT_CORE_CLK_DIV,
416 FEAT_LCD_CLK_SRC,
417 FEAT_DSI_DCS_CMD_CONFIG_VC,
418 FEAT_DSI_VC_OCP_WIDTH,
419 FEAT_DSI_GNQ,
420 FEAT_HDMI_CTS_SWMODE,
421 FEAT_HANDLE_UV_SEPARATE,
422 FEAT_ATTR2,
423 FEAT_CPR,
424 FEAT_PRELOAD,
425 FEAT_FIR_COEF_V,
426 FEAT_ALPHA_FREE_ZORDER,
427 FEAT_FIFO_MERGE,
428 FEAT_BURST_2D,
429};
430
431static const enum dss_feat_id omap4_dss_feat_list[] = {
432 FEAT_MGR_LCD2,
433 FEAT_CORE_CLK_DIV,
434 FEAT_LCD_CLK_SRC,
435 FEAT_DSI_DCS_CMD_CONFIG_VC,
436 FEAT_DSI_VC_OCP_WIDTH,
437 FEAT_DSI_GNQ,
438 FEAT_HDMI_CTS_SWMODE,
439 FEAT_HDMI_AUDIO_USE_MCLK,
440 FEAT_HANDLE_UV_SEPARATE,
441 FEAT_ATTR2,
442 FEAT_CPR,
443 FEAT_PRELOAD,
444 FEAT_FIR_COEF_V,
445 FEAT_ALPHA_FREE_ZORDER,
446 FEAT_FIFO_MERGE,
447 FEAT_BURST_2D,
448};
449
450/* OMAP2 DSS Features */
451static const struct omap_dss_features omap2_dss_features = {
452 .reg_fields = omap2_dss_reg_fields,
453 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
454
455 .features = omap2_dss_feat_list,
456 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
457
458 .num_mgrs = 2,
459 .num_ovls = 3,
460 .supported_displays = omap2_dss_supported_displays,
461 .supported_color_modes = omap2_dss_supported_color_modes,
462 .overlay_caps = omap2_dss_overlay_caps,
463 .clksrc_names = omap2_dss_clk_source_names,
464 .dss_params = omap2_dss_param_range,
465 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
466 .buffer_size_unit = 1,
467 .burst_size_unit = 8,
468};
469
470/* OMAP3 DSS Features */
471static const struct omap_dss_features omap3430_dss_features = {
472 .reg_fields = omap3_dss_reg_fields,
473 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
474
475 .features = omap3430_dss_feat_list,
476 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
477
478 .num_mgrs = 2,
479 .num_ovls = 3,
480 .supported_displays = omap3430_dss_supported_displays,
481 .supported_color_modes = omap3_dss_supported_color_modes,
482 .overlay_caps = omap3430_dss_overlay_caps,
483 .clksrc_names = omap3_dss_clk_source_names,
484 .dss_params = omap3_dss_param_range,
485 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
486 .buffer_size_unit = 1,
487 .burst_size_unit = 8,
488};
489
490static const struct omap_dss_features omap3630_dss_features = {
491 .reg_fields = omap3_dss_reg_fields,
492 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
493
494 .features = omap3630_dss_feat_list,
495 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
496
497 .num_mgrs = 2,
498 .num_ovls = 3,
499 .supported_displays = omap3630_dss_supported_displays,
500 .supported_color_modes = omap3_dss_supported_color_modes,
501 .overlay_caps = omap3630_dss_overlay_caps,
502 .clksrc_names = omap3_dss_clk_source_names,
503 .dss_params = omap3_dss_param_range,
504 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB,
505 .buffer_size_unit = 1,
506 .burst_size_unit = 8,
507};
508
509/* OMAP4 DSS Features */
510/* For OMAP4430 ES 1.0 revision */
511static const struct omap_dss_features omap4430_es1_0_dss_features = {
512 .reg_fields = omap4_dss_reg_fields,
513 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
514
515 .features = omap4430_es1_0_dss_feat_list,
516 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
517
518 .num_mgrs = 3,
519 .num_ovls = 4,
520 .supported_displays = omap4_dss_supported_displays,
521 .supported_color_modes = omap4_dss_supported_color_modes,
522 .overlay_caps = omap4_dss_overlay_caps,
523 .clksrc_names = omap4_dss_clk_source_names,
524 .dss_params = omap4_dss_param_range,
525 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
526 .buffer_size_unit = 16,
527 .burst_size_unit = 16,
528};
529
530/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
531static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
532 .reg_fields = omap4_dss_reg_fields,
533 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
534
535 .features = omap4430_es2_0_1_2_dss_feat_list,
536 .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list),
537
538 .num_mgrs = 3,
539 .num_ovls = 4,
540 .supported_displays = omap4_dss_supported_displays,
541 .supported_color_modes = omap4_dss_supported_color_modes,
542 .overlay_caps = omap4_dss_overlay_caps,
543 .clksrc_names = omap4_dss_clk_source_names,
544 .dss_params = omap4_dss_param_range,
545 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
546 .buffer_size_unit = 16,
547 .burst_size_unit = 16,
548};
549
550/* For all the other OMAP4 versions */
551static const struct omap_dss_features omap4_dss_features = {
552 .reg_fields = omap4_dss_reg_fields,
553 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
554
555 .features = omap4_dss_feat_list,
556 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
557
558 .num_mgrs = 3,
559 .num_ovls = 4,
560 .supported_displays = omap4_dss_supported_displays,
561 .supported_color_modes = omap4_dss_supported_color_modes,
562 .overlay_caps = omap4_dss_overlay_caps,
563 .clksrc_names = omap4_dss_clk_source_names,
564 .dss_params = omap4_dss_param_range,
565 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
566 .buffer_size_unit = 16,
567 .burst_size_unit = 16,
568};
569
570#if defined(CONFIG_OMAP4_DSS_HDMI)
571/* HDMI OMAP4 Functions*/
572static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
573
574 .video_configure = ti_hdmi_4xxx_basic_configure,
575 .phy_enable = ti_hdmi_4xxx_phy_enable,
576 .phy_disable = ti_hdmi_4xxx_phy_disable,
577 .read_edid = ti_hdmi_4xxx_read_edid,
578 .detect = ti_hdmi_4xxx_detect,
579 .pll_enable = ti_hdmi_4xxx_pll_enable,
580 .pll_disable = ti_hdmi_4xxx_pll_disable,
581 .video_enable = ti_hdmi_4xxx_wp_video_start,
582 .video_disable = ti_hdmi_4xxx_wp_video_stop,
583 .dump_wrapper = ti_hdmi_4xxx_wp_dump,
584 .dump_core = ti_hdmi_4xxx_core_dump,
585 .dump_pll = ti_hdmi_4xxx_pll_dump,
586 .dump_phy = ti_hdmi_4xxx_phy_dump,
587#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
588 .audio_enable = ti_hdmi_4xxx_wp_audio_enable,
589 .audio_disable = ti_hdmi_4xxx_wp_audio_disable,
590 .audio_start = ti_hdmi_4xxx_audio_start,
591 .audio_stop = ti_hdmi_4xxx_audio_stop,
592 .audio_config = ti_hdmi_4xxx_audio_config,
593#endif
594
595};
596
597void dss_init_hdmi_ip_ops(struct hdmi_ip_data *ip_data)
598{
599 if (cpu_is_omap44xx())
600 ip_data->ops = &omap4_hdmi_functions;
601}
602#endif
603
604/* Functions returning values related to a DSS feature */
605int dss_feat_get_num_mgrs(void)
606{
607 return omap_current_dss_features->num_mgrs;
608}
609
610int dss_feat_get_num_ovls(void)
611{
612 return omap_current_dss_features->num_ovls;
613}
614
615unsigned long dss_feat_get_param_min(enum dss_range_param param)
616{
617 return omap_current_dss_features->dss_params[param].min;
618}
619
620unsigned long dss_feat_get_param_max(enum dss_range_param param)
621{
622 return omap_current_dss_features->dss_params[param].max;
623}
624
625enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel)
626{
627 return omap_current_dss_features->supported_displays[channel];
628}
629
630enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane)
631{
632 return omap_current_dss_features->supported_color_modes[plane];
633}
634
635enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane)
636{
637 return omap_current_dss_features->overlay_caps[plane];
638}
639
640bool dss_feat_color_mode_supported(enum omap_plane plane,
641 enum omap_color_mode color_mode)
642{
643 return omap_current_dss_features->supported_color_modes[plane] &
644 color_mode;
645}
646
647const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
648{
649 return omap_current_dss_features->clksrc_names[id];
650}
651
652u32 dss_feat_get_buffer_size_unit(void)
653{
654 return omap_current_dss_features->buffer_size_unit;
655}
656
657u32 dss_feat_get_burst_size_unit(void)
658{
659 return omap_current_dss_features->burst_size_unit;
660}
661
662/* DSS has_feature check */
663bool dss_has_feature(enum dss_feat_id id)
664{
665 int i;
666 const enum dss_feat_id *features = omap_current_dss_features->features;
667 const int num_features = omap_current_dss_features->num_features;
668
669 for (i = 0; i < num_features; i++) {
670 if (features[i] == id)
671 return true;
672 }
673
674 return false;
675}
676
677void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
678{
679 if (id >= omap_current_dss_features->num_reg_fields)
680 BUG();
681
682 *start = omap_current_dss_features->reg_fields[id].start;
683 *end = omap_current_dss_features->reg_fields[id].end;
684}
685
686bool dss_feat_rotation_type_supported(enum omap_dss_rotation_type rot_type)
687{
688 return omap_current_dss_features->supported_rotation_types & rot_type;
689}
690
691void dss_features_init(void)
692{
693 if (cpu_is_omap24xx())
694 omap_current_dss_features = &omap2_dss_features;
695 else if (cpu_is_omap3630())
696 omap_current_dss_features = &omap3630_dss_features;
697 else if (cpu_is_omap34xx())
698 omap_current_dss_features = &omap3430_dss_features;
699 else if (omap_rev() == OMAP4430_REV_ES1_0)
700 omap_current_dss_features = &omap4430_es1_0_dss_features;
701 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
702 omap_rev() == OMAP4430_REV_ES2_1 ||
703 omap_rev() == OMAP4430_REV_ES2_2)
704 omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
705 else if (cpu_is_omap44xx())
706 omap_current_dss_features = &omap4_dss_features;
707 else
708 DSSWARN("Unsupported OMAP version");
709}