Linux kernel mirror (for testing)
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1/*
2 * Copyright 2011 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16#ifndef _ASM_TILE_PGTABLE_64_H
17#define _ASM_TILE_PGTABLE_64_H
18
19/* The level-0 page table breaks the address space into 32-bit chunks. */
20#define PGDIR_SHIFT HV_LOG2_L1_SPAN
21#define PGDIR_SIZE HV_L1_SPAN
22#define PGDIR_MASK (~(PGDIR_SIZE-1))
23#define PTRS_PER_PGD HV_L0_ENTRIES
24#define PGD_INDEX(va) HV_L0_INDEX(va)
25#define SIZEOF_PGD HV_L0_SIZE
26
27/*
28 * The level-1 index is defined by the huge page size. A PMD is composed
29 * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
30 */
31#define PMD_SHIFT HPAGE_SHIFT
32#define PMD_SIZE HPAGE_SIZE
33#define PMD_MASK (~(PMD_SIZE-1))
34#define PTRS_PER_PMD _HV_L1_ENTRIES(HPAGE_SHIFT)
35#define PMD_INDEX(va) _HV_L1_INDEX(va, HPAGE_SHIFT)
36#define SIZEOF_PMD _HV_L1_SIZE(HPAGE_SHIFT)
37
38/*
39 * The level-2 index is defined by the difference between the huge
40 * page size and the normal page size. A PTE is composed of
41 * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
42 * Note that the hypervisor docs use PTE for what we call pte_t, so
43 * this nomenclature is somewhat confusing.
44 */
45#define PTRS_PER_PTE _HV_L2_ENTRIES(HPAGE_SHIFT, PAGE_SHIFT)
46#define PTE_INDEX(va) _HV_L2_INDEX(va, HPAGE_SHIFT, PAGE_SHIFT)
47#define SIZEOF_PTE _HV_L2_SIZE(HPAGE_SHIFT, PAGE_SHIFT)
48
49/*
50 * Align the vmalloc area to an L2 page table. Omit guard pages at
51 * the beginning and end for simplicity (particularly in the per-cpu
52 * memory allocation code). The vmalloc code puts in an internal
53 * guard page between each allocation.
54 */
55#define _VMALLOC_END HUGE_VMAP_BASE
56#define VMALLOC_END _VMALLOC_END
57#define VMALLOC_START _VMALLOC_START
58
59#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
60
61#ifndef __ASSEMBLY__
62
63/* We have no pud since we are a three-level page table. */
64#include <asm-generic/pgtable-nopud.h>
65
66static inline int pud_none(pud_t pud)
67{
68 return pud_val(pud) == 0;
69}
70
71static inline int pud_present(pud_t pud)
72{
73 return pud_val(pud) & _PAGE_PRESENT;
74}
75
76#define pmd_ERROR(e) \
77 pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
78
79static inline void pud_clear(pud_t *pudp)
80{
81 __pte_clear(&pudp->pgd);
82}
83
84static inline int pud_bad(pud_t pud)
85{
86 return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
87}
88
89/* Return the page-table frame number (ptfn) that a pud_t points at. */
90#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
91
92/*
93 * A given kernel pud_t maps to a kernel pmd_t table at a specific
94 * virtual address. Since kernel pmd_t tables can be aligned at
95 * sub-page granularity, this macro can return non-page-aligned
96 * pointers, despite its name.
97 */
98#define pud_page_vaddr(pud) \
99 (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
100
101/*
102 * A pud_t points to a pmd_t array. Since we can have multiple per
103 * page, we don't have a one-to-one mapping of pud_t's to pages.
104 */
105#define pud_page(pud) pfn_to_page(PFN_DOWN(HV_PTFN_TO_CPA(pud_ptfn(pud))))
106
107static inline unsigned long pud_index(unsigned long address)
108{
109 return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
110}
111
112#define pmd_offset(pud, address) \
113 ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
114
115/* Normalize an address to having the correct high bits set. */
116#define pgd_addr_normalize pgd_addr_normalize
117static inline unsigned long pgd_addr_normalize(unsigned long addr)
118{
119 return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
120 (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
121}
122
123/* We don't define any pgds for these addresses. */
124static inline int pgd_addr_invalid(unsigned long addr)
125{
126 return addr >= MEM_HV_START ||
127 (addr > MEM_LOW_END && addr < MEM_HIGH_START);
128}
129
130/*
131 * Use atomic instructions to provide atomicity against the hypervisor.
132 */
133#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
134static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
135 unsigned long addr, pte_t *ptep)
136{
137 return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
138 HV_PTE_INDEX_ACCESSED) & 0x1;
139}
140
141#define __HAVE_ARCH_PTEP_SET_WRPROTECT
142static inline void ptep_set_wrprotect(struct mm_struct *mm,
143 unsigned long addr, pte_t *ptep)
144{
145 __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
146}
147
148#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
149static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
150 unsigned long addr, pte_t *ptep)
151{
152 return hv_pte(__insn_exch(&ptep->val, 0UL));
153}
154
155/*
156 * pmds are the same as pgds and ptes, so converting is a no-op.
157 */
158#define pmd_pte(pmd) (pmd)
159#define pmdp_ptep(pmdp) (pmdp)
160#define pte_pmd(pte) (pte)
161
162#endif /* __ASSEMBLY__ */
163
164#endif /* _ASM_TILE_PGTABLE_64_H */