tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 */
7#ifndef MFD_AB8500_H
8#define MFD_AB8500_H
9
10#include <linux/atomic.h>
11#include <linux/mutex.h>
12
13struct device;
14
15/*
16 * AB IC versions
17 *
18 * AB8500_VERSION_AB8500 should be 0xFF but will never be read as need a
19 * non-supported multi-byte I2C access via PRCMU. Set to 0x00 to ease the
20 * print of version string.
21 */
22enum ab8500_version {
23 AB8500_VERSION_AB8500 = 0x0,
24 AB8500_VERSION_AB8505 = 0x1,
25 AB8500_VERSION_AB9540 = 0x2,
26 AB8500_VERSION_AB8540 = 0x3,
27 AB8500_VERSION_UNDEFINED,
28};
29
30/* AB8500 CIDs*/
31#define AB8500_CUTEARLY 0x00
32#define AB8500_CUT1P0 0x10
33#define AB8500_CUT1P1 0x11
34#define AB8500_CUT2P0 0x20
35#define AB8500_CUT3P0 0x30
36#define AB8500_CUT3P3 0x33
37
38/*
39 * AB8500 bank addresses
40 */
41#define AB8500_SYS_CTRL1_BLOCK 0x1
42#define AB8500_SYS_CTRL2_BLOCK 0x2
43#define AB8500_REGU_CTRL1 0x3
44#define AB8500_REGU_CTRL2 0x4
45#define AB8500_USB 0x5
46#define AB8500_TVOUT 0x6
47#define AB8500_DBI 0x7
48#define AB8500_ECI_AV_ACC 0x8
49#define AB8500_RESERVED 0x9
50#define AB8500_GPADC 0xA
51#define AB8500_CHARGER 0xB
52#define AB8500_GAS_GAUGE 0xC
53#define AB8500_AUDIO 0xD
54#define AB8500_INTERRUPT 0xE
55#define AB8500_RTC 0xF
56#define AB8500_MISC 0x10
57#define AB8500_DEVELOPMENT 0x11
58#define AB8500_DEBUG 0x12
59#define AB8500_PROD_TEST 0x13
60#define AB8500_OTP_EMUL 0x15
61
62/*
63 * Interrupts
64 * Values used to index into array ab8500_irq_regoffset[] defined in
65 * drivers/mdf/ab8500-core.c
66 */
67/* Definitions for AB8500 and AB9540 */
68/* ab8500_irq_regoffset[0] -> IT[Source|Latch|Mask]1 */
69#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0 /* not 8505/9540 */
70#define AB8500_INT_UN_PLUG_TV_DET 1 /* not 8505/9540 */
71#define AB8500_INT_PLUG_TV_DET 2 /* not 8505/9540 */
72#define AB8500_INT_TEMP_WARM 3
73#define AB8500_INT_PON_KEY2DB_F 4
74#define AB8500_INT_PON_KEY2DB_R 5
75#define AB8500_INT_PON_KEY1DB_F 6
76#define AB8500_INT_PON_KEY1DB_R 7
77/* ab8500_irq_regoffset[1] -> IT[Source|Latch|Mask]2 */
78#define AB8500_INT_BATT_OVV 8
79#define AB8500_INT_MAIN_CH_UNPLUG_DET 10 /* not 8505 */
80#define AB8500_INT_MAIN_CH_PLUG_DET 11 /* not 8505 */
81#define AB8500_INT_VBUS_DET_F 14
82#define AB8500_INT_VBUS_DET_R 15
83/* ab8500_irq_regoffset[2] -> IT[Source|Latch|Mask]3 */
84#define AB8500_INT_VBUS_CH_DROP_END 16
85#define AB8500_INT_RTC_60S 17
86#define AB8500_INT_RTC_ALARM 18
87#define AB8500_INT_BAT_CTRL_INDB 20
88#define AB8500_INT_CH_WD_EXP 21
89#define AB8500_INT_VBUS_OVV 22
90#define AB8500_INT_MAIN_CH_DROP_END 23 /* not 8505/9540 */
91/* ab8500_irq_regoffset[3] -> IT[Source|Latch|Mask]4 */
92#define AB8500_INT_CCN_CONV_ACC 24
93#define AB8500_INT_INT_AUD 25
94#define AB8500_INT_CCEOC 26
95#define AB8500_INT_CC_INT_CALIB 27
96#define AB8500_INT_LOW_BAT_F 28
97#define AB8500_INT_LOW_BAT_R 29
98#define AB8500_INT_BUP_CHG_NOT_OK 30
99#define AB8500_INT_BUP_CHG_OK 31
100/* ab8500_irq_regoffset[4] -> IT[Source|Latch|Mask]5 */
101#define AB8500_INT_GP_HW_ADC_CONV_END 32 /* not 8505 */
102#define AB8500_INT_ACC_DETECT_1DB_F 33
103#define AB8500_INT_ACC_DETECT_1DB_R 34
104#define AB8500_INT_ACC_DETECT_22DB_F 35
105#define AB8500_INT_ACC_DETECT_22DB_R 36
106#define AB8500_INT_ACC_DETECT_21DB_F 37
107#define AB8500_INT_ACC_DETECT_21DB_R 38
108#define AB8500_INT_GP_SW_ADC_CONV_END 39
109/* ab8500_irq_regoffset[5] -> IT[Source|Latch|Mask]7 */
110#define AB8500_INT_GPIO6R 40 /* not 8505/9540 */
111#define AB8500_INT_GPIO7R 41 /* not 8505/9540 */
112#define AB8500_INT_GPIO8R 42 /* not 8505/9540 */
113#define AB8500_INT_GPIO9R 43 /* not 8505/9540 */
114#define AB8500_INT_GPIO10R 44
115#define AB8500_INT_GPIO11R 45
116#define AB8500_INT_GPIO12R 46 /* not 8505 */
117#define AB8500_INT_GPIO13R 47
118/* ab8500_irq_regoffset[6] -> IT[Source|Latch|Mask]8 */
119#define AB8500_INT_GPIO24R 48 /* not 8505 */
120#define AB8500_INT_GPIO25R 49 /* not 8505 */
121#define AB8500_INT_GPIO36R 50 /* not 8505/9540 */
122#define AB8500_INT_GPIO37R 51 /* not 8505/9540 */
123#define AB8500_INT_GPIO38R 52 /* not 8505/9540 */
124#define AB8500_INT_GPIO39R 53 /* not 8505/9540 */
125#define AB8500_INT_GPIO40R 54
126#define AB8500_INT_GPIO41R 55
127/* ab8500_irq_regoffset[7] -> IT[Source|Latch|Mask]9 */
128#define AB8500_INT_GPIO6F 56 /* not 8505/9540 */
129#define AB8500_INT_GPIO7F 57 /* not 8505/9540 */
130#define AB8500_INT_GPIO8F 58 /* not 8505/9540 */
131#define AB8500_INT_GPIO9F 59 /* not 8505/9540 */
132#define AB8500_INT_GPIO10F 60
133#define AB8500_INT_GPIO11F 61
134#define AB8500_INT_GPIO12F 62 /* not 8505 */
135#define AB8500_INT_GPIO13F 63
136/* ab8500_irq_regoffset[8] -> IT[Source|Latch|Mask]10 */
137#define AB8500_INT_GPIO24F 64 /* not 8505 */
138#define AB8500_INT_GPIO25F 65 /* not 8505 */
139#define AB8500_INT_GPIO36F 66 /* not 8505/9540 */
140#define AB8500_INT_GPIO37F 67 /* not 8505/9540 */
141#define AB8500_INT_GPIO38F 68 /* not 8505/9540 */
142#define AB8500_INT_GPIO39F 69 /* not 8505/9540 */
143#define AB8500_INT_GPIO40F 70
144#define AB8500_INT_GPIO41F 71
145/* ab8500_irq_regoffset[9] -> IT[Source|Latch|Mask]12 */
146#define AB8500_INT_ADP_SOURCE_ERROR 72
147#define AB8500_INT_ADP_SINK_ERROR 73
148#define AB8500_INT_ADP_PROBE_PLUG 74
149#define AB8500_INT_ADP_PROBE_UNPLUG 75
150#define AB8500_INT_ADP_SENSE_OFF 76
151#define AB8500_INT_USB_PHY_POWER_ERR 78
152#define AB8500_INT_USB_LINK_STATUS 79
153/* ab8500_irq_regoffset[10] -> IT[Source|Latch|Mask]19 */
154#define AB8500_INT_BTEMP_LOW 80
155#define AB8500_INT_BTEMP_LOW_MEDIUM 81
156#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
157#define AB8500_INT_BTEMP_HIGH 83
158/* ab8500_irq_regoffset[11] -> IT[Source|Latch|Mask]20 */
159#define AB8500_INT_SRP_DETECT 88
160#define AB8500_INT_USB_CHARGER_NOT_OKR 89
161#define AB8500_INT_ID_WAKEUP_R 90
162#define AB8500_INT_ID_DET_R1R 92
163#define AB8500_INT_ID_DET_R2R 93
164#define AB8500_INT_ID_DET_R3R 94
165#define AB8500_INT_ID_DET_R4R 95
166/* ab8500_irq_regoffset[12] -> IT[Source|Latch|Mask]21 */
167#define AB8500_INT_ID_WAKEUP_F 96
168#define AB8500_INT_ID_DET_R1F 98
169#define AB8500_INT_ID_DET_R2F 99
170#define AB8500_INT_ID_DET_R3F 100
171#define AB8500_INT_ID_DET_R4F 101
172#define AB8500_INT_CHAUTORESTARTAFTSEC 102
173#define AB8500_INT_CHSTOPBYSEC 103
174/* ab8500_irq_regoffset[13] -> IT[Source|Latch|Mask]22 */
175#define AB8500_INT_USB_CH_TH_PROT_F 104
176#define AB8500_INT_USB_CH_TH_PROT_R 105
177#define AB8500_INT_MAIN_CH_TH_PROT_F 106 /* not 8505/9540 */
178#define AB8500_INT_MAIN_CH_TH_PROT_R 107 /* not 8505/9540 */
179#define AB8500_INT_CHCURLIMNOHSCHIRP 109
180#define AB8500_INT_CHCURLIMHSCHIRP 110
181#define AB8500_INT_XTAL32K_KO 111
182
183/* Definitions for AB9540 */
184/* ab8500_irq_regoffset[14] -> IT[Source|Latch|Mask]13 */
185#define AB9540_INT_GPIO50R 113
186#define AB9540_INT_GPIO51R 114 /* not 8505 */
187#define AB9540_INT_GPIO52R 115
188#define AB9540_INT_GPIO53R 116
189#define AB9540_INT_GPIO54R 117 /* not 8505 */
190#define AB9540_INT_IEXT_CH_RF_BFN_R 118
191#define AB9540_INT_IEXT_CH_RF_BFN_F 119
192/* ab8500_irq_regoffset[15] -> IT[Source|Latch|Mask]14 */
193#define AB9540_INT_GPIO50F 121
194#define AB9540_INT_GPIO51F 122 /* not 8505 */
195#define AB9540_INT_GPIO52F 123
196#define AB9540_INT_GPIO53F 124
197#define AB9540_INT_GPIO54F 125 /* not 8505 */
198/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
199#define AB8505_INT_KEYSTUCK 128
200#define AB8505_INT_IKR 129
201#define AB8505_INT_IKP 130
202#define AB8505_INT_KP 131
203#define AB8505_INT_KEYDEGLITCH 132
204#define AB8505_INT_MODPWRSTATUSF 134
205#define AB8505_INT_MODPWRSTATUSR 135
206
207/*
208 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
209 * entire platform. This is a "compile time" constant so this must be set to
210 * the largest possible value that may be encountered with different AB SOCs.
211 * Of the currently supported AB devices, AB8500 and AB9540, it is the AB9540
212 * which is larger.
213 */
214#define AB8500_NR_IRQS 112
215#define AB8505_NR_IRQS 136
216#define AB9540_NR_IRQS 136
217/* This is set to the roof of any AB8500 chip variant IRQ counts */
218#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
219
220#define AB8500_NUM_IRQ_REGS 14
221#define AB9540_NUM_IRQ_REGS 17
222
223/**
224 * struct ab8500 - ab8500 internal structure
225 * @dev: parent device
226 * @lock: read/write operations lock
227 * @irq_lock: genirq bus lock
228 * @transfer_ongoing: 0 if no transfer ongoing
229 * @irq: irq line
230 * @version: chip version id (e.g. ab8500 or ab9540)
231 * @chip_id: chip revision id
232 * @write: register write
233 * @write_masked: masked register write
234 * @read: register read
235 * @rx_buf: rx buf for SPI
236 * @tx_buf: tx buf for SPI
237 * @mask: cache of IRQ regs for bus lock
238 * @oldmask: cache of previous IRQ regs for bus lock
239 * @mask_size: Actual number of valid entries in mask[], oldmask[] and
240 * irq_reg_offset
241 * @irq_reg_offset: Array of offsets into IRQ registers
242 */
243struct ab8500 {
244 struct device *dev;
245 struct mutex lock;
246 struct mutex irq_lock;
247 atomic_t transfer_ongoing;
248 int irq_base;
249 int irq;
250 enum ab8500_version version;
251 u8 chip_id;
252
253 int (*write)(struct ab8500 *ab8500, u16 addr, u8 data);
254 int (*write_masked)(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data);
255 int (*read)(struct ab8500 *ab8500, u16 addr);
256
257 unsigned long tx_buf[4];
258 unsigned long rx_buf[4];
259
260 u8 *mask;
261 u8 *oldmask;
262 int mask_size;
263 const int *irq_reg_offset;
264};
265
266struct regulator_reg_init;
267struct regulator_init_data;
268struct ab8500_gpio_platform_data;
269
270/**
271 * struct ab8500_platform_data - AB8500 platform data
272 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
273 * @init: board-specific initialization after detection of ab8500
274 * @num_regulator_reg_init: number of regulator init registers
275 * @regulator_reg_init: regulator init registers
276 * @num_regulator: number of regulators
277 * @regulator: machine-specific constraints for regulators
278 */
279struct ab8500_platform_data {
280 int irq_base;
281 void (*init) (struct ab8500 *);
282 int num_regulator_reg_init;
283 struct ab8500_regulator_reg_init *regulator_reg_init;
284 int num_regulator;
285 struct regulator_init_data *regulator;
286 struct ab8500_gpio_platform_data *gpio;
287};
288
289extern int __devinit ab8500_init(struct ab8500 *ab8500,
290 enum ab8500_version version);
291extern int __devexit ab8500_exit(struct ab8500 *ab8500);
292
293extern int ab8500_suspend(struct ab8500 *ab8500);
294
295static inline int is_ab8500(struct ab8500 *ab)
296{
297 return ab->version == AB8500_VERSION_AB8500;
298}
299
300static inline int is_ab8505(struct ab8500 *ab)
301{
302 return ab->version == AB8500_VERSION_AB8505;
303}
304
305static inline int is_ab9540(struct ab8500 *ab)
306{
307 return ab->version == AB8500_VERSION_AB9540;
308}
309
310static inline int is_ab8540(struct ab8500 *ab)
311{
312 return ab->version == AB8500_VERSION_AB8540;
313}
314
315/* exclude also ab8505, ab9540... */
316static inline int is_ab8500_1p0_or_earlier(struct ab8500 *ab)
317{
318 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P0));
319}
320
321/* exclude also ab8505, ab9540... */
322static inline int is_ab8500_1p1_or_earlier(struct ab8500 *ab)
323{
324 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT1P1));
325}
326
327/* exclude also ab8505, ab9540... */
328static inline int is_ab8500_2p0_or_earlier(struct ab8500 *ab)
329{
330 return (is_ab8500(ab) && (ab->chip_id <= AB8500_CUT2P0));
331}
332
333/* exclude also ab8505, ab9540... */
334static inline int is_ab8500_2p0(struct ab8500 *ab)
335{
336 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
337}
338
339#endif /* MFD_AB8500_H */