tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/dma-mapping.h>
20#include <linux/slab.h>
21#include <linux/device.h>
22#include <linux/mmc/host.h>
23#include <linux/scatterlist.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/pm_runtime.h>
27#include <linux/mmc/sdhci-pci-data.h>
28
29#include "sdhci.h"
30
31/*
32 * PCI device IDs
33 */
34#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
35#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
36
37/*
38 * PCI registers
39 */
40
41#define PCI_SDHCI_IFPIO 0x00
42#define PCI_SDHCI_IFDMA 0x01
43#define PCI_SDHCI_IFVENDOR 0x02
44
45#define PCI_SLOT_INFO 0x40 /* 8 bits */
46#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
47#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
48
49#define MAX_SLOTS 8
50
51struct sdhci_pci_chip;
52struct sdhci_pci_slot;
53
54struct sdhci_pci_fixes {
55 unsigned int quirks;
56 unsigned int quirks2;
57 bool allow_runtime_pm;
58
59 int (*probe) (struct sdhci_pci_chip *);
60
61 int (*probe_slot) (struct sdhci_pci_slot *);
62 void (*remove_slot) (struct sdhci_pci_slot *, int);
63
64 int (*suspend) (struct sdhci_pci_chip *);
65 int (*resume) (struct sdhci_pci_chip *);
66};
67
68struct sdhci_pci_slot {
69 struct sdhci_pci_chip *chip;
70 struct sdhci_host *host;
71 struct sdhci_pci_data *data;
72
73 int pci_bar;
74 int rst_n_gpio;
75 int cd_gpio;
76 int cd_irq;
77};
78
79struct sdhci_pci_chip {
80 struct pci_dev *pdev;
81
82 unsigned int quirks;
83 unsigned int quirks2;
84 bool allow_runtime_pm;
85 const struct sdhci_pci_fixes *fixes;
86
87 int num_slots; /* Slots on controller */
88 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
89};
90
91
92/*****************************************************************************\
93 * *
94 * Hardware specific quirk handling *
95 * *
96\*****************************************************************************/
97
98static int ricoh_probe(struct sdhci_pci_chip *chip)
99{
100 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
101 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
102 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
103 return 0;
104}
105
106static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
107{
108 slot->host->caps =
109 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
110 & SDHCI_TIMEOUT_CLK_MASK) |
111
112 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
113 & SDHCI_CLOCK_BASE_MASK) |
114
115 SDHCI_TIMEOUT_CLK_UNIT |
116 SDHCI_CAN_VDD_330 |
117 SDHCI_CAN_DO_SDMA;
118 return 0;
119}
120
121static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
122{
123 /* Apply a delay to allow controller to settle */
124 /* Otherwise it becomes confused if card state changed
125 during suspend */
126 msleep(500);
127 return 0;
128}
129
130static const struct sdhci_pci_fixes sdhci_ricoh = {
131 .probe = ricoh_probe,
132 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
133 SDHCI_QUIRK_FORCE_DMA |
134 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
135};
136
137static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
138 .probe_slot = ricoh_mmc_probe_slot,
139 .resume = ricoh_mmc_resume,
140 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
141 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
142 SDHCI_QUIRK_NO_CARD_NO_RESET |
143 SDHCI_QUIRK_MISSING_CAPS
144};
145
146static const struct sdhci_pci_fixes sdhci_ene_712 = {
147 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
148 SDHCI_QUIRK_BROKEN_DMA,
149};
150
151static const struct sdhci_pci_fixes sdhci_ene_714 = {
152 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
153 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
154 SDHCI_QUIRK_BROKEN_DMA,
155};
156
157static const struct sdhci_pci_fixes sdhci_cafe = {
158 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
159 SDHCI_QUIRK_NO_BUSY_IRQ |
160 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
161};
162
163static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
164{
165 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
166 return 0;
167}
168
169/*
170 * ADMA operation is disabled for Moorestown platform due to
171 * hardware bugs.
172 */
173static int mrst_hc_probe(struct sdhci_pci_chip *chip)
174{
175 /*
176 * slots number is fixed here for MRST as SDIO3/5 are never used and
177 * have hardware bugs.
178 */
179 chip->num_slots = 1;
180 return 0;
181}
182
183static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
184{
185 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
186 return 0;
187}
188
189#ifdef CONFIG_PM_RUNTIME
190
191static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
192{
193 struct sdhci_pci_slot *slot = dev_id;
194 struct sdhci_host *host = slot->host;
195
196 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
197 return IRQ_HANDLED;
198}
199
200static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
201{
202 int err, irq, gpio = slot->cd_gpio;
203
204 slot->cd_gpio = -EINVAL;
205 slot->cd_irq = -EINVAL;
206
207 if (!gpio_is_valid(gpio))
208 return;
209
210 err = gpio_request(gpio, "sd_cd");
211 if (err < 0)
212 goto out;
213
214 err = gpio_direction_input(gpio);
215 if (err < 0)
216 goto out_free;
217
218 irq = gpio_to_irq(gpio);
219 if (irq < 0)
220 goto out_free;
221
222 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
223 IRQF_TRIGGER_FALLING, "sd_cd", slot);
224 if (err)
225 goto out_free;
226
227 slot->cd_gpio = gpio;
228 slot->cd_irq = irq;
229
230 return;
231
232out_free:
233 gpio_free(gpio);
234out:
235 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
236}
237
238static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
239{
240 if (slot->cd_irq >= 0)
241 free_irq(slot->cd_irq, slot);
242 if (gpio_is_valid(slot->cd_gpio))
243 gpio_free(slot->cd_gpio);
244}
245
246#else
247
248static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
249{
250}
251
252static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
253{
254}
255
256#endif
257
258static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
259{
260 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
261 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
262 MMC_CAP2_HC_ERASE_SZ;
263 return 0;
264}
265
266static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
267{
268 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
269 return 0;
270}
271
272static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
273 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
274 .probe_slot = mrst_hc_probe_slot,
275};
276
277static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
278 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
279 .probe = mrst_hc_probe,
280};
281
282static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
283 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
284 .allow_runtime_pm = true,
285};
286
287static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
288 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
289 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
290 .allow_runtime_pm = true,
291 .probe_slot = mfd_sdio_probe_slot,
292};
293
294static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
295 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
296 .allow_runtime_pm = true,
297 .probe_slot = mfd_emmc_probe_slot,
298};
299
300static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
301 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
302 .probe_slot = pch_hc_probe_slot,
303};
304
305/* O2Micro extra registers */
306#define O2_SD_LOCK_WP 0xD3
307#define O2_SD_MULTI_VCC3V 0xEE
308#define O2_SD_CLKREQ 0xEC
309#define O2_SD_CAPS 0xE0
310#define O2_SD_ADMA1 0xE2
311#define O2_SD_ADMA2 0xE7
312#define O2_SD_INF_MOD 0xF1
313
314static int o2_probe(struct sdhci_pci_chip *chip)
315{
316 int ret;
317 u8 scratch;
318
319 switch (chip->pdev->device) {
320 case PCI_DEVICE_ID_O2_8220:
321 case PCI_DEVICE_ID_O2_8221:
322 case PCI_DEVICE_ID_O2_8320:
323 case PCI_DEVICE_ID_O2_8321:
324 /* This extra setup is required due to broken ADMA. */
325 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
326 if (ret)
327 return ret;
328 scratch &= 0x7f;
329 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
330
331 /* Set Multi 3 to VCC3V# */
332 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
333
334 /* Disable CLK_REQ# support after media DET */
335 ret = pci_read_config_byte(chip->pdev, O2_SD_CLKREQ, &scratch);
336 if (ret)
337 return ret;
338 scratch |= 0x20;
339 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
340
341 /* Choose capabilities, enable SDMA. We have to write 0x01
342 * to the capabilities register first to unlock it.
343 */
344 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
345 if (ret)
346 return ret;
347 scratch |= 0x01;
348 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
349 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
350
351 /* Disable ADMA1/2 */
352 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
353 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
354
355 /* Disable the infinite transfer mode */
356 ret = pci_read_config_byte(chip->pdev, O2_SD_INF_MOD, &scratch);
357 if (ret)
358 return ret;
359 scratch |= 0x08;
360 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
361
362 /* Lock WP */
363 ret = pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
364 if (ret)
365 return ret;
366 scratch |= 0x80;
367 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
368 }
369
370 return 0;
371}
372
373static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
374{
375 u8 scratch;
376 int ret;
377
378 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
379 if (ret)
380 return ret;
381
382 /*
383 * Turn PMOS on [bit 0], set over current detection to 2.4 V
384 * [bit 1:2] and enable over current debouncing [bit 6].
385 */
386 if (on)
387 scratch |= 0x47;
388 else
389 scratch &= ~0x47;
390
391 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
392 if (ret)
393 return ret;
394
395 return 0;
396}
397
398static int jmicron_probe(struct sdhci_pci_chip *chip)
399{
400 int ret;
401 u16 mmcdev = 0;
402
403 if (chip->pdev->revision == 0) {
404 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
405 SDHCI_QUIRK_32BIT_DMA_SIZE |
406 SDHCI_QUIRK_32BIT_ADMA_SIZE |
407 SDHCI_QUIRK_RESET_AFTER_REQUEST |
408 SDHCI_QUIRK_BROKEN_SMALL_PIO;
409 }
410
411 /*
412 * JMicron chips can have two interfaces to the same hardware
413 * in order to work around limitations in Microsoft's driver.
414 * We need to make sure we only bind to one of them.
415 *
416 * This code assumes two things:
417 *
418 * 1. The PCI code adds subfunctions in order.
419 *
420 * 2. The MMC interface has a lower subfunction number
421 * than the SD interface.
422 */
423 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
424 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
425 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
426 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
427
428 if (mmcdev) {
429 struct pci_dev *sd_dev;
430
431 sd_dev = NULL;
432 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
433 mmcdev, sd_dev)) != NULL) {
434 if ((PCI_SLOT(chip->pdev->devfn) ==
435 PCI_SLOT(sd_dev->devfn)) &&
436 (chip->pdev->bus == sd_dev->bus))
437 break;
438 }
439
440 if (sd_dev) {
441 pci_dev_put(sd_dev);
442 dev_info(&chip->pdev->dev, "Refusing to bind to "
443 "secondary interface.\n");
444 return -ENODEV;
445 }
446 }
447
448 /*
449 * JMicron chips need a bit of a nudge to enable the power
450 * output pins.
451 */
452 ret = jmicron_pmos(chip, 1);
453 if (ret) {
454 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
455 return ret;
456 }
457
458 /* quirk for unsable RO-detection on JM388 chips */
459 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
460 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
461 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
462
463 return 0;
464}
465
466static void jmicron_enable_mmc(struct sdhci_host *host, int on)
467{
468 u8 scratch;
469
470 scratch = readb(host->ioaddr + 0xC0);
471
472 if (on)
473 scratch |= 0x01;
474 else
475 scratch &= ~0x01;
476
477 writeb(scratch, host->ioaddr + 0xC0);
478}
479
480static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
481{
482 if (slot->chip->pdev->revision == 0) {
483 u16 version;
484
485 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
486 version = (version & SDHCI_VENDOR_VER_MASK) >>
487 SDHCI_VENDOR_VER_SHIFT;
488
489 /*
490 * Older versions of the chip have lots of nasty glitches
491 * in the ADMA engine. It's best just to avoid it
492 * completely.
493 */
494 if (version < 0xAC)
495 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
496 }
497
498 /* JM388 MMC doesn't support 1.8V while SD supports it */
499 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
500 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
501 MMC_VDD_29_30 | MMC_VDD_30_31 |
502 MMC_VDD_165_195; /* allow 1.8V */
503 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
504 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
505 }
506
507 /*
508 * The secondary interface requires a bit set to get the
509 * interrupts.
510 */
511 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
512 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
513 jmicron_enable_mmc(slot->host, 1);
514
515 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
516
517 return 0;
518}
519
520static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
521{
522 if (dead)
523 return;
524
525 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
526 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
527 jmicron_enable_mmc(slot->host, 0);
528}
529
530static int jmicron_suspend(struct sdhci_pci_chip *chip)
531{
532 int i;
533
534 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
535 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
536 for (i = 0; i < chip->num_slots; i++)
537 jmicron_enable_mmc(chip->slots[i]->host, 0);
538 }
539
540 return 0;
541}
542
543static int jmicron_resume(struct sdhci_pci_chip *chip)
544{
545 int ret, i;
546
547 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
548 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
549 for (i = 0; i < chip->num_slots; i++)
550 jmicron_enable_mmc(chip->slots[i]->host, 1);
551 }
552
553 ret = jmicron_pmos(chip, 1);
554 if (ret) {
555 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
556 return ret;
557 }
558
559 return 0;
560}
561
562static const struct sdhci_pci_fixes sdhci_o2 = {
563 .probe = o2_probe,
564};
565
566static const struct sdhci_pci_fixes sdhci_jmicron = {
567 .probe = jmicron_probe,
568
569 .probe_slot = jmicron_probe_slot,
570 .remove_slot = jmicron_remove_slot,
571
572 .suspend = jmicron_suspend,
573 .resume = jmicron_resume,
574};
575
576/* SysKonnect CardBus2SDIO extra registers */
577#define SYSKT_CTRL 0x200
578#define SYSKT_RDFIFO_STAT 0x204
579#define SYSKT_WRFIFO_STAT 0x208
580#define SYSKT_POWER_DATA 0x20c
581#define SYSKT_POWER_330 0xef
582#define SYSKT_POWER_300 0xf8
583#define SYSKT_POWER_184 0xcc
584#define SYSKT_POWER_CMD 0x20d
585#define SYSKT_POWER_START (1 << 7)
586#define SYSKT_POWER_STATUS 0x20e
587#define SYSKT_POWER_STATUS_OK (1 << 0)
588#define SYSKT_BOARD_REV 0x210
589#define SYSKT_CHIP_REV 0x211
590#define SYSKT_CONF_DATA 0x212
591#define SYSKT_CONF_DATA_1V8 (1 << 2)
592#define SYSKT_CONF_DATA_2V5 (1 << 1)
593#define SYSKT_CONF_DATA_3V3 (1 << 0)
594
595static int syskt_probe(struct sdhci_pci_chip *chip)
596{
597 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
598 chip->pdev->class &= ~0x0000FF;
599 chip->pdev->class |= PCI_SDHCI_IFDMA;
600 }
601 return 0;
602}
603
604static int syskt_probe_slot(struct sdhci_pci_slot *slot)
605{
606 int tm, ps;
607
608 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
609 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
610 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
611 "board rev %d.%d, chip rev %d.%d\n",
612 board_rev >> 4, board_rev & 0xf,
613 chip_rev >> 4, chip_rev & 0xf);
614 if (chip_rev >= 0x20)
615 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
616
617 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
618 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
619 udelay(50);
620 tm = 10; /* Wait max 1 ms */
621 do {
622 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
623 if (ps & SYSKT_POWER_STATUS_OK)
624 break;
625 udelay(100);
626 } while (--tm);
627 if (!tm) {
628 dev_err(&slot->chip->pdev->dev,
629 "power regulator never stabilized");
630 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
631 return -ENODEV;
632 }
633
634 return 0;
635}
636
637static const struct sdhci_pci_fixes sdhci_syskt = {
638 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
639 .probe = syskt_probe,
640 .probe_slot = syskt_probe_slot,
641};
642
643static int via_probe(struct sdhci_pci_chip *chip)
644{
645 if (chip->pdev->revision == 0x10)
646 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
647
648 return 0;
649}
650
651static const struct sdhci_pci_fixes sdhci_via = {
652 .probe = via_probe,
653};
654
655static const struct pci_device_id pci_ids[] __devinitdata = {
656 {
657 .vendor = PCI_VENDOR_ID_RICOH,
658 .device = PCI_DEVICE_ID_RICOH_R5C822,
659 .subvendor = PCI_ANY_ID,
660 .subdevice = PCI_ANY_ID,
661 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
662 },
663
664 {
665 .vendor = PCI_VENDOR_ID_RICOH,
666 .device = 0x843,
667 .subvendor = PCI_ANY_ID,
668 .subdevice = PCI_ANY_ID,
669 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
670 },
671
672 {
673 .vendor = PCI_VENDOR_ID_RICOH,
674 .device = 0xe822,
675 .subvendor = PCI_ANY_ID,
676 .subdevice = PCI_ANY_ID,
677 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
678 },
679
680 {
681 .vendor = PCI_VENDOR_ID_RICOH,
682 .device = 0xe823,
683 .subvendor = PCI_ANY_ID,
684 .subdevice = PCI_ANY_ID,
685 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
686 },
687
688 {
689 .vendor = PCI_VENDOR_ID_ENE,
690 .device = PCI_DEVICE_ID_ENE_CB712_SD,
691 .subvendor = PCI_ANY_ID,
692 .subdevice = PCI_ANY_ID,
693 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
694 },
695
696 {
697 .vendor = PCI_VENDOR_ID_ENE,
698 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
699 .subvendor = PCI_ANY_ID,
700 .subdevice = PCI_ANY_ID,
701 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
702 },
703
704 {
705 .vendor = PCI_VENDOR_ID_ENE,
706 .device = PCI_DEVICE_ID_ENE_CB714_SD,
707 .subvendor = PCI_ANY_ID,
708 .subdevice = PCI_ANY_ID,
709 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
710 },
711
712 {
713 .vendor = PCI_VENDOR_ID_ENE,
714 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
715 .subvendor = PCI_ANY_ID,
716 .subdevice = PCI_ANY_ID,
717 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
718 },
719
720 {
721 .vendor = PCI_VENDOR_ID_MARVELL,
722 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
723 .subvendor = PCI_ANY_ID,
724 .subdevice = PCI_ANY_ID,
725 .driver_data = (kernel_ulong_t)&sdhci_cafe,
726 },
727
728 {
729 .vendor = PCI_VENDOR_ID_JMICRON,
730 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
731 .subvendor = PCI_ANY_ID,
732 .subdevice = PCI_ANY_ID,
733 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
734 },
735
736 {
737 .vendor = PCI_VENDOR_ID_JMICRON,
738 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
739 .subvendor = PCI_ANY_ID,
740 .subdevice = PCI_ANY_ID,
741 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
742 },
743
744 {
745 .vendor = PCI_VENDOR_ID_JMICRON,
746 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
749 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
750 },
751
752 {
753 .vendor = PCI_VENDOR_ID_JMICRON,
754 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
755 .subvendor = PCI_ANY_ID,
756 .subdevice = PCI_ANY_ID,
757 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
758 },
759
760 {
761 .vendor = PCI_VENDOR_ID_SYSKONNECT,
762 .device = 0x8000,
763 .subvendor = PCI_ANY_ID,
764 .subdevice = PCI_ANY_ID,
765 .driver_data = (kernel_ulong_t)&sdhci_syskt,
766 },
767
768 {
769 .vendor = PCI_VENDOR_ID_VIA,
770 .device = 0x95d0,
771 .subvendor = PCI_ANY_ID,
772 .subdevice = PCI_ANY_ID,
773 .driver_data = (kernel_ulong_t)&sdhci_via,
774 },
775
776 {
777 .vendor = PCI_VENDOR_ID_INTEL,
778 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
779 .subvendor = PCI_ANY_ID,
780 .subdevice = PCI_ANY_ID,
781 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
782 },
783
784 {
785 .vendor = PCI_VENDOR_ID_INTEL,
786 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
787 .subvendor = PCI_ANY_ID,
788 .subdevice = PCI_ANY_ID,
789 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
790 },
791
792 {
793 .vendor = PCI_VENDOR_ID_INTEL,
794 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
795 .subvendor = PCI_ANY_ID,
796 .subdevice = PCI_ANY_ID,
797 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
798 },
799
800 {
801 .vendor = PCI_VENDOR_ID_INTEL,
802 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
803 .subvendor = PCI_ANY_ID,
804 .subdevice = PCI_ANY_ID,
805 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
806 },
807
808 {
809 .vendor = PCI_VENDOR_ID_INTEL,
810 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
811 .subvendor = PCI_ANY_ID,
812 .subdevice = PCI_ANY_ID,
813 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
814 },
815
816 {
817 .vendor = PCI_VENDOR_ID_INTEL,
818 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
819 .subvendor = PCI_ANY_ID,
820 .subdevice = PCI_ANY_ID,
821 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
822 },
823
824 {
825 .vendor = PCI_VENDOR_ID_INTEL,
826 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
827 .subvendor = PCI_ANY_ID,
828 .subdevice = PCI_ANY_ID,
829 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
830 },
831
832 {
833 .vendor = PCI_VENDOR_ID_INTEL,
834 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
835 .subvendor = PCI_ANY_ID,
836 .subdevice = PCI_ANY_ID,
837 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
838 },
839
840 {
841 .vendor = PCI_VENDOR_ID_INTEL,
842 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
843 .subvendor = PCI_ANY_ID,
844 .subdevice = PCI_ANY_ID,
845 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
846 },
847
848 {
849 .vendor = PCI_VENDOR_ID_INTEL,
850 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
851 .subvendor = PCI_ANY_ID,
852 .subdevice = PCI_ANY_ID,
853 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
854 },
855
856 {
857 .vendor = PCI_VENDOR_ID_O2,
858 .device = PCI_DEVICE_ID_O2_8120,
859 .subvendor = PCI_ANY_ID,
860 .subdevice = PCI_ANY_ID,
861 .driver_data = (kernel_ulong_t)&sdhci_o2,
862 },
863
864 {
865 .vendor = PCI_VENDOR_ID_O2,
866 .device = PCI_DEVICE_ID_O2_8220,
867 .subvendor = PCI_ANY_ID,
868 .subdevice = PCI_ANY_ID,
869 .driver_data = (kernel_ulong_t)&sdhci_o2,
870 },
871
872 {
873 .vendor = PCI_VENDOR_ID_O2,
874 .device = PCI_DEVICE_ID_O2_8221,
875 .subvendor = PCI_ANY_ID,
876 .subdevice = PCI_ANY_ID,
877 .driver_data = (kernel_ulong_t)&sdhci_o2,
878 },
879
880 {
881 .vendor = PCI_VENDOR_ID_O2,
882 .device = PCI_DEVICE_ID_O2_8320,
883 .subvendor = PCI_ANY_ID,
884 .subdevice = PCI_ANY_ID,
885 .driver_data = (kernel_ulong_t)&sdhci_o2,
886 },
887
888 {
889 .vendor = PCI_VENDOR_ID_O2,
890 .device = PCI_DEVICE_ID_O2_8321,
891 .subvendor = PCI_ANY_ID,
892 .subdevice = PCI_ANY_ID,
893 .driver_data = (kernel_ulong_t)&sdhci_o2,
894 },
895
896 { /* Generic SD host controller */
897 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
898 },
899
900 { /* end: all zeroes */ },
901};
902
903MODULE_DEVICE_TABLE(pci, pci_ids);
904
905/*****************************************************************************\
906 * *
907 * SDHCI core callbacks *
908 * *
909\*****************************************************************************/
910
911static int sdhci_pci_enable_dma(struct sdhci_host *host)
912{
913 struct sdhci_pci_slot *slot;
914 struct pci_dev *pdev;
915 int ret;
916
917 slot = sdhci_priv(host);
918 pdev = slot->chip->pdev;
919
920 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
921 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
922 (host->flags & SDHCI_USE_SDMA)) {
923 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
924 "doesn't fully claim to support it.\n");
925 }
926
927 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
928 if (ret)
929 return ret;
930
931 pci_set_master(pdev);
932
933 return 0;
934}
935
936static int sdhci_pci_8bit_width(struct sdhci_host *host, int width)
937{
938 u8 ctrl;
939
940 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
941
942 switch (width) {
943 case MMC_BUS_WIDTH_8:
944 ctrl |= SDHCI_CTRL_8BITBUS;
945 ctrl &= ~SDHCI_CTRL_4BITBUS;
946 break;
947 case MMC_BUS_WIDTH_4:
948 ctrl |= SDHCI_CTRL_4BITBUS;
949 ctrl &= ~SDHCI_CTRL_8BITBUS;
950 break;
951 default:
952 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
953 break;
954 }
955
956 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
957
958 return 0;
959}
960
961static void sdhci_pci_hw_reset(struct sdhci_host *host)
962{
963 struct sdhci_pci_slot *slot = sdhci_priv(host);
964 int rst_n_gpio = slot->rst_n_gpio;
965
966 if (!gpio_is_valid(rst_n_gpio))
967 return;
968 gpio_set_value_cansleep(rst_n_gpio, 0);
969 /* For eMMC, minimum is 1us but give it 10us for good measure */
970 udelay(10);
971 gpio_set_value_cansleep(rst_n_gpio, 1);
972 /* For eMMC, minimum is 200us but give it 300us for good measure */
973 usleep_range(300, 1000);
974}
975
976static struct sdhci_ops sdhci_pci_ops = {
977 .enable_dma = sdhci_pci_enable_dma,
978 .platform_8bit_width = sdhci_pci_8bit_width,
979 .hw_reset = sdhci_pci_hw_reset,
980};
981
982/*****************************************************************************\
983 * *
984 * Suspend/resume *
985 * *
986\*****************************************************************************/
987
988#ifdef CONFIG_PM
989
990static int sdhci_pci_suspend(struct device *dev)
991{
992 struct pci_dev *pdev = to_pci_dev(dev);
993 struct sdhci_pci_chip *chip;
994 struct sdhci_pci_slot *slot;
995 mmc_pm_flag_t slot_pm_flags;
996 mmc_pm_flag_t pm_flags = 0;
997 int i, ret;
998
999 chip = pci_get_drvdata(pdev);
1000 if (!chip)
1001 return 0;
1002
1003 for (i = 0; i < chip->num_slots; i++) {
1004 slot = chip->slots[i];
1005 if (!slot)
1006 continue;
1007
1008 ret = sdhci_suspend_host(slot->host);
1009
1010 if (ret)
1011 goto err_pci_suspend;
1012
1013 slot_pm_flags = slot->host->mmc->pm_flags;
1014 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1015 sdhci_enable_irq_wakeups(slot->host);
1016
1017 pm_flags |= slot_pm_flags;
1018 }
1019
1020 if (chip->fixes && chip->fixes->suspend) {
1021 ret = chip->fixes->suspend(chip);
1022 if (ret)
1023 goto err_pci_suspend;
1024 }
1025
1026 pci_save_state(pdev);
1027 if (pm_flags & MMC_PM_KEEP_POWER) {
1028 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ) {
1029 pci_pme_active(pdev, true);
1030 pci_enable_wake(pdev, PCI_D3hot, 1);
1031 }
1032 pci_set_power_state(pdev, PCI_D3hot);
1033 } else {
1034 pci_enable_wake(pdev, PCI_D3hot, 0);
1035 pci_disable_device(pdev);
1036 pci_set_power_state(pdev, PCI_D3hot);
1037 }
1038
1039 return 0;
1040
1041err_pci_suspend:
1042 while (--i >= 0)
1043 sdhci_resume_host(chip->slots[i]->host);
1044 return ret;
1045}
1046
1047static int sdhci_pci_resume(struct device *dev)
1048{
1049 struct pci_dev *pdev = to_pci_dev(dev);
1050 struct sdhci_pci_chip *chip;
1051 struct sdhci_pci_slot *slot;
1052 int i, ret;
1053
1054 chip = pci_get_drvdata(pdev);
1055 if (!chip)
1056 return 0;
1057
1058 pci_set_power_state(pdev, PCI_D0);
1059 pci_restore_state(pdev);
1060 ret = pci_enable_device(pdev);
1061 if (ret)
1062 return ret;
1063
1064 if (chip->fixes && chip->fixes->resume) {
1065 ret = chip->fixes->resume(chip);
1066 if (ret)
1067 return ret;
1068 }
1069
1070 for (i = 0; i < chip->num_slots; i++) {
1071 slot = chip->slots[i];
1072 if (!slot)
1073 continue;
1074
1075 ret = sdhci_resume_host(slot->host);
1076 if (ret)
1077 return ret;
1078 }
1079
1080 return 0;
1081}
1082
1083#else /* CONFIG_PM */
1084
1085#define sdhci_pci_suspend NULL
1086#define sdhci_pci_resume NULL
1087
1088#endif /* CONFIG_PM */
1089
1090#ifdef CONFIG_PM_RUNTIME
1091
1092static int sdhci_pci_runtime_suspend(struct device *dev)
1093{
1094 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1095 struct sdhci_pci_chip *chip;
1096 struct sdhci_pci_slot *slot;
1097 int i, ret;
1098
1099 chip = pci_get_drvdata(pdev);
1100 if (!chip)
1101 return 0;
1102
1103 for (i = 0; i < chip->num_slots; i++) {
1104 slot = chip->slots[i];
1105 if (!slot)
1106 continue;
1107
1108 ret = sdhci_runtime_suspend_host(slot->host);
1109
1110 if (ret)
1111 goto err_pci_runtime_suspend;
1112 }
1113
1114 if (chip->fixes && chip->fixes->suspend) {
1115 ret = chip->fixes->suspend(chip);
1116 if (ret)
1117 goto err_pci_runtime_suspend;
1118 }
1119
1120 return 0;
1121
1122err_pci_runtime_suspend:
1123 while (--i >= 0)
1124 sdhci_runtime_resume_host(chip->slots[i]->host);
1125 return ret;
1126}
1127
1128static int sdhci_pci_runtime_resume(struct device *dev)
1129{
1130 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1131 struct sdhci_pci_chip *chip;
1132 struct sdhci_pci_slot *slot;
1133 int i, ret;
1134
1135 chip = pci_get_drvdata(pdev);
1136 if (!chip)
1137 return 0;
1138
1139 if (chip->fixes && chip->fixes->resume) {
1140 ret = chip->fixes->resume(chip);
1141 if (ret)
1142 return ret;
1143 }
1144
1145 for (i = 0; i < chip->num_slots; i++) {
1146 slot = chip->slots[i];
1147 if (!slot)
1148 continue;
1149
1150 ret = sdhci_runtime_resume_host(slot->host);
1151 if (ret)
1152 return ret;
1153 }
1154
1155 return 0;
1156}
1157
1158static int sdhci_pci_runtime_idle(struct device *dev)
1159{
1160 return 0;
1161}
1162
1163#else
1164
1165#define sdhci_pci_runtime_suspend NULL
1166#define sdhci_pci_runtime_resume NULL
1167#define sdhci_pci_runtime_idle NULL
1168
1169#endif
1170
1171static const struct dev_pm_ops sdhci_pci_pm_ops = {
1172 .suspend = sdhci_pci_suspend,
1173 .resume = sdhci_pci_resume,
1174 .runtime_suspend = sdhci_pci_runtime_suspend,
1175 .runtime_resume = sdhci_pci_runtime_resume,
1176 .runtime_idle = sdhci_pci_runtime_idle,
1177};
1178
1179/*****************************************************************************\
1180 * *
1181 * Device probing/removal *
1182 * *
1183\*****************************************************************************/
1184
1185static struct sdhci_pci_slot * __devinit sdhci_pci_probe_slot(
1186 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1187 int slotno)
1188{
1189 struct sdhci_pci_slot *slot;
1190 struct sdhci_host *host;
1191 int ret, bar = first_bar + slotno;
1192
1193 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1194 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1195 return ERR_PTR(-ENODEV);
1196 }
1197
1198 if (pci_resource_len(pdev, bar) != 0x100) {
1199 dev_err(&pdev->dev, "Invalid iomem size. You may "
1200 "experience problems.\n");
1201 }
1202
1203 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1204 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1205 return ERR_PTR(-ENODEV);
1206 }
1207
1208 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1209 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1210 return ERR_PTR(-ENODEV);
1211 }
1212
1213 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1214 if (IS_ERR(host)) {
1215 dev_err(&pdev->dev, "cannot allocate host\n");
1216 return ERR_CAST(host);
1217 }
1218
1219 slot = sdhci_priv(host);
1220
1221 slot->chip = chip;
1222 slot->host = host;
1223 slot->pci_bar = bar;
1224 slot->rst_n_gpio = -EINVAL;
1225 slot->cd_gpio = -EINVAL;
1226
1227 /* Retrieve platform data if there is any */
1228 if (*sdhci_pci_get_data)
1229 slot->data = sdhci_pci_get_data(pdev, slotno);
1230
1231 if (slot->data) {
1232 if (slot->data->setup) {
1233 ret = slot->data->setup(slot->data);
1234 if (ret) {
1235 dev_err(&pdev->dev, "platform setup failed\n");
1236 goto free;
1237 }
1238 }
1239 slot->rst_n_gpio = slot->data->rst_n_gpio;
1240 slot->cd_gpio = slot->data->cd_gpio;
1241 }
1242
1243 host->hw_name = "PCI";
1244 host->ops = &sdhci_pci_ops;
1245 host->quirks = chip->quirks;
1246 host->quirks2 = chip->quirks2;
1247
1248 host->irq = pdev->irq;
1249
1250 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1251 if (ret) {
1252 dev_err(&pdev->dev, "cannot request region\n");
1253 goto cleanup;
1254 }
1255
1256 host->ioaddr = pci_ioremap_bar(pdev, bar);
1257 if (!host->ioaddr) {
1258 dev_err(&pdev->dev, "failed to remap registers\n");
1259 ret = -ENOMEM;
1260 goto release;
1261 }
1262
1263 if (chip->fixes && chip->fixes->probe_slot) {
1264 ret = chip->fixes->probe_slot(slot);
1265 if (ret)
1266 goto unmap;
1267 }
1268
1269 if (gpio_is_valid(slot->rst_n_gpio)) {
1270 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1271 gpio_direction_output(slot->rst_n_gpio, 1);
1272 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1273 } else {
1274 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1275 slot->rst_n_gpio = -EINVAL;
1276 }
1277 }
1278
1279 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1280
1281 ret = sdhci_add_host(host);
1282 if (ret)
1283 goto remove;
1284
1285 sdhci_pci_add_own_cd(slot);
1286
1287 return slot;
1288
1289remove:
1290 if (gpio_is_valid(slot->rst_n_gpio))
1291 gpio_free(slot->rst_n_gpio);
1292
1293 if (chip->fixes && chip->fixes->remove_slot)
1294 chip->fixes->remove_slot(slot, 0);
1295
1296unmap:
1297 iounmap(host->ioaddr);
1298
1299release:
1300 pci_release_region(pdev, bar);
1301
1302cleanup:
1303 if (slot->data && slot->data->cleanup)
1304 slot->data->cleanup(slot->data);
1305
1306free:
1307 sdhci_free_host(host);
1308
1309 return ERR_PTR(ret);
1310}
1311
1312static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1313{
1314 int dead;
1315 u32 scratch;
1316
1317 sdhci_pci_remove_own_cd(slot);
1318
1319 dead = 0;
1320 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1321 if (scratch == (u32)-1)
1322 dead = 1;
1323
1324 sdhci_remove_host(slot->host, dead);
1325
1326 if (gpio_is_valid(slot->rst_n_gpio))
1327 gpio_free(slot->rst_n_gpio);
1328
1329 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1330 slot->chip->fixes->remove_slot(slot, dead);
1331
1332 if (slot->data && slot->data->cleanup)
1333 slot->data->cleanup(slot->data);
1334
1335 pci_release_region(slot->chip->pdev, slot->pci_bar);
1336
1337 sdhci_free_host(slot->host);
1338}
1339
1340static void __devinit sdhci_pci_runtime_pm_allow(struct device *dev)
1341{
1342 pm_runtime_put_noidle(dev);
1343 pm_runtime_allow(dev);
1344 pm_runtime_set_autosuspend_delay(dev, 50);
1345 pm_runtime_use_autosuspend(dev);
1346 pm_suspend_ignore_children(dev, 1);
1347}
1348
1349static void __devexit sdhci_pci_runtime_pm_forbid(struct device *dev)
1350{
1351 pm_runtime_forbid(dev);
1352 pm_runtime_get_noresume(dev);
1353}
1354
1355static int __devinit sdhci_pci_probe(struct pci_dev *pdev,
1356 const struct pci_device_id *ent)
1357{
1358 struct sdhci_pci_chip *chip;
1359 struct sdhci_pci_slot *slot;
1360
1361 u8 slots, first_bar;
1362 int ret, i;
1363
1364 BUG_ON(pdev == NULL);
1365 BUG_ON(ent == NULL);
1366
1367 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1368 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1369
1370 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1371 if (ret)
1372 return ret;
1373
1374 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1375 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1376 if (slots == 0)
1377 return -ENODEV;
1378
1379 BUG_ON(slots > MAX_SLOTS);
1380
1381 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1382 if (ret)
1383 return ret;
1384
1385 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1386
1387 if (first_bar > 5) {
1388 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1389 return -ENODEV;
1390 }
1391
1392 ret = pci_enable_device(pdev);
1393 if (ret)
1394 return ret;
1395
1396 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1397 if (!chip) {
1398 ret = -ENOMEM;
1399 goto err;
1400 }
1401
1402 chip->pdev = pdev;
1403 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1404 if (chip->fixes) {
1405 chip->quirks = chip->fixes->quirks;
1406 chip->quirks2 = chip->fixes->quirks2;
1407 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1408 }
1409 chip->num_slots = slots;
1410
1411 pci_set_drvdata(pdev, chip);
1412
1413 if (chip->fixes && chip->fixes->probe) {
1414 ret = chip->fixes->probe(chip);
1415 if (ret)
1416 goto free;
1417 }
1418
1419 slots = chip->num_slots; /* Quirk may have changed this */
1420
1421 for (i = 0; i < slots; i++) {
1422 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1423 if (IS_ERR(slot)) {
1424 for (i--; i >= 0; i--)
1425 sdhci_pci_remove_slot(chip->slots[i]);
1426 ret = PTR_ERR(slot);
1427 goto free;
1428 }
1429
1430 chip->slots[i] = slot;
1431 }
1432
1433 if (chip->allow_runtime_pm)
1434 sdhci_pci_runtime_pm_allow(&pdev->dev);
1435
1436 return 0;
1437
1438free:
1439 pci_set_drvdata(pdev, NULL);
1440 kfree(chip);
1441
1442err:
1443 pci_disable_device(pdev);
1444 return ret;
1445}
1446
1447static void __devexit sdhci_pci_remove(struct pci_dev *pdev)
1448{
1449 int i;
1450 struct sdhci_pci_chip *chip;
1451
1452 chip = pci_get_drvdata(pdev);
1453
1454 if (chip) {
1455 if (chip->allow_runtime_pm)
1456 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1457
1458 for (i = 0; i < chip->num_slots; i++)
1459 sdhci_pci_remove_slot(chip->slots[i]);
1460
1461 pci_set_drvdata(pdev, NULL);
1462 kfree(chip);
1463 }
1464
1465 pci_disable_device(pdev);
1466}
1467
1468static struct pci_driver sdhci_driver = {
1469 .name = "sdhci-pci",
1470 .id_table = pci_ids,
1471 .probe = sdhci_pci_probe,
1472 .remove = __devexit_p(sdhci_pci_remove),
1473 .driver = {
1474 .pm = &sdhci_pci_pm_ops
1475 },
1476};
1477
1478/*****************************************************************************\
1479 * *
1480 * Driver init/exit *
1481 * *
1482\*****************************************************************************/
1483
1484static int __init sdhci_drv_init(void)
1485{
1486 return pci_register_driver(&sdhci_driver);
1487}
1488
1489static void __exit sdhci_drv_exit(void)
1490{
1491 pci_unregister_driver(&sdhci_driver);
1492}
1493
1494module_init(sdhci_drv_init);
1495module_exit(sdhci_drv_exit);
1496
1497MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1498MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1499MODULE_LICENSE("GPL");