tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * This file is part of wlcore
3 *
4 * Copyright (C) 2011 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22#ifndef __WLCORE_H__
23#define __WLCORE_H__
24
25#include <linux/platform_device.h>
26
27#include "wl12xx.h"
28#include "event.h"
29
30/* The maximum number of Tx descriptors in all chip families */
31#define WLCORE_MAX_TX_DESCRIPTORS 32
32
33/* forward declaration */
34struct wl1271_tx_hw_descr;
35enum wl_rx_buf_align;
36
37struct wlcore_ops {
38 int (*identify_chip)(struct wl1271 *wl);
39 int (*identify_fw)(struct wl1271 *wl);
40 int (*boot)(struct wl1271 *wl);
41 void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
42 void *buf, size_t len);
43 void (*ack_event)(struct wl1271 *wl);
44 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
45 void (*set_tx_desc_blocks)(struct wl1271 *wl,
46 struct wl1271_tx_hw_descr *desc,
47 u32 blks, u32 spare_blks);
48 void (*set_tx_desc_data_len)(struct wl1271 *wl,
49 struct wl1271_tx_hw_descr *desc,
50 struct sk_buff *skb);
51 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
52 u32 rx_desc);
53 void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
54 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
55 u32 data_len);
56 void (*tx_delayed_compl)(struct wl1271 *wl);
57 void (*tx_immediate_compl)(struct wl1271 *wl);
58 int (*hw_init)(struct wl1271 *wl);
59 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
60 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
61 struct wl12xx_vif *wlvif);
62 s8 (*get_pg_ver)(struct wl1271 *wl);
63 void (*get_mac)(struct wl1271 *wl);
64};
65
66enum wlcore_partitions {
67 PART_DOWN,
68 PART_WORK,
69 PART_BOOT,
70 PART_DRPW,
71 PART_TOP_PRCM_ELP_SOC,
72 PART_PHY_INIT,
73
74 PART_TABLE_LEN,
75};
76
77struct wlcore_partition {
78 u32 size;
79 u32 start;
80};
81
82struct wlcore_partition_set {
83 struct wlcore_partition mem;
84 struct wlcore_partition reg;
85 struct wlcore_partition mem2;
86 struct wlcore_partition mem3;
87};
88
89enum wlcore_registers {
90 /* register addresses, used with partition translation */
91 REG_ECPU_CONTROL,
92 REG_INTERRUPT_NO_CLEAR,
93 REG_INTERRUPT_ACK,
94 REG_COMMAND_MAILBOX_PTR,
95 REG_EVENT_MAILBOX_PTR,
96 REG_INTERRUPT_TRIG,
97 REG_INTERRUPT_MASK,
98 REG_PC_ON_RECOVERY,
99 REG_CHIP_ID_B,
100 REG_CMD_MBOX_ADDRESS,
101
102 /* data access memory addresses, used with partition translation */
103 REG_SLV_MEM_DATA,
104 REG_SLV_REG_DATA,
105
106 /* raw data access memory addresses */
107 REG_RAW_FW_STATUS_ADDR,
108
109 REG_TABLE_LEN,
110};
111
112struct wl1271 {
113 struct ieee80211_hw *hw;
114 bool mac80211_registered;
115
116 struct device *dev;
117
118 void *if_priv;
119
120 struct wl1271_if_operations *if_ops;
121
122 void (*set_power)(bool enable);
123 int irq;
124 int ref_clock;
125
126 spinlock_t wl_lock;
127
128 enum wl1271_state state;
129 enum wl12xx_fw_type fw_type;
130 bool plt;
131 u8 last_vif_count;
132 struct mutex mutex;
133
134 unsigned long flags;
135
136 struct wlcore_partition_set curr_part;
137
138 struct wl1271_chip chip;
139
140 int cmd_box_addr;
141
142 u8 *fw;
143 size_t fw_len;
144 void *nvs;
145 size_t nvs_len;
146
147 s8 hw_pg_ver;
148
149 /* address read from the fuse ROM */
150 u32 fuse_oui_addr;
151 u32 fuse_nic_addr;
152
153 /* we have up to 2 MAC addresses */
154 struct mac_address addresses[2];
155 int channel;
156 u8 system_hlid;
157
158 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
159 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
160 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
161 unsigned long rate_policies_map[
162 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
163
164 struct list_head wlvif_list;
165
166 u8 sta_count;
167 u8 ap_count;
168
169 struct wl1271_acx_mem_map *target_mem_map;
170
171 /* Accounting for allocated / available TX blocks on HW */
172 u32 tx_blocks_freed;
173 u32 tx_blocks_available;
174 u32 tx_allocated_blocks;
175 u32 tx_results_count;
176
177 /* Accounting for allocated / available Tx packets in HW */
178 u32 tx_pkts_freed[NUM_TX_QUEUES];
179 u32 tx_allocated_pkts[NUM_TX_QUEUES];
180
181 /* Transmitted TX packets counter for chipset interface */
182 u32 tx_packets_count;
183
184 /* Time-offset between host and chipset clocks */
185 s64 time_offset;
186
187 /* Frames scheduled for transmission, not handled yet */
188 int tx_queue_count[NUM_TX_QUEUES];
189 long stopped_queues_map;
190
191 /* Frames received, not handled yet by mac80211 */
192 struct sk_buff_head deferred_rx_queue;
193
194 /* Frames sent, not returned yet to mac80211 */
195 struct sk_buff_head deferred_tx_queue;
196
197 struct work_struct tx_work;
198 struct workqueue_struct *freezable_wq;
199
200 /* Pending TX frames */
201 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
202 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
203 int tx_frames_cnt;
204
205 /* FW Rx counter */
206 u32 rx_counter;
207
208 /* Rx memory pool address */
209 struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
210
211 /* Intermediate buffer, used for packet aggregation */
212 u8 *aggr_buf;
213
214 /* Reusable dummy packet template */
215 struct sk_buff *dummy_packet;
216
217 /* Network stack work */
218 struct work_struct netstack_work;
219
220 /* FW log buffer */
221 u8 *fwlog;
222
223 /* Number of valid bytes in the FW log buffer */
224 ssize_t fwlog_size;
225
226 /* Sysfs FW log entry readers wait queue */
227 wait_queue_head_t fwlog_waitq;
228
229 /* Hardware recovery work */
230 struct work_struct recovery_work;
231
232 /* Pointer that holds DMA-friendly block for the mailbox */
233 struct event_mailbox *mbox;
234
235 /* The mbox event mask */
236 u32 event_mask;
237
238 /* Mailbox pointers */
239 u32 mbox_ptr[2];
240
241 /* Are we currently scanning */
242 struct ieee80211_vif *scan_vif;
243 struct wl1271_scan scan;
244 struct delayed_work scan_complete_work;
245
246 /* Connection loss work */
247 struct delayed_work connection_loss_work;
248
249 bool sched_scanning;
250
251 /* The current band */
252 enum ieee80211_band band;
253
254 struct completion *elp_compl;
255 struct delayed_work elp_work;
256
257 /* in dBm */
258 int power_level;
259
260 struct wl1271_stats stats;
261
262 __le32 buffer_32;
263 u32 buffer_cmd;
264 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
265
266 struct wl_fw_status *fw_status;
267 struct wl1271_tx_hw_res_if *tx_res_if;
268
269 /* Current chipset configuration */
270 struct wlcore_conf conf;
271
272 bool sg_enabled;
273
274 bool enable_11a;
275
276 /* Most recently reported noise in dBm */
277 s8 noise;
278
279 /* bands supported by this instance of wl12xx */
280 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
281
282 int tcxo_clock;
283
284 /*
285 * wowlan trigger was configured during suspend.
286 * (currently, only "ANY" trigger is supported)
287 */
288 bool wow_enabled;
289 bool irq_wake_enabled;
290
291 /*
292 * AP-mode - links indexed by HLID. The global and broadcast links
293 * are always active.
294 */
295 struct wl1271_link links[WL12XX_MAX_LINKS];
296
297 /* AP-mode - a bitmap of links currently in PS mode according to FW */
298 u32 ap_fw_ps_map;
299
300 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
301 unsigned long ap_ps_map;
302
303 /* Quirks of specific hardware revisions */
304 unsigned int quirks;
305
306 /* Platform limitations */
307 unsigned int platform_quirks;
308
309 /* number of currently active RX BA sessions */
310 int ba_rx_session_count;
311
312 /* AP-mode - number of currently connected stations */
313 int active_sta_count;
314
315 /* last wlvif we transmitted from */
316 struct wl12xx_vif *last_wlvif;
317
318 /* work to fire when Tx is stuck */
319 struct delayed_work tx_watchdog_work;
320
321 struct wlcore_ops *ops;
322 /* pointer to the lower driver partition table */
323 const struct wlcore_partition_set *ptable;
324 /* pointer to the lower driver register table */
325 const int *rtable;
326 /* name of the firmwares to load - for PLT, single role, multi-role */
327 const char *plt_fw_name;
328 const char *sr_fw_name;
329 const char *mr_fw_name;
330
331 /* per-chip-family private structure */
332 void *priv;
333
334 /* number of TX descriptors the HW supports. */
335 u32 num_tx_desc;
336
337 /* spare Tx blocks for normal/GEM operating modes */
338 u32 normal_tx_spare;
339 u32 gem_tx_spare;
340
341 /* translate HW Tx rates to standard rate-indices */
342 const u8 **band_rate_to_idx;
343
344 /* size of table for HW rates that can be received from chip */
345 u8 hw_tx_rate_tbl_size;
346
347 /* this HW rate and below are considered HT rates for this chip */
348 u8 hw_min_ht_rate;
349
350 /* HW HT (11n) capabilities */
351 struct ieee80211_sta_ht_cap ht_cap;
352
353 /* size of the private FW status data */
354 size_t fw_status_priv_len;
355
356 /* RX Data filter rule state - enabled/disabled */
357 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
358};
359
360int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
361int __devexit wlcore_remove(struct platform_device *pdev);
362struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
363int wlcore_free_hw(struct wl1271 *wl);
364
365/* Firmware image load chunk size */
366#define CHUNK_SIZE 16384
367
368/* Quirks */
369
370/* Each RX/TX transaction requires an end-of-transaction transfer */
371#define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
372
373/* wl127x and SPI don't support SDIO block size alignment */
374#define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
375
376/* means aggregated Rx packets are aligned to a SDIO block */
377#define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
378
379/* Older firmwares did not implement the FW logger over bus feature */
380#define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
381
382/* Older firmwares use an old NVS format */
383#define WLCORE_QUIRK_LEGACY_NVS BIT(5)
384
385/* Some firmwares may not support ELP */
386#define WLCORE_QUIRK_NO_ELP BIT(6)
387
388/* TODO: move to the lower drivers when all usages are abstracted */
389#define CHIP_ID_1271_PG10 (0x4030101)
390#define CHIP_ID_1271_PG20 (0x4030111)
391#define CHIP_ID_1283_PG10 (0x05030101)
392#define CHIP_ID_1283_PG20 (0x05030111)
393
394/* TODO: move all these common registers and values elsewhere */
395#define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
396
397/* ELP register commands */
398#define ELPCTRL_WAKE_UP 0x1
399#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
400#define ELPCTRL_SLEEP 0x0
401/* ELP WLAN_READY bit */
402#define ELPCTRL_WLAN_READY 0x2
403
404/*************************************************************************
405
406 Interrupt Trigger Register (Host -> WiLink)
407
408**************************************************************************/
409
410/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
411
412/*
413 * The host sets this bit to inform the Wlan
414 * FW that a TX packet is in the XFER
415 * Buffer #0.
416 */
417#define INTR_TRIG_TX_PROC0 BIT(2)
418
419/*
420 * The host sets this bit to inform the FW
421 * that it read a packet from RX XFER
422 * Buffer #0.
423 */
424#define INTR_TRIG_RX_PROC0 BIT(3)
425
426#define INTR_TRIG_DEBUG_ACK BIT(4)
427
428#define INTR_TRIG_STATE_CHANGED BIT(5)
429
430/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
431
432/*
433 * The host sets this bit to inform the FW
434 * that it read a packet from RX XFER
435 * Buffer #1.
436 */
437#define INTR_TRIG_RX_PROC1 BIT(17)
438
439/*
440 * The host sets this bit to inform the Wlan
441 * hardware that a TX packet is in the XFER
442 * Buffer #1.
443 */
444#define INTR_TRIG_TX_PROC1 BIT(18)
445
446#define ACX_SLV_SOFT_RESET_BIT BIT(1)
447#define SOFT_RESET_MAX_TIME 1000000
448#define SOFT_RESET_STALL_TIME 1000
449
450#define ECPU_CONTROL_HALT 0x00000101
451
452#define WELP_ARM_COMMAND_VAL 0x4
453
454#endif /* __WLCORE_H__ */