tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28#include <linux/spinlock.h>
29#include <linux/ioctl.h>
30
31/* platform driver name to register */
32#define NVT_DRIVER_NAME "nuvoton-cir"
33
34/* debugging module parameter */
35static int debug;
36
37
38#define nvt_pr(level, text, ...) \
39 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
40
41#define nvt_dbg(text, ...) \
42 if (debug) \
43 printk(KERN_DEBUG \
44 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
45
46#define nvt_dbg_verbose(text, ...) \
47 if (debug > 1) \
48 printk(KERN_DEBUG \
49 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
50
51#define nvt_dbg_wake(text, ...) \
52 if (debug > 2) \
53 printk(KERN_DEBUG \
54 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
55
56
57/*
58 * Original lirc driver said min value of 76, and recommended value of 256
59 * for the buffer length, but then used 2048. Never mind that the size of the
60 * RX FIFO is 32 bytes... So I'm using 32 for RX and 256 for TX atm, but I'm
61 * not sure if maybe that TX value is off by a factor of 8 (bits vs. bytes),
62 * and I don't have TX-capable hardware to test/debug on...
63 */
64#define TX_BUF_LEN 256
65#define RX_BUF_LEN 32
66
67struct nvt_dev {
68 struct pnp_dev *pdev;
69 struct rc_dev *rdev;
70
71 spinlock_t nvt_lock;
72
73 /* for rx */
74 u8 buf[RX_BUF_LEN];
75 unsigned int pkts;
76
77 struct {
78 spinlock_t lock;
79 u8 buf[TX_BUF_LEN];
80 unsigned int buf_count;
81 unsigned int cur_buf_num;
82 wait_queue_head_t queue;
83 u8 tx_state;
84 } tx;
85
86 /* EFER Config register index/data pair */
87 u8 cr_efir;
88 u8 cr_efdr;
89
90 /* hardware I/O settings */
91 unsigned long cir_addr;
92 unsigned long cir_wake_addr;
93 int cir_irq;
94 int cir_wake_irq;
95
96 /* hardware id */
97 u8 chip_major;
98 u8 chip_minor;
99
100 /* hardware features */
101 bool hw_learning_capable;
102 bool hw_tx_capable;
103
104 /* rx settings */
105 bool learning_enabled;
106 bool carrier_detect_enabled;
107
108 /* track cir wake state */
109 u8 wake_state;
110 /* for study */
111 u8 study_state;
112 /* carrier period = 1 / frequency */
113 u32 carrier;
114};
115
116/* study states */
117#define ST_STUDY_NONE 0x0
118#define ST_STUDY_START 0x1
119#define ST_STUDY_CARRIER 0x2
120#define ST_STUDY_ALL_RECV 0x4
121
122/* wake states */
123#define ST_WAKE_NONE 0x0
124#define ST_WAKE_START 0x1
125#define ST_WAKE_FINISH 0x2
126
127/* receive states */
128#define ST_RX_WAIT_7F 0x1
129#define ST_RX_WAIT_HEAD 0x2
130#define ST_RX_WAIT_SILENT_END 0x4
131
132/* send states */
133#define ST_TX_NONE 0x0
134#define ST_TX_REQUEST 0x2
135#define ST_TX_REPLY 0x4
136
137/* buffer packet constants */
138#define BUF_PULSE_BIT 0x80
139#define BUF_LEN_MASK 0x7f
140#define BUF_REPEAT_BYTE 0x70
141#define BUF_REPEAT_MASK 0xf0
142
143/* CIR settings */
144
145/* total length of CIR and CIR WAKE */
146#define CIR_IOREG_LENGTH 0x0f
147
148/* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL (0x7d0 = 2000) */
149#define CIR_RX_LIMIT_COUNT 0x7d0
150
151/* CIR Regs */
152#define CIR_IRCON 0x00
153#define CIR_IRSTS 0x01
154#define CIR_IREN 0x02
155#define CIR_RXFCONT 0x03
156#define CIR_CP 0x04
157#define CIR_CC 0x05
158#define CIR_SLCH 0x06
159#define CIR_SLCL 0x07
160#define CIR_FIFOCON 0x08
161#define CIR_IRFIFOSTS 0x09
162#define CIR_SRXFIFO 0x0a
163#define CIR_TXFCONT 0x0b
164#define CIR_STXFIFO 0x0c
165#define CIR_FCCH 0x0d
166#define CIR_FCCL 0x0e
167#define CIR_IRFSM 0x0f
168
169/* CIR IRCON settings */
170#define CIR_IRCON_RECV 0x80
171#define CIR_IRCON_WIREN 0x40
172#define CIR_IRCON_TXEN 0x20
173#define CIR_IRCON_RXEN 0x10
174#define CIR_IRCON_WRXINV 0x08
175#define CIR_IRCON_RXINV 0x04
176
177#define CIR_IRCON_SAMPLE_PERIOD_SEL_1 0x00
178#define CIR_IRCON_SAMPLE_PERIOD_SEL_25 0x01
179#define CIR_IRCON_SAMPLE_PERIOD_SEL_50 0x02
180#define CIR_IRCON_SAMPLE_PERIOD_SEL_100 0x03
181
182/* FIXME: make this a runtime option */
183/* select sample period as 50us */
184#define CIR_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
185
186/* CIR IRSTS settings */
187#define CIR_IRSTS_RDR 0x80
188#define CIR_IRSTS_RTR 0x40
189#define CIR_IRSTS_PE 0x20
190#define CIR_IRSTS_RFO 0x10
191#define CIR_IRSTS_TE 0x08
192#define CIR_IRSTS_TTR 0x04
193#define CIR_IRSTS_TFU 0x02
194#define CIR_IRSTS_GH 0x01
195
196/* CIR IREN settings */
197#define CIR_IREN_RDR 0x80
198#define CIR_IREN_RTR 0x40
199#define CIR_IREN_PE 0x20
200#define CIR_IREN_RFO 0x10
201#define CIR_IREN_TE 0x08
202#define CIR_IREN_TTR 0x04
203#define CIR_IREN_TFU 0x02
204#define CIR_IREN_GH 0x01
205
206/* CIR FIFOCON settings */
207#define CIR_FIFOCON_TXFIFOCLR 0x80
208
209#define CIR_FIFOCON_TX_TRIGGER_LEV_31 0x00
210#define CIR_FIFOCON_TX_TRIGGER_LEV_24 0x10
211#define CIR_FIFOCON_TX_TRIGGER_LEV_16 0x20
212#define CIR_FIFOCON_TX_TRIGGER_LEV_8 0x30
213
214/* FIXME: make this a runtime option */
215/* select TX trigger level as 16 */
216#define CIR_FIFOCON_TX_TRIGGER_LEV CIR_FIFOCON_TX_TRIGGER_LEV_16
217
218#define CIR_FIFOCON_RXFIFOCLR 0x08
219
220#define CIR_FIFOCON_RX_TRIGGER_LEV_1 0x00
221#define CIR_FIFOCON_RX_TRIGGER_LEV_8 0x01
222#define CIR_FIFOCON_RX_TRIGGER_LEV_16 0x02
223#define CIR_FIFOCON_RX_TRIGGER_LEV_24 0x03
224
225/* FIXME: make this a runtime option */
226/* select RX trigger level as 24 */
227#define CIR_FIFOCON_RX_TRIGGER_LEV CIR_FIFOCON_RX_TRIGGER_LEV_24
228
229/* CIR IRFIFOSTS settings */
230#define CIR_IRFIFOSTS_IR_PENDING 0x80
231#define CIR_IRFIFOSTS_RX_GS 0x40
232#define CIR_IRFIFOSTS_RX_FTA 0x20
233#define CIR_IRFIFOSTS_RX_EMPTY 0x10
234#define CIR_IRFIFOSTS_RX_FULL 0x08
235#define CIR_IRFIFOSTS_TX_FTA 0x04
236#define CIR_IRFIFOSTS_TX_EMPTY 0x02
237#define CIR_IRFIFOSTS_TX_FULL 0x01
238
239
240/* CIR WAKE UP Regs */
241#define CIR_WAKE_IRCON 0x00
242#define CIR_WAKE_IRSTS 0x01
243#define CIR_WAKE_IREN 0x02
244#define CIR_WAKE_FIFO_CMP_DEEP 0x03
245#define CIR_WAKE_FIFO_CMP_TOL 0x04
246#define CIR_WAKE_FIFO_COUNT 0x05
247#define CIR_WAKE_SLCH 0x06
248#define CIR_WAKE_SLCL 0x07
249#define CIR_WAKE_FIFOCON 0x08
250#define CIR_WAKE_SRXFSTS 0x09
251#define CIR_WAKE_SAMPLE_RX_FIFO 0x0a
252#define CIR_WAKE_WR_FIFO_DATA 0x0b
253#define CIR_WAKE_RD_FIFO_ONLY 0x0c
254#define CIR_WAKE_RD_FIFO_ONLY_IDX 0x0d
255#define CIR_WAKE_FIFO_IGNORE 0x0e
256#define CIR_WAKE_IRFSM 0x0f
257
258/* CIR WAKE UP IRCON settings */
259#define CIR_WAKE_IRCON_DEC_RST 0x80
260#define CIR_WAKE_IRCON_MODE1 0x40
261#define CIR_WAKE_IRCON_MODE0 0x20
262#define CIR_WAKE_IRCON_RXEN 0x10
263#define CIR_WAKE_IRCON_R 0x08
264#define CIR_WAKE_IRCON_RXINV 0x04
265
266/* FIXME/jarod: make this a runtime option */
267/* select a same sample period like cir register */
268#define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL CIR_IRCON_SAMPLE_PERIOD_SEL_50
269
270/* CIR WAKE IRSTS Bits */
271#define CIR_WAKE_IRSTS_RDR 0x80
272#define CIR_WAKE_IRSTS_RTR 0x40
273#define CIR_WAKE_IRSTS_PE 0x20
274#define CIR_WAKE_IRSTS_RFO 0x10
275#define CIR_WAKE_IRSTS_GH 0x08
276#define CIR_WAKE_IRSTS_IR_PENDING 0x01
277
278/* CIR WAKE UP IREN Bits */
279#define CIR_WAKE_IREN_RDR 0x80
280#define CIR_WAKE_IREN_RTR 0x40
281#define CIR_WAKE_IREN_PE 0x20
282#define CIR_WAKE_IREN_RFO 0x10
283#define CIR_WAKE_IREN_TE 0x08
284#define CIR_WAKE_IREN_TTR 0x04
285#define CIR_WAKE_IREN_TFU 0x02
286#define CIR_WAKE_IREN_GH 0x01
287
288/* CIR WAKE FIFOCON settings */
289#define CIR_WAKE_FIFOCON_RXFIFOCLR 0x08
290
291#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 0x00
292#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 0x01
293#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 0x02
294#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 0x03
295
296/* FIXME: make this a runtime option */
297/* select WAKE UP RX trigger level as 67 */
298#define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67
299
300/* CIR WAKE SRXFSTS settings */
301#define CIR_WAKE_IRFIFOSTS_RX_GS 0x80
302#define CIR_WAKE_IRFIFOSTS_RX_FTA 0x40
303#define CIR_WAKE_IRFIFOSTS_RX_EMPTY 0x20
304#define CIR_WAKE_IRFIFOSTS_RX_FULL 0x10
305
306/*
307 * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes
308 * the system comparing only 65 bytes (fails with this set to 67)
309 */
310#define CIR_WAKE_FIFO_CMP_BYTES 65
311/* CIR Wake byte comparison tolerance */
312#define CIR_WAKE_CMP_TOLERANCE 5
313
314/*
315 * Extended Function Enable Registers:
316 * Extended Function Index Register
317 * Extended Function Data Register
318 */
319#define CR_EFIR 0x2e
320#define CR_EFDR 0x2f
321
322/* Possible alternate EFER values, depends on how the chip is wired */
323#define CR_EFIR2 0x4e
324#define CR_EFDR2 0x4f
325
326/* Extended Function Mode enable/disable magic values */
327#define EFER_EFM_ENABLE 0x87
328#define EFER_EFM_DISABLE 0xaa
329
330/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
331#define CHIP_ID_HIGH_667 0xa5
332#define CHIP_ID_HIGH_677B 0xb4
333#define CHIP_ID_HIGH_677C 0xc3
334#define CHIP_ID_LOW_667 0x13
335#define CHIP_ID_LOW_677B2 0x72
336#define CHIP_ID_LOW_677B3 0x73
337#define CHIP_ID_LOW_677C 0x33
338
339/* Config regs we need to care about */
340#define CR_SOFTWARE_RESET 0x02
341#define CR_LOGICAL_DEV_SEL 0x07
342#define CR_CHIP_ID_HI 0x20
343#define CR_CHIP_ID_LO 0x21
344#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
345#define CR_OUTPUT_PIN_SEL 0x27
346#define CR_MULTIFUNC_PIN_SEL 0x2c
347#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
348/* next three regs valid for both the CIR and CIR_WAKE logical devices */
349#define CR_CIR_BASE_ADDR_HI 0x60
350#define CR_CIR_BASE_ADDR_LO 0x61
351#define CR_CIR_IRQ_RSRC 0x70
352/* next three regs valid only for ACPI logical dev */
353#define CR_ACPI_CIR_WAKE 0xe0
354#define CR_ACPI_IRQ_EVENTS 0xf6
355#define CR_ACPI_IRQ_EVENTS2 0xf7
356
357/* Logical devices that we need to care about */
358#define LOGICAL_DEV_LPT 0x01
359#define LOGICAL_DEV_CIR 0x06
360#define LOGICAL_DEV_ACPI 0x0a
361#define LOGICAL_DEV_CIR_WAKE 0x0e
362
363#define LOGICAL_DEV_DISABLE 0x00
364#define LOGICAL_DEV_ENABLE 0x01
365
366#define CIR_WAKE_ENABLE_BIT 0x08
367#define CIR_INTR_MOUSE_IRQ_BIT 0x80
368#define PME_INTR_CIR_PASS_BIT 0x08
369
370/* w83677hg CIR pin config */
371#define OUTPUT_PIN_SEL_MASK 0xbc
372#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
373#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
374
375/* w83667hg CIR pin config */
376#define MULTIFUNC_PIN_SEL_MASK 0x1f
377#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
378#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
379
380/* MCE CIR signal length, related on sample period */
381
382/* MCE CIR controller signal length: about 43ms
383 * 43ms / 50us (sample period) * 0.85 (inaccuracy)
384 */
385#define CONTROLLER_BUF_LEN_MIN 830
386
387/* MCE CIR keyboard signal length: about 26ms
388 * 26ms / 50us (sample period) * 0.85 (inaccuracy)
389 */
390#define KEYBOARD_BUF_LEN_MAX 650
391#define KEYBOARD_BUF_LEN_MIN 610
392
393/* MCE CIR mouse signal length: about 24ms
394 * 24ms / 50us (sample period) * 0.85 (inaccuracy)
395 */
396#define MOUSE_BUF_LEN_MIN 565
397
398#define CIR_SAMPLE_PERIOD 50
399#define CIR_SAMPLE_LOW_INACCURACY 0.85
400
401/* MAX silence time that driver will sent to lirc */
402#define MAX_SILENCE_TIME 60000
403
404#if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100
405#define SAMPLE_PERIOD 100
406
407#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50
408#define SAMPLE_PERIOD 50
409
410#elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25
411#define SAMPLE_PERIOD 25
412
413#else
414#define SAMPLE_PERIOD 1
415#endif
416
417/* as VISTA MCE definition, valid carrier value */
418#define MAX_CARRIER 60000
419#define MIN_CARRIER 30000