tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / sound / soc / codecs / wm5100.h
at v3.4-rc4 5156 lines 280 kB view raw
1/* 2 * wm5100.h -- WM5100 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14#ifndef WM5100_ASOC_H 15#define WM5100_ASOC_H 16 17#include <sound/soc.h> 18#include <linux/regmap.h> 19 20int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack); 21 22#define WM5100_CLK_AIF1 1 23#define WM5100_CLK_AIF2 2 24#define WM5100_CLK_AIF3 3 25#define WM5100_CLK_SYSCLK 4 26#define WM5100_CLK_ASYNCCLK 5 27#define WM5100_CLK_32KHZ 6 28#define WM5100_CLK_OPCLK 7 29 30#define WM5100_CLKSRC_MCLK1 0 31#define WM5100_CLKSRC_MCLK2 1 32#define WM5100_CLKSRC_SYSCLK 2 33#define WM5100_CLKSRC_FLL1 4 34#define WM5100_CLKSRC_FLL2 5 35#define WM5100_CLKSRC_AIF1BCLK 8 36#define WM5100_CLKSRC_AIF2BCLK 9 37#define WM5100_CLKSRC_AIF3BCLK 10 38#define WM5100_CLKSRC_ASYNCCLK 0x100 39 40#define WM5100_FLL1 1 41#define WM5100_FLL2 2 42 43#define WM5100_FLL_SRC_MCLK1 0x0 44#define WM5100_FLL_SRC_MCLK2 0x1 45#define WM5100_FLL_SRC_FLL1 0x4 46#define WM5100_FLL_SRC_FLL2 0x5 47#define WM5100_FLL_SRC_AIF1BCLK 0x8 48#define WM5100_FLL_SRC_AIF2BCLK 0x9 49#define WM5100_FLL_SRC_AIF3BCLK 0xa 50 51/* 52 * Register values. 53 */ 54#define WM5100_SOFTWARE_RESET 0x00 55#define WM5100_DEVICE_REVISION 0x01 56#define WM5100_CTRL_IF_1 0x10 57#define WM5100_TONE_GENERATOR_1 0x20 58#define WM5100_PWM_DRIVE_1 0x30 59#define WM5100_PWM_DRIVE_2 0x31 60#define WM5100_PWM_DRIVE_3 0x32 61#define WM5100_CLOCKING_1 0x100 62#define WM5100_CLOCKING_3 0x101 63#define WM5100_CLOCKING_4 0x102 64#define WM5100_CLOCKING_5 0x103 65#define WM5100_CLOCKING_6 0x104 66#define WM5100_CLOCKING_7 0x107 67#define WM5100_CLOCKING_8 0x108 68#define WM5100_ASRC_ENABLE 0x120 69#define WM5100_ASRC_STATUS 0x121 70#define WM5100_ASRC_RATE1 0x122 71#define WM5100_ISRC_1_CTRL_1 0x141 72#define WM5100_ISRC_1_CTRL_2 0x142 73#define WM5100_ISRC_2_CTRL1 0x143 74#define WM5100_ISRC_2_CTRL_2 0x144 75#define WM5100_FLL1_CONTROL_1 0x182 76#define WM5100_FLL1_CONTROL_2 0x183 77#define WM5100_FLL1_CONTROL_3 0x184 78#define WM5100_FLL1_CONTROL_5 0x186 79#define WM5100_FLL1_CONTROL_6 0x187 80#define WM5100_FLL1_EFS_1 0x188 81#define WM5100_FLL2_CONTROL_1 0x1A2 82#define WM5100_FLL2_CONTROL_2 0x1A3 83#define WM5100_FLL2_CONTROL_3 0x1A4 84#define WM5100_FLL2_CONTROL_5 0x1A6 85#define WM5100_FLL2_CONTROL_6 0x1A7 86#define WM5100_FLL2_EFS_1 0x1A8 87#define WM5100_MIC_CHARGE_PUMP_1 0x200 88#define WM5100_MIC_CHARGE_PUMP_2 0x201 89#define WM5100_HP_CHARGE_PUMP_1 0x202 90#define WM5100_LDO1_CONTROL 0x211 91#define WM5100_MIC_BIAS_CTRL_1 0x215 92#define WM5100_MIC_BIAS_CTRL_2 0x216 93#define WM5100_MIC_BIAS_CTRL_3 0x217 94#define WM5100_ACCESSORY_DETECT_MODE_1 0x280 95#define WM5100_HEADPHONE_DETECT_1 0x288 96#define WM5100_HEADPHONE_DETECT_2 0x289 97#define WM5100_MIC_DETECT_1 0x290 98#define WM5100_MIC_DETECT_2 0x291 99#define WM5100_MIC_DETECT_3 0x292 100#define WM5100_MISC_CONTROL 0x2BB 101#define WM5100_INPUT_ENABLES 0x301 102#define WM5100_INPUT_ENABLES_STATUS 0x302 103#define WM5100_IN1L_CONTROL 0x310 104#define WM5100_IN1R_CONTROL 0x311 105#define WM5100_IN2L_CONTROL 0x312 106#define WM5100_IN2R_CONTROL 0x313 107#define WM5100_IN3L_CONTROL 0x314 108#define WM5100_IN3R_CONTROL 0x315 109#define WM5100_IN4L_CONTROL 0x316 110#define WM5100_IN4R_CONTROL 0x317 111#define WM5100_RXANC_SRC 0x318 112#define WM5100_INPUT_VOLUME_RAMP 0x319 113#define WM5100_ADC_DIGITAL_VOLUME_1L 0x320 114#define WM5100_ADC_DIGITAL_VOLUME_1R 0x321 115#define WM5100_ADC_DIGITAL_VOLUME_2L 0x322 116#define WM5100_ADC_DIGITAL_VOLUME_2R 0x323 117#define WM5100_ADC_DIGITAL_VOLUME_3L 0x324 118#define WM5100_ADC_DIGITAL_VOLUME_3R 0x325 119#define WM5100_ADC_DIGITAL_VOLUME_4L 0x326 120#define WM5100_ADC_DIGITAL_VOLUME_4R 0x327 121#define WM5100_OUTPUT_ENABLES_2 0x401 122#define WM5100_OUTPUT_STATUS_1 0x402 123#define WM5100_OUTPUT_STATUS_2 0x403 124#define WM5100_CHANNEL_ENABLES_1 0x408 125#define WM5100_OUT_VOLUME_1L 0x410 126#define WM5100_OUT_VOLUME_1R 0x411 127#define WM5100_DAC_VOLUME_LIMIT_1L 0x412 128#define WM5100_DAC_VOLUME_LIMIT_1R 0x413 129#define WM5100_OUT_VOLUME_2L 0x414 130#define WM5100_OUT_VOLUME_2R 0x415 131#define WM5100_DAC_VOLUME_LIMIT_2L 0x416 132#define WM5100_DAC_VOLUME_LIMIT_2R 0x417 133#define WM5100_OUT_VOLUME_3L 0x418 134#define WM5100_OUT_VOLUME_3R 0x419 135#define WM5100_DAC_VOLUME_LIMIT_3L 0x41A 136#define WM5100_DAC_VOLUME_LIMIT_3R 0x41B 137#define WM5100_OUT_VOLUME_4L 0x41C 138#define WM5100_OUT_VOLUME_4R 0x41D 139#define WM5100_DAC_VOLUME_LIMIT_5L 0x41E 140#define WM5100_DAC_VOLUME_LIMIT_5R 0x41F 141#define WM5100_DAC_VOLUME_LIMIT_6L 0x420 142#define WM5100_DAC_VOLUME_LIMIT_6R 0x421 143#define WM5100_DAC_AEC_CONTROL_1 0x440 144#define WM5100_OUTPUT_VOLUME_RAMP 0x441 145#define WM5100_DAC_DIGITAL_VOLUME_1L 0x480 146#define WM5100_DAC_DIGITAL_VOLUME_1R 0x481 147#define WM5100_DAC_DIGITAL_VOLUME_2L 0x482 148#define WM5100_DAC_DIGITAL_VOLUME_2R 0x483 149#define WM5100_DAC_DIGITAL_VOLUME_3L 0x484 150#define WM5100_DAC_DIGITAL_VOLUME_3R 0x485 151#define WM5100_DAC_DIGITAL_VOLUME_4L 0x486 152#define WM5100_DAC_DIGITAL_VOLUME_4R 0x487 153#define WM5100_DAC_DIGITAL_VOLUME_5L 0x488 154#define WM5100_DAC_DIGITAL_VOLUME_5R 0x489 155#define WM5100_DAC_DIGITAL_VOLUME_6L 0x48A 156#define WM5100_DAC_DIGITAL_VOLUME_6R 0x48B 157#define WM5100_PDM_SPK1_CTRL_1 0x4C0 158#define WM5100_PDM_SPK1_CTRL_2 0x4C1 159#define WM5100_PDM_SPK2_CTRL_1 0x4C2 160#define WM5100_PDM_SPK2_CTRL_2 0x4C3 161#define WM5100_AUDIO_IF_1_1 0x500 162#define WM5100_AUDIO_IF_1_2 0x501 163#define WM5100_AUDIO_IF_1_3 0x502 164#define WM5100_AUDIO_IF_1_4 0x503 165#define WM5100_AUDIO_IF_1_5 0x504 166#define WM5100_AUDIO_IF_1_6 0x505 167#define WM5100_AUDIO_IF_1_7 0x506 168#define WM5100_AUDIO_IF_1_8 0x507 169#define WM5100_AUDIO_IF_1_9 0x508 170#define WM5100_AUDIO_IF_1_10 0x509 171#define WM5100_AUDIO_IF_1_11 0x50A 172#define WM5100_AUDIO_IF_1_12 0x50B 173#define WM5100_AUDIO_IF_1_13 0x50C 174#define WM5100_AUDIO_IF_1_14 0x50D 175#define WM5100_AUDIO_IF_1_15 0x50E 176#define WM5100_AUDIO_IF_1_16 0x50F 177#define WM5100_AUDIO_IF_1_17 0x510 178#define WM5100_AUDIO_IF_1_18 0x511 179#define WM5100_AUDIO_IF_1_19 0x512 180#define WM5100_AUDIO_IF_1_20 0x513 181#define WM5100_AUDIO_IF_1_21 0x514 182#define WM5100_AUDIO_IF_1_22 0x515 183#define WM5100_AUDIO_IF_1_23 0x516 184#define WM5100_AUDIO_IF_1_24 0x517 185#define WM5100_AUDIO_IF_1_25 0x518 186#define WM5100_AUDIO_IF_1_26 0x519 187#define WM5100_AUDIO_IF_1_27 0x51A 188#define WM5100_AUDIO_IF_2_1 0x540 189#define WM5100_AUDIO_IF_2_2 0x541 190#define WM5100_AUDIO_IF_2_3 0x542 191#define WM5100_AUDIO_IF_2_4 0x543 192#define WM5100_AUDIO_IF_2_5 0x544 193#define WM5100_AUDIO_IF_2_6 0x545 194#define WM5100_AUDIO_IF_2_7 0x546 195#define WM5100_AUDIO_IF_2_8 0x547 196#define WM5100_AUDIO_IF_2_9 0x548 197#define WM5100_AUDIO_IF_2_10 0x549 198#define WM5100_AUDIO_IF_2_11 0x54A 199#define WM5100_AUDIO_IF_2_18 0x551 200#define WM5100_AUDIO_IF_2_19 0x552 201#define WM5100_AUDIO_IF_2_26 0x559 202#define WM5100_AUDIO_IF_2_27 0x55A 203#define WM5100_AUDIO_IF_3_1 0x580 204#define WM5100_AUDIO_IF_3_2 0x581 205#define WM5100_AUDIO_IF_3_3 0x582 206#define WM5100_AUDIO_IF_3_4 0x583 207#define WM5100_AUDIO_IF_3_5 0x584 208#define WM5100_AUDIO_IF_3_6 0x585 209#define WM5100_AUDIO_IF_3_7 0x586 210#define WM5100_AUDIO_IF_3_8 0x587 211#define WM5100_AUDIO_IF_3_9 0x588 212#define WM5100_AUDIO_IF_3_10 0x589 213#define WM5100_AUDIO_IF_3_11 0x58A 214#define WM5100_AUDIO_IF_3_18 0x591 215#define WM5100_AUDIO_IF_3_19 0x592 216#define WM5100_AUDIO_IF_3_26 0x599 217#define WM5100_AUDIO_IF_3_27 0x59A 218#define WM5100_PWM1MIX_INPUT_1_SOURCE 0x640 219#define WM5100_PWM1MIX_INPUT_1_VOLUME 0x641 220#define WM5100_PWM1MIX_INPUT_2_SOURCE 0x642 221#define WM5100_PWM1MIX_INPUT_2_VOLUME 0x643 222#define WM5100_PWM1MIX_INPUT_3_SOURCE 0x644 223#define WM5100_PWM1MIX_INPUT_3_VOLUME 0x645 224#define WM5100_PWM1MIX_INPUT_4_SOURCE 0x646 225#define WM5100_PWM1MIX_INPUT_4_VOLUME 0x647 226#define WM5100_PWM2MIX_INPUT_1_SOURCE 0x648 227#define WM5100_PWM2MIX_INPUT_1_VOLUME 0x649 228#define WM5100_PWM2MIX_INPUT_2_SOURCE 0x64A 229#define WM5100_PWM2MIX_INPUT_2_VOLUME 0x64B 230#define WM5100_PWM2MIX_INPUT_3_SOURCE 0x64C 231#define WM5100_PWM2MIX_INPUT_3_VOLUME 0x64D 232#define WM5100_PWM2MIX_INPUT_4_SOURCE 0x64E 233#define WM5100_PWM2MIX_INPUT_4_VOLUME 0x64F 234#define WM5100_OUT1LMIX_INPUT_1_SOURCE 0x680 235#define WM5100_OUT1LMIX_INPUT_1_VOLUME 0x681 236#define WM5100_OUT1LMIX_INPUT_2_SOURCE 0x682 237#define WM5100_OUT1LMIX_INPUT_2_VOLUME 0x683 238#define WM5100_OUT1LMIX_INPUT_3_SOURCE 0x684 239#define WM5100_OUT1LMIX_INPUT_3_VOLUME 0x685 240#define WM5100_OUT1LMIX_INPUT_4_SOURCE 0x686 241#define WM5100_OUT1LMIX_INPUT_4_VOLUME 0x687 242#define WM5100_OUT1RMIX_INPUT_1_SOURCE 0x688 243#define WM5100_OUT1RMIX_INPUT_1_VOLUME 0x689 244#define WM5100_OUT1RMIX_INPUT_2_SOURCE 0x68A 245#define WM5100_OUT1RMIX_INPUT_2_VOLUME 0x68B 246#define WM5100_OUT1RMIX_INPUT_3_SOURCE 0x68C 247#define WM5100_OUT1RMIX_INPUT_3_VOLUME 0x68D 248#define WM5100_OUT1RMIX_INPUT_4_SOURCE 0x68E 249#define WM5100_OUT1RMIX_INPUT_4_VOLUME 0x68F 250#define WM5100_OUT2LMIX_INPUT_1_SOURCE 0x690 251#define WM5100_OUT2LMIX_INPUT_1_VOLUME 0x691 252#define WM5100_OUT2LMIX_INPUT_2_SOURCE 0x692 253#define WM5100_OUT2LMIX_INPUT_2_VOLUME 0x693 254#define WM5100_OUT2LMIX_INPUT_3_SOURCE 0x694 255#define WM5100_OUT2LMIX_INPUT_3_VOLUME 0x695 256#define WM5100_OUT2LMIX_INPUT_4_SOURCE 0x696 257#define WM5100_OUT2LMIX_INPUT_4_VOLUME 0x697 258#define WM5100_OUT2RMIX_INPUT_1_SOURCE 0x698 259#define WM5100_OUT2RMIX_INPUT_1_VOLUME 0x699 260#define WM5100_OUT2RMIX_INPUT_2_SOURCE 0x69A 261#define WM5100_OUT2RMIX_INPUT_2_VOLUME 0x69B 262#define WM5100_OUT2RMIX_INPUT_3_SOURCE 0x69C 263#define WM5100_OUT2RMIX_INPUT_3_VOLUME 0x69D 264#define WM5100_OUT2RMIX_INPUT_4_SOURCE 0x69E 265#define WM5100_OUT2RMIX_INPUT_4_VOLUME 0x69F 266#define WM5100_OUT3LMIX_INPUT_1_SOURCE 0x6A0 267#define WM5100_OUT3LMIX_INPUT_1_VOLUME 0x6A1 268#define WM5100_OUT3LMIX_INPUT_2_SOURCE 0x6A2 269#define WM5100_OUT3LMIX_INPUT_2_VOLUME 0x6A3 270#define WM5100_OUT3LMIX_INPUT_3_SOURCE 0x6A4 271#define WM5100_OUT3LMIX_INPUT_3_VOLUME 0x6A5 272#define WM5100_OUT3LMIX_INPUT_4_SOURCE 0x6A6 273#define WM5100_OUT3LMIX_INPUT_4_VOLUME 0x6A7 274#define WM5100_OUT3RMIX_INPUT_1_SOURCE 0x6A8 275#define WM5100_OUT3RMIX_INPUT_1_VOLUME 0x6A9 276#define WM5100_OUT3RMIX_INPUT_2_SOURCE 0x6AA 277#define WM5100_OUT3RMIX_INPUT_2_VOLUME 0x6AB 278#define WM5100_OUT3RMIX_INPUT_3_SOURCE 0x6AC 279#define WM5100_OUT3RMIX_INPUT_3_VOLUME 0x6AD 280#define WM5100_OUT3RMIX_INPUT_4_SOURCE 0x6AE 281#define WM5100_OUT3RMIX_INPUT_4_VOLUME 0x6AF 282#define WM5100_OUT4LMIX_INPUT_1_SOURCE 0x6B0 283#define WM5100_OUT4LMIX_INPUT_1_VOLUME 0x6B1 284#define WM5100_OUT4LMIX_INPUT_2_SOURCE 0x6B2 285#define WM5100_OUT4LMIX_INPUT_2_VOLUME 0x6B3 286#define WM5100_OUT4LMIX_INPUT_3_SOURCE 0x6B4 287#define WM5100_OUT4LMIX_INPUT_3_VOLUME 0x6B5 288#define WM5100_OUT4LMIX_INPUT_4_SOURCE 0x6B6 289#define WM5100_OUT4LMIX_INPUT_4_VOLUME 0x6B7 290#define WM5100_OUT4RMIX_INPUT_1_SOURCE 0x6B8 291#define WM5100_OUT4RMIX_INPUT_1_VOLUME 0x6B9 292#define WM5100_OUT4RMIX_INPUT_2_SOURCE 0x6BA 293#define WM5100_OUT4RMIX_INPUT_2_VOLUME 0x6BB 294#define WM5100_OUT4RMIX_INPUT_3_SOURCE 0x6BC 295#define WM5100_OUT4RMIX_INPUT_3_VOLUME 0x6BD 296#define WM5100_OUT4RMIX_INPUT_4_SOURCE 0x6BE 297#define WM5100_OUT4RMIX_INPUT_4_VOLUME 0x6BF 298#define WM5100_OUT5LMIX_INPUT_1_SOURCE 0x6C0 299#define WM5100_OUT5LMIX_INPUT_1_VOLUME 0x6C1 300#define WM5100_OUT5LMIX_INPUT_2_SOURCE 0x6C2 301#define WM5100_OUT5LMIX_INPUT_2_VOLUME 0x6C3 302#define WM5100_OUT5LMIX_INPUT_3_SOURCE 0x6C4 303#define WM5100_OUT5LMIX_INPUT_3_VOLUME 0x6C5 304#define WM5100_OUT5LMIX_INPUT_4_SOURCE 0x6C6 305#define WM5100_OUT5LMIX_INPUT_4_VOLUME 0x6C7 306#define WM5100_OUT5RMIX_INPUT_1_SOURCE 0x6C8 307#define WM5100_OUT5RMIX_INPUT_1_VOLUME 0x6C9 308#define WM5100_OUT5RMIX_INPUT_2_SOURCE 0x6CA 309#define WM5100_OUT5RMIX_INPUT_2_VOLUME 0x6CB 310#define WM5100_OUT5RMIX_INPUT_3_SOURCE 0x6CC 311#define WM5100_OUT5RMIX_INPUT_3_VOLUME 0x6CD 312#define WM5100_OUT5RMIX_INPUT_4_SOURCE 0x6CE 313#define WM5100_OUT5RMIX_INPUT_4_VOLUME 0x6CF 314#define WM5100_OUT6LMIX_INPUT_1_SOURCE 0x6D0 315#define WM5100_OUT6LMIX_INPUT_1_VOLUME 0x6D1 316#define WM5100_OUT6LMIX_INPUT_2_SOURCE 0x6D2 317#define WM5100_OUT6LMIX_INPUT_2_VOLUME 0x6D3 318#define WM5100_OUT6LMIX_INPUT_3_SOURCE 0x6D4 319#define WM5100_OUT6LMIX_INPUT_3_VOLUME 0x6D5 320#define WM5100_OUT6LMIX_INPUT_4_SOURCE 0x6D6 321#define WM5100_OUT6LMIX_INPUT_4_VOLUME 0x6D7 322#define WM5100_OUT6RMIX_INPUT_1_SOURCE 0x6D8 323#define WM5100_OUT6RMIX_INPUT_1_VOLUME 0x6D9 324#define WM5100_OUT6RMIX_INPUT_2_SOURCE 0x6DA 325#define WM5100_OUT6RMIX_INPUT_2_VOLUME 0x6DB 326#define WM5100_OUT6RMIX_INPUT_3_SOURCE 0x6DC 327#define WM5100_OUT6RMIX_INPUT_3_VOLUME 0x6DD 328#define WM5100_OUT6RMIX_INPUT_4_SOURCE 0x6DE 329#define WM5100_OUT6RMIX_INPUT_4_VOLUME 0x6DF 330#define WM5100_AIF1TX1MIX_INPUT_1_SOURCE 0x700 331#define WM5100_AIF1TX1MIX_INPUT_1_VOLUME 0x701 332#define WM5100_AIF1TX1MIX_INPUT_2_SOURCE 0x702 333#define WM5100_AIF1TX1MIX_INPUT_2_VOLUME 0x703 334#define WM5100_AIF1TX1MIX_INPUT_3_SOURCE 0x704 335#define WM5100_AIF1TX1MIX_INPUT_3_VOLUME 0x705 336#define WM5100_AIF1TX1MIX_INPUT_4_SOURCE 0x706 337#define WM5100_AIF1TX1MIX_INPUT_4_VOLUME 0x707 338#define WM5100_AIF1TX2MIX_INPUT_1_SOURCE 0x708 339#define WM5100_AIF1TX2MIX_INPUT_1_VOLUME 0x709 340#define WM5100_AIF1TX2MIX_INPUT_2_SOURCE 0x70A 341#define WM5100_AIF1TX2MIX_INPUT_2_VOLUME 0x70B 342#define WM5100_AIF1TX2MIX_INPUT_3_SOURCE 0x70C 343#define WM5100_AIF1TX2MIX_INPUT_3_VOLUME 0x70D 344#define WM5100_AIF1TX2MIX_INPUT_4_SOURCE 0x70E 345#define WM5100_AIF1TX2MIX_INPUT_4_VOLUME 0x70F 346#define WM5100_AIF1TX3MIX_INPUT_1_SOURCE 0x710 347#define WM5100_AIF1TX3MIX_INPUT_1_VOLUME 0x711 348#define WM5100_AIF1TX3MIX_INPUT_2_SOURCE 0x712 349#define WM5100_AIF1TX3MIX_INPUT_2_VOLUME 0x713 350#define WM5100_AIF1TX3MIX_INPUT_3_SOURCE 0x714 351#define WM5100_AIF1TX3MIX_INPUT_3_VOLUME 0x715 352#define WM5100_AIF1TX3MIX_INPUT_4_SOURCE 0x716 353#define WM5100_AIF1TX3MIX_INPUT_4_VOLUME 0x717 354#define WM5100_AIF1TX4MIX_INPUT_1_SOURCE 0x718 355#define WM5100_AIF1TX4MIX_INPUT_1_VOLUME 0x719 356#define WM5100_AIF1TX4MIX_INPUT_2_SOURCE 0x71A 357#define WM5100_AIF1TX4MIX_INPUT_2_VOLUME 0x71B 358#define WM5100_AIF1TX4MIX_INPUT_3_SOURCE 0x71C 359#define WM5100_AIF1TX4MIX_INPUT_3_VOLUME 0x71D 360#define WM5100_AIF1TX4MIX_INPUT_4_SOURCE 0x71E 361#define WM5100_AIF1TX4MIX_INPUT_4_VOLUME 0x71F 362#define WM5100_AIF1TX5MIX_INPUT_1_SOURCE 0x720 363#define WM5100_AIF1TX5MIX_INPUT_1_VOLUME 0x721 364#define WM5100_AIF1TX5MIX_INPUT_2_SOURCE 0x722 365#define WM5100_AIF1TX5MIX_INPUT_2_VOLUME 0x723 366#define WM5100_AIF1TX5MIX_INPUT_3_SOURCE 0x724 367#define WM5100_AIF1TX5MIX_INPUT_3_VOLUME 0x725 368#define WM5100_AIF1TX5MIX_INPUT_4_SOURCE 0x726 369#define WM5100_AIF1TX5MIX_INPUT_4_VOLUME 0x727 370#define WM5100_AIF1TX6MIX_INPUT_1_SOURCE 0x728 371#define WM5100_AIF1TX6MIX_INPUT_1_VOLUME 0x729 372#define WM5100_AIF1TX6MIX_INPUT_2_SOURCE 0x72A 373#define WM5100_AIF1TX6MIX_INPUT_2_VOLUME 0x72B 374#define WM5100_AIF1TX6MIX_INPUT_3_SOURCE 0x72C 375#define WM5100_AIF1TX6MIX_INPUT_3_VOLUME 0x72D 376#define WM5100_AIF1TX6MIX_INPUT_4_SOURCE 0x72E 377#define WM5100_AIF1TX6MIX_INPUT_4_VOLUME 0x72F 378#define WM5100_AIF1TX7MIX_INPUT_1_SOURCE 0x730 379#define WM5100_AIF1TX7MIX_INPUT_1_VOLUME 0x731 380#define WM5100_AIF1TX7MIX_INPUT_2_SOURCE 0x732 381#define WM5100_AIF1TX7MIX_INPUT_2_VOLUME 0x733 382#define WM5100_AIF1TX7MIX_INPUT_3_SOURCE 0x734 383#define WM5100_AIF1TX7MIX_INPUT_3_VOLUME 0x735 384#define WM5100_AIF1TX7MIX_INPUT_4_SOURCE 0x736 385#define WM5100_AIF1TX7MIX_INPUT_4_VOLUME 0x737 386#define WM5100_AIF1TX8MIX_INPUT_1_SOURCE 0x738 387#define WM5100_AIF1TX8MIX_INPUT_1_VOLUME 0x739 388#define WM5100_AIF1TX8MIX_INPUT_2_SOURCE 0x73A 389#define WM5100_AIF1TX8MIX_INPUT_2_VOLUME 0x73B 390#define WM5100_AIF1TX8MIX_INPUT_3_SOURCE 0x73C 391#define WM5100_AIF1TX8MIX_INPUT_3_VOLUME 0x73D 392#define WM5100_AIF1TX8MIX_INPUT_4_SOURCE 0x73E 393#define WM5100_AIF1TX8MIX_INPUT_4_VOLUME 0x73F 394#define WM5100_AIF2TX1MIX_INPUT_1_SOURCE 0x740 395#define WM5100_AIF2TX1MIX_INPUT_1_VOLUME 0x741 396#define WM5100_AIF2TX1MIX_INPUT_2_SOURCE 0x742 397#define WM5100_AIF2TX1MIX_INPUT_2_VOLUME 0x743 398#define WM5100_AIF2TX1MIX_INPUT_3_SOURCE 0x744 399#define WM5100_AIF2TX1MIX_INPUT_3_VOLUME 0x745 400#define WM5100_AIF2TX1MIX_INPUT_4_SOURCE 0x746 401#define WM5100_AIF2TX1MIX_INPUT_4_VOLUME 0x747 402#define WM5100_AIF2TX2MIX_INPUT_1_SOURCE 0x748 403#define WM5100_AIF2TX2MIX_INPUT_1_VOLUME 0x749 404#define WM5100_AIF2TX2MIX_INPUT_2_SOURCE 0x74A 405#define WM5100_AIF2TX2MIX_INPUT_2_VOLUME 0x74B 406#define WM5100_AIF2TX2MIX_INPUT_3_SOURCE 0x74C 407#define WM5100_AIF2TX2MIX_INPUT_3_VOLUME 0x74D 408#define WM5100_AIF2TX2MIX_INPUT_4_SOURCE 0x74E 409#define WM5100_AIF2TX2MIX_INPUT_4_VOLUME 0x74F 410#define WM5100_AIF3TX1MIX_INPUT_1_SOURCE 0x780 411#define WM5100_AIF3TX1MIX_INPUT_1_VOLUME 0x781 412#define WM5100_AIF3TX1MIX_INPUT_2_SOURCE 0x782 413#define WM5100_AIF3TX1MIX_INPUT_2_VOLUME 0x783 414#define WM5100_AIF3TX1MIX_INPUT_3_SOURCE 0x784 415#define WM5100_AIF3TX1MIX_INPUT_3_VOLUME 0x785 416#define WM5100_AIF3TX1MIX_INPUT_4_SOURCE 0x786 417#define WM5100_AIF3TX1MIX_INPUT_4_VOLUME 0x787 418#define WM5100_AIF3TX2MIX_INPUT_1_SOURCE 0x788 419#define WM5100_AIF3TX2MIX_INPUT_1_VOLUME 0x789 420#define WM5100_AIF3TX2MIX_INPUT_2_SOURCE 0x78A 421#define WM5100_AIF3TX2MIX_INPUT_2_VOLUME 0x78B 422#define WM5100_AIF3TX2MIX_INPUT_3_SOURCE 0x78C 423#define WM5100_AIF3TX2MIX_INPUT_3_VOLUME 0x78D 424#define WM5100_AIF3TX2MIX_INPUT_4_SOURCE 0x78E 425#define WM5100_AIF3TX2MIX_INPUT_4_VOLUME 0x78F 426#define WM5100_EQ1MIX_INPUT_1_SOURCE 0x880 427#define WM5100_EQ1MIX_INPUT_1_VOLUME 0x881 428#define WM5100_EQ1MIX_INPUT_2_SOURCE 0x882 429#define WM5100_EQ1MIX_INPUT_2_VOLUME 0x883 430#define WM5100_EQ1MIX_INPUT_3_SOURCE 0x884 431#define WM5100_EQ1MIX_INPUT_3_VOLUME 0x885 432#define WM5100_EQ1MIX_INPUT_4_SOURCE 0x886 433#define WM5100_EQ1MIX_INPUT_4_VOLUME 0x887 434#define WM5100_EQ2MIX_INPUT_1_SOURCE 0x888 435#define WM5100_EQ2MIX_INPUT_1_VOLUME 0x889 436#define WM5100_EQ2MIX_INPUT_2_SOURCE 0x88A 437#define WM5100_EQ2MIX_INPUT_2_VOLUME 0x88B 438#define WM5100_EQ2MIX_INPUT_3_SOURCE 0x88C 439#define WM5100_EQ2MIX_INPUT_3_VOLUME 0x88D 440#define WM5100_EQ2MIX_INPUT_4_SOURCE 0x88E 441#define WM5100_EQ2MIX_INPUT_4_VOLUME 0x88F 442#define WM5100_EQ3MIX_INPUT_1_SOURCE 0x890 443#define WM5100_EQ3MIX_INPUT_1_VOLUME 0x891 444#define WM5100_EQ3MIX_INPUT_2_SOURCE 0x892 445#define WM5100_EQ3MIX_INPUT_2_VOLUME 0x893 446#define WM5100_EQ3MIX_INPUT_3_SOURCE 0x894 447#define WM5100_EQ3MIX_INPUT_3_VOLUME 0x895 448#define WM5100_EQ3MIX_INPUT_4_SOURCE 0x896 449#define WM5100_EQ3MIX_INPUT_4_VOLUME 0x897 450#define WM5100_EQ4MIX_INPUT_1_SOURCE 0x898 451#define WM5100_EQ4MIX_INPUT_1_VOLUME 0x899 452#define WM5100_EQ4MIX_INPUT_2_SOURCE 0x89A 453#define WM5100_EQ4MIX_INPUT_2_VOLUME 0x89B 454#define WM5100_EQ4MIX_INPUT_3_SOURCE 0x89C 455#define WM5100_EQ4MIX_INPUT_3_VOLUME 0x89D 456#define WM5100_EQ4MIX_INPUT_4_SOURCE 0x89E 457#define WM5100_EQ4MIX_INPUT_4_VOLUME 0x89F 458#define WM5100_DRC1LMIX_INPUT_1_SOURCE 0x8C0 459#define WM5100_DRC1LMIX_INPUT_1_VOLUME 0x8C1 460#define WM5100_DRC1LMIX_INPUT_2_SOURCE 0x8C2 461#define WM5100_DRC1LMIX_INPUT_2_VOLUME 0x8C3 462#define WM5100_DRC1LMIX_INPUT_3_SOURCE 0x8C4 463#define WM5100_DRC1LMIX_INPUT_3_VOLUME 0x8C5 464#define WM5100_DRC1LMIX_INPUT_4_SOURCE 0x8C6 465#define WM5100_DRC1LMIX_INPUT_4_VOLUME 0x8C7 466#define WM5100_DRC1RMIX_INPUT_1_SOURCE 0x8C8 467#define WM5100_DRC1RMIX_INPUT_1_VOLUME 0x8C9 468#define WM5100_DRC1RMIX_INPUT_2_SOURCE 0x8CA 469#define WM5100_DRC1RMIX_INPUT_2_VOLUME 0x8CB 470#define WM5100_DRC1RMIX_INPUT_3_SOURCE 0x8CC 471#define WM5100_DRC1RMIX_INPUT_3_VOLUME 0x8CD 472#define WM5100_DRC1RMIX_INPUT_4_SOURCE 0x8CE 473#define WM5100_DRC1RMIX_INPUT_4_VOLUME 0x8CF 474#define WM5100_HPLP1MIX_INPUT_1_SOURCE 0x900 475#define WM5100_HPLP1MIX_INPUT_1_VOLUME 0x901 476#define WM5100_HPLP1MIX_INPUT_2_SOURCE 0x902 477#define WM5100_HPLP1MIX_INPUT_2_VOLUME 0x903 478#define WM5100_HPLP1MIX_INPUT_3_SOURCE 0x904 479#define WM5100_HPLP1MIX_INPUT_3_VOLUME 0x905 480#define WM5100_HPLP1MIX_INPUT_4_SOURCE 0x906 481#define WM5100_HPLP1MIX_INPUT_4_VOLUME 0x907 482#define WM5100_HPLP2MIX_INPUT_1_SOURCE 0x908 483#define WM5100_HPLP2MIX_INPUT_1_VOLUME 0x909 484#define WM5100_HPLP2MIX_INPUT_2_SOURCE 0x90A 485#define WM5100_HPLP2MIX_INPUT_2_VOLUME 0x90B 486#define WM5100_HPLP2MIX_INPUT_3_SOURCE 0x90C 487#define WM5100_HPLP2MIX_INPUT_3_VOLUME 0x90D 488#define WM5100_HPLP2MIX_INPUT_4_SOURCE 0x90E 489#define WM5100_HPLP2MIX_INPUT_4_VOLUME 0x90F 490#define WM5100_HPLP3MIX_INPUT_1_SOURCE 0x910 491#define WM5100_HPLP3MIX_INPUT_1_VOLUME 0x911 492#define WM5100_HPLP3MIX_INPUT_2_SOURCE 0x912 493#define WM5100_HPLP3MIX_INPUT_2_VOLUME 0x913 494#define WM5100_HPLP3MIX_INPUT_3_SOURCE 0x914 495#define WM5100_HPLP3MIX_INPUT_3_VOLUME 0x915 496#define WM5100_HPLP3MIX_INPUT_4_SOURCE 0x916 497#define WM5100_HPLP3MIX_INPUT_4_VOLUME 0x917 498#define WM5100_HPLP4MIX_INPUT_1_SOURCE 0x918 499#define WM5100_HPLP4MIX_INPUT_1_VOLUME 0x919 500#define WM5100_HPLP4MIX_INPUT_2_SOURCE 0x91A 501#define WM5100_HPLP4MIX_INPUT_2_VOLUME 0x91B 502#define WM5100_HPLP4MIX_INPUT_3_SOURCE 0x91C 503#define WM5100_HPLP4MIX_INPUT_3_VOLUME 0x91D 504#define WM5100_HPLP4MIX_INPUT_4_SOURCE 0x91E 505#define WM5100_HPLP4MIX_INPUT_4_VOLUME 0x91F 506#define WM5100_DSP1LMIX_INPUT_1_SOURCE 0x940 507#define WM5100_DSP1LMIX_INPUT_1_VOLUME 0x941 508#define WM5100_DSP1LMIX_INPUT_2_SOURCE 0x942 509#define WM5100_DSP1LMIX_INPUT_2_VOLUME 0x943 510#define WM5100_DSP1LMIX_INPUT_3_SOURCE 0x944 511#define WM5100_DSP1LMIX_INPUT_3_VOLUME 0x945 512#define WM5100_DSP1LMIX_INPUT_4_SOURCE 0x946 513#define WM5100_DSP1LMIX_INPUT_4_VOLUME 0x947 514#define WM5100_DSP1RMIX_INPUT_1_SOURCE 0x948 515#define WM5100_DSP1RMIX_INPUT_1_VOLUME 0x949 516#define WM5100_DSP1RMIX_INPUT_2_SOURCE 0x94A 517#define WM5100_DSP1RMIX_INPUT_2_VOLUME 0x94B 518#define WM5100_DSP1RMIX_INPUT_3_SOURCE 0x94C 519#define WM5100_DSP1RMIX_INPUT_3_VOLUME 0x94D 520#define WM5100_DSP1RMIX_INPUT_4_SOURCE 0x94E 521#define WM5100_DSP1RMIX_INPUT_4_VOLUME 0x94F 522#define WM5100_DSP1AUX1MIX_INPUT_1_SOURCE 0x950 523#define WM5100_DSP1AUX2MIX_INPUT_1_SOURCE 0x958 524#define WM5100_DSP1AUX3MIX_INPUT_1_SOURCE 0x960 525#define WM5100_DSP1AUX4MIX_INPUT_1_SOURCE 0x968 526#define WM5100_DSP1AUX5MIX_INPUT_1_SOURCE 0x970 527#define WM5100_DSP1AUX6MIX_INPUT_1_SOURCE 0x978 528#define WM5100_DSP2LMIX_INPUT_1_SOURCE 0x980 529#define WM5100_DSP2LMIX_INPUT_1_VOLUME 0x981 530#define WM5100_DSP2LMIX_INPUT_2_SOURCE 0x982 531#define WM5100_DSP2LMIX_INPUT_2_VOLUME 0x983 532#define WM5100_DSP2LMIX_INPUT_3_SOURCE 0x984 533#define WM5100_DSP2LMIX_INPUT_3_VOLUME 0x985 534#define WM5100_DSP2LMIX_INPUT_4_SOURCE 0x986 535#define WM5100_DSP2LMIX_INPUT_4_VOLUME 0x987 536#define WM5100_DSP2RMIX_INPUT_1_SOURCE 0x988 537#define WM5100_DSP2RMIX_INPUT_1_VOLUME 0x989 538#define WM5100_DSP2RMIX_INPUT_2_SOURCE 0x98A 539#define WM5100_DSP2RMIX_INPUT_2_VOLUME 0x98B 540#define WM5100_DSP2RMIX_INPUT_3_SOURCE 0x98C 541#define WM5100_DSP2RMIX_INPUT_3_VOLUME 0x98D 542#define WM5100_DSP2RMIX_INPUT_4_SOURCE 0x98E 543#define WM5100_DSP2RMIX_INPUT_4_VOLUME 0x98F 544#define WM5100_DSP2AUX1MIX_INPUT_1_SOURCE 0x990 545#define WM5100_DSP2AUX2MIX_INPUT_1_SOURCE 0x998 546#define WM5100_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0 547#define WM5100_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8 548#define WM5100_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0 549#define WM5100_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8 550#define WM5100_DSP3LMIX_INPUT_1_SOURCE 0x9C0 551#define WM5100_DSP3LMIX_INPUT_1_VOLUME 0x9C1 552#define WM5100_DSP3LMIX_INPUT_2_SOURCE 0x9C2 553#define WM5100_DSP3LMIX_INPUT_2_VOLUME 0x9C3 554#define WM5100_DSP3LMIX_INPUT_3_SOURCE 0x9C4 555#define WM5100_DSP3LMIX_INPUT_3_VOLUME 0x9C5 556#define WM5100_DSP3LMIX_INPUT_4_SOURCE 0x9C6 557#define WM5100_DSP3LMIX_INPUT_4_VOLUME 0x9C7 558#define WM5100_DSP3RMIX_INPUT_1_SOURCE 0x9C8 559#define WM5100_DSP3RMIX_INPUT_1_VOLUME 0x9C9 560#define WM5100_DSP3RMIX_INPUT_2_SOURCE 0x9CA 561#define WM5100_DSP3RMIX_INPUT_2_VOLUME 0x9CB 562#define WM5100_DSP3RMIX_INPUT_3_SOURCE 0x9CC 563#define WM5100_DSP3RMIX_INPUT_3_VOLUME 0x9CD 564#define WM5100_DSP3RMIX_INPUT_4_SOURCE 0x9CE 565#define WM5100_DSP3RMIX_INPUT_4_VOLUME 0x9CF 566#define WM5100_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0 567#define WM5100_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8 568#define WM5100_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0 569#define WM5100_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8 570#define WM5100_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0 571#define WM5100_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8 572#define WM5100_ASRC1LMIX_INPUT_1_SOURCE 0xA80 573#define WM5100_ASRC1RMIX_INPUT_1_SOURCE 0xA88 574#define WM5100_ASRC2LMIX_INPUT_1_SOURCE 0xA90 575#define WM5100_ASRC2RMIX_INPUT_1_SOURCE 0xA98 576#define WM5100_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00 577#define WM5100_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08 578#define WM5100_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10 579#define WM5100_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18 580#define WM5100_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20 581#define WM5100_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28 582#define WM5100_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30 583#define WM5100_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38 584#define WM5100_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40 585#define WM5100_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48 586#define WM5100_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50 587#define WM5100_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58 588#define WM5100_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60 589#define WM5100_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68 590#define WM5100_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70 591#define WM5100_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78 592#define WM5100_GPIO_CTRL_1 0xC00 593#define WM5100_GPIO_CTRL_2 0xC01 594#define WM5100_GPIO_CTRL_3 0xC02 595#define WM5100_GPIO_CTRL_4 0xC03 596#define WM5100_GPIO_CTRL_5 0xC04 597#define WM5100_GPIO_CTRL_6 0xC05 598#define WM5100_MISC_PAD_CTRL_1 0xC23 599#define WM5100_MISC_PAD_CTRL_2 0xC24 600#define WM5100_MISC_PAD_CTRL_3 0xC25 601#define WM5100_MISC_PAD_CTRL_4 0xC26 602#define WM5100_MISC_PAD_CTRL_5 0xC27 603#define WM5100_MISC_GPIO_1 0xC28 604#define WM5100_INTERRUPT_STATUS_1 0xD00 605#define WM5100_INTERRUPT_STATUS_2 0xD01 606#define WM5100_INTERRUPT_STATUS_3 0xD02 607#define WM5100_INTERRUPT_STATUS_4 0xD03 608#define WM5100_INTERRUPT_RAW_STATUS_2 0xD04 609#define WM5100_INTERRUPT_RAW_STATUS_3 0xD05 610#define WM5100_INTERRUPT_RAW_STATUS_4 0xD06 611#define WM5100_INTERRUPT_STATUS_1_MASK 0xD07 612#define WM5100_INTERRUPT_STATUS_2_MASK 0xD08 613#define WM5100_INTERRUPT_STATUS_3_MASK 0xD09 614#define WM5100_INTERRUPT_STATUS_4_MASK 0xD0A 615#define WM5100_INTERRUPT_CONTROL 0xD1F 616#define WM5100_IRQ_DEBOUNCE_1 0xD20 617#define WM5100_IRQ_DEBOUNCE_2 0xD21 618#define WM5100_FX_CTRL 0xE00 619#define WM5100_EQ1_1 0xE10 620#define WM5100_EQ1_2 0xE11 621#define WM5100_EQ1_3 0xE12 622#define WM5100_EQ1_4 0xE13 623#define WM5100_EQ1_5 0xE14 624#define WM5100_EQ1_6 0xE15 625#define WM5100_EQ1_7 0xE16 626#define WM5100_EQ1_8 0xE17 627#define WM5100_EQ1_9 0xE18 628#define WM5100_EQ1_10 0xE19 629#define WM5100_EQ1_11 0xE1A 630#define WM5100_EQ1_12 0xE1B 631#define WM5100_EQ1_13 0xE1C 632#define WM5100_EQ1_14 0xE1D 633#define WM5100_EQ1_15 0xE1E 634#define WM5100_EQ1_16 0xE1F 635#define WM5100_EQ1_17 0xE20 636#define WM5100_EQ1_18 0xE21 637#define WM5100_EQ1_19 0xE22 638#define WM5100_EQ1_20 0xE23 639#define WM5100_EQ2_1 0xE26 640#define WM5100_EQ2_2 0xE27 641#define WM5100_EQ2_3 0xE28 642#define WM5100_EQ2_4 0xE29 643#define WM5100_EQ2_5 0xE2A 644#define WM5100_EQ2_6 0xE2B 645#define WM5100_EQ2_7 0xE2C 646#define WM5100_EQ2_8 0xE2D 647#define WM5100_EQ2_9 0xE2E 648#define WM5100_EQ2_10 0xE2F 649#define WM5100_EQ2_11 0xE30 650#define WM5100_EQ2_12 0xE31 651#define WM5100_EQ2_13 0xE32 652#define WM5100_EQ2_14 0xE33 653#define WM5100_EQ2_15 0xE34 654#define WM5100_EQ2_16 0xE35 655#define WM5100_EQ2_17 0xE36 656#define WM5100_EQ2_18 0xE37 657#define WM5100_EQ2_19 0xE38 658#define WM5100_EQ2_20 0xE39 659#define WM5100_EQ3_1 0xE3C 660#define WM5100_EQ3_2 0xE3D 661#define WM5100_EQ3_3 0xE3E 662#define WM5100_EQ3_4 0xE3F 663#define WM5100_EQ3_5 0xE40 664#define WM5100_EQ3_6 0xE41 665#define WM5100_EQ3_7 0xE42 666#define WM5100_EQ3_8 0xE43 667#define WM5100_EQ3_9 0xE44 668#define WM5100_EQ3_10 0xE45 669#define WM5100_EQ3_11 0xE46 670#define WM5100_EQ3_12 0xE47 671#define WM5100_EQ3_13 0xE48 672#define WM5100_EQ3_14 0xE49 673#define WM5100_EQ3_15 0xE4A 674#define WM5100_EQ3_16 0xE4B 675#define WM5100_EQ3_17 0xE4C 676#define WM5100_EQ3_18 0xE4D 677#define WM5100_EQ3_19 0xE4E 678#define WM5100_EQ3_20 0xE4F 679#define WM5100_EQ4_1 0xE52 680#define WM5100_EQ4_2 0xE53 681#define WM5100_EQ4_3 0xE54 682#define WM5100_EQ4_4 0xE55 683#define WM5100_EQ4_5 0xE56 684#define WM5100_EQ4_6 0xE57 685#define WM5100_EQ4_7 0xE58 686#define WM5100_EQ4_8 0xE59 687#define WM5100_EQ4_9 0xE5A 688#define WM5100_EQ4_10 0xE5B 689#define WM5100_EQ4_11 0xE5C 690#define WM5100_EQ4_12 0xE5D 691#define WM5100_EQ4_13 0xE5E 692#define WM5100_EQ4_14 0xE5F 693#define WM5100_EQ4_15 0xE60 694#define WM5100_EQ4_16 0xE61 695#define WM5100_EQ4_17 0xE62 696#define WM5100_EQ4_18 0xE63 697#define WM5100_EQ4_19 0xE64 698#define WM5100_EQ4_20 0xE65 699#define WM5100_DRC1_CTRL1 0xE80 700#define WM5100_DRC1_CTRL2 0xE81 701#define WM5100_DRC1_CTRL3 0xE82 702#define WM5100_DRC1_CTRL4 0xE83 703#define WM5100_DRC1_CTRL5 0xE84 704#define WM5100_HPLPF1_1 0xEC0 705#define WM5100_HPLPF1_2 0xEC1 706#define WM5100_HPLPF2_1 0xEC4 707#define WM5100_HPLPF2_2 0xEC5 708#define WM5100_HPLPF3_1 0xEC8 709#define WM5100_HPLPF3_2 0xEC9 710#define WM5100_HPLPF4_1 0xECC 711#define WM5100_HPLPF4_2 0xECD 712#define WM5100_DSP1_DM_0 0x4000 713#define WM5100_DSP1_DM_1 0x4001 714#define WM5100_DSP1_DM_2 0x4002 715#define WM5100_DSP1_DM_3 0x4003 716#define WM5100_DSP1_DM_508 0x41FC 717#define WM5100_DSP1_DM_509 0x41FD 718#define WM5100_DSP1_DM_510 0x41FE 719#define WM5100_DSP1_DM_511 0x41FF 720#define WM5100_DSP1_PM_0 0x4800 721#define WM5100_DSP1_PM_1 0x4801 722#define WM5100_DSP1_PM_2 0x4802 723#define WM5100_DSP1_PM_3 0x4803 724#define WM5100_DSP1_PM_4 0x4804 725#define WM5100_DSP1_PM_5 0x4805 726#define WM5100_DSP1_PM_1530 0x4DFA 727#define WM5100_DSP1_PM_1531 0x4DFB 728#define WM5100_DSP1_PM_1532 0x4DFC 729#define WM5100_DSP1_PM_1533 0x4DFD 730#define WM5100_DSP1_PM_1534 0x4DFE 731#define WM5100_DSP1_PM_1535 0x4DFF 732#define WM5100_DSP1_ZM_0 0x5000 733#define WM5100_DSP1_ZM_1 0x5001 734#define WM5100_DSP1_ZM_2 0x5002 735#define WM5100_DSP1_ZM_3 0x5003 736#define WM5100_DSP1_ZM_2044 0x57FC 737#define WM5100_DSP1_ZM_2045 0x57FD 738#define WM5100_DSP1_ZM_2046 0x57FE 739#define WM5100_DSP1_ZM_2047 0x57FF 740#define WM5100_DSP2_DM_0 0x6000 741#define WM5100_DSP2_DM_1 0x6001 742#define WM5100_DSP2_DM_2 0x6002 743#define WM5100_DSP2_DM_3 0x6003 744#define WM5100_DSP2_DM_508 0x61FC 745#define WM5100_DSP2_DM_509 0x61FD 746#define WM5100_DSP2_DM_510 0x61FE 747#define WM5100_DSP2_DM_511 0x61FF 748#define WM5100_DSP2_PM_0 0x6800 749#define WM5100_DSP2_PM_1 0x6801 750#define WM5100_DSP2_PM_2 0x6802 751#define WM5100_DSP2_PM_3 0x6803 752#define WM5100_DSP2_PM_4 0x6804 753#define WM5100_DSP2_PM_5 0x6805 754#define WM5100_DSP2_PM_1530 0x6DFA 755#define WM5100_DSP2_PM_1531 0x6DFB 756#define WM5100_DSP2_PM_1532 0x6DFC 757#define WM5100_DSP2_PM_1533 0x6DFD 758#define WM5100_DSP2_PM_1534 0x6DFE 759#define WM5100_DSP2_PM_1535 0x6DFF 760#define WM5100_DSP2_ZM_0 0x7000 761#define WM5100_DSP2_ZM_1 0x7001 762#define WM5100_DSP2_ZM_2 0x7002 763#define WM5100_DSP2_ZM_3 0x7003 764#define WM5100_DSP2_ZM_2044 0x77FC 765#define WM5100_DSP2_ZM_2045 0x77FD 766#define WM5100_DSP2_ZM_2046 0x77FE 767#define WM5100_DSP2_ZM_2047 0x77FF 768#define WM5100_DSP3_DM_0 0x8000 769#define WM5100_DSP3_DM_1 0x8001 770#define WM5100_DSP3_DM_2 0x8002 771#define WM5100_DSP3_DM_3 0x8003 772#define WM5100_DSP3_DM_508 0x81FC 773#define WM5100_DSP3_DM_509 0x81FD 774#define WM5100_DSP3_DM_510 0x81FE 775#define WM5100_DSP3_DM_511 0x81FF 776#define WM5100_DSP3_PM_0 0x8800 777#define WM5100_DSP3_PM_1 0x8801 778#define WM5100_DSP3_PM_2 0x8802 779#define WM5100_DSP3_PM_3 0x8803 780#define WM5100_DSP3_PM_4 0x8804 781#define WM5100_DSP3_PM_5 0x8805 782#define WM5100_DSP3_PM_1530 0x8DFA 783#define WM5100_DSP3_PM_1531 0x8DFB 784#define WM5100_DSP3_PM_1532 0x8DFC 785#define WM5100_DSP3_PM_1533 0x8DFD 786#define WM5100_DSP3_PM_1534 0x8DFE 787#define WM5100_DSP3_PM_1535 0x8DFF 788#define WM5100_DSP3_ZM_0 0x9000 789#define WM5100_DSP3_ZM_1 0x9001 790#define WM5100_DSP3_ZM_2 0x9002 791#define WM5100_DSP3_ZM_3 0x9003 792#define WM5100_DSP3_ZM_2044 0x97FC 793#define WM5100_DSP3_ZM_2045 0x97FD 794#define WM5100_DSP3_ZM_2046 0x97FE 795#define WM5100_DSP3_ZM_2047 0x97FF 796 797#define WM5100_REGISTER_COUNT 1435 798#define WM5100_MAX_REGISTER 0x97FF 799 800/* 801 * Field Definitions. 802 */ 803 804/* 805 * R0 (0x00) - software reset 806 */ 807#define WM5100_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ 808#define WM5100_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ 809#define WM5100_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ 810 811/* 812 * R1 (0x01) - Device Revision 813 */ 814#define WM5100_DEVICE_REVISION_MASK 0x000F /* DEVICE_REVISION - [3:0] */ 815#define WM5100_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [3:0] */ 816#define WM5100_DEVICE_REVISION_WIDTH 4 /* DEVICE_REVISION - [3:0] */ 817 818/* 819 * R16 (0x10) - Ctrl IF 1 820 */ 821#define WM5100_AUTO_INC 0x0001 /* AUTO_INC */ 822#define WM5100_AUTO_INC_MASK 0x0001 /* AUTO_INC */ 823#define WM5100_AUTO_INC_SHIFT 0 /* AUTO_INC */ 824#define WM5100_AUTO_INC_WIDTH 1 /* AUTO_INC */ 825 826/* 827 * R32 (0x20) - Tone Generator 1 828 */ 829#define WM5100_TONE_RATE_MASK 0x3000 /* TONE_RATE - [13:12] */ 830#define WM5100_TONE_RATE_SHIFT 12 /* TONE_RATE - [13:12] */ 831#define WM5100_TONE_RATE_WIDTH 2 /* TONE_RATE - [13:12] */ 832#define WM5100_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */ 833#define WM5100_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */ 834#define WM5100_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */ 835#define WM5100_TONE2_ENA 0x0002 /* TONE2_ENA */ 836#define WM5100_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */ 837#define WM5100_TONE2_ENA_SHIFT 1 /* TONE2_ENA */ 838#define WM5100_TONE2_ENA_WIDTH 1 /* TONE2_ENA */ 839#define WM5100_TONE1_ENA 0x0001 /* TONE1_ENA */ 840#define WM5100_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */ 841#define WM5100_TONE1_ENA_SHIFT 0 /* TONE1_ENA */ 842#define WM5100_TONE1_ENA_WIDTH 1 /* TONE1_ENA */ 843 844/* 845 * R48 (0x30) - PWM Drive 1 846 */ 847#define WM5100_PWM_RATE_MASK 0x3000 /* PWM_RATE - [13:12] */ 848#define WM5100_PWM_RATE_SHIFT 12 /* PWM_RATE - [13:12] */ 849#define WM5100_PWM_RATE_WIDTH 2 /* PWM_RATE - [13:12] */ 850#define WM5100_PWM_CLK_SEL_MASK 0x0300 /* PWM_CLK_SEL - [9:8] */ 851#define WM5100_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [9:8] */ 852#define WM5100_PWM_CLK_SEL_WIDTH 2 /* PWM_CLK_SEL - [9:8] */ 853#define WM5100_PWM2_OVD 0x0020 /* PWM2_OVD */ 854#define WM5100_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */ 855#define WM5100_PWM2_OVD_SHIFT 5 /* PWM2_OVD */ 856#define WM5100_PWM2_OVD_WIDTH 1 /* PWM2_OVD */ 857#define WM5100_PWM1_OVD 0x0010 /* PWM1_OVD */ 858#define WM5100_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */ 859#define WM5100_PWM1_OVD_SHIFT 4 /* PWM1_OVD */ 860#define WM5100_PWM1_OVD_WIDTH 1 /* PWM1_OVD */ 861#define WM5100_PWM2_ENA 0x0002 /* PWM2_ENA */ 862#define WM5100_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */ 863#define WM5100_PWM2_ENA_SHIFT 1 /* PWM2_ENA */ 864#define WM5100_PWM2_ENA_WIDTH 1 /* PWM2_ENA */ 865#define WM5100_PWM1_ENA 0x0001 /* PWM1_ENA */ 866#define WM5100_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */ 867#define WM5100_PWM1_ENA_SHIFT 0 /* PWM1_ENA */ 868#define WM5100_PWM1_ENA_WIDTH 1 /* PWM1_ENA */ 869 870/* 871 * R49 (0x31) - PWM Drive 2 872 */ 873#define WM5100_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */ 874#define WM5100_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */ 875#define WM5100_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */ 876 877/* 878 * R50 (0x32) - PWM Drive 3 879 */ 880#define WM5100_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */ 881#define WM5100_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */ 882#define WM5100_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */ 883 884/* 885 * R256 (0x100) - Clocking 1 886 */ 887#define WM5100_CLK_32K_SRC_MASK 0x000F /* CLK_32K_SRC - [3:0] */ 888#define WM5100_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [3:0] */ 889#define WM5100_CLK_32K_SRC_WIDTH 4 /* CLK_32K_SRC - [3:0] */ 890 891/* 892 * R257 (0x101) - Clocking 3 893 */ 894#define WM5100_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */ 895#define WM5100_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */ 896#define WM5100_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */ 897#define WM5100_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */ 898#define WM5100_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */ 899#define WM5100_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */ 900#define WM5100_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */ 901#define WM5100_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */ 902#define WM5100_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */ 903#define WM5100_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */ 904 905/* 906 * R258 (0x102) - Clocking 4 907 */ 908#define WM5100_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */ 909#define WM5100_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */ 910#define WM5100_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */ 911 912/* 913 * R259 (0x103) - Clocking 5 914 */ 915#define WM5100_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */ 916#define WM5100_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */ 917#define WM5100_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */ 918 919/* 920 * R260 (0x104) - Clocking 6 921 */ 922#define WM5100_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */ 923#define WM5100_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */ 924#define WM5100_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */ 925 926/* 927 * R263 (0x107) - Clocking 7 928 */ 929#define WM5100_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */ 930#define WM5100_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */ 931#define WM5100_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */ 932#define WM5100_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */ 933#define WM5100_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */ 934#define WM5100_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */ 935#define WM5100_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */ 936#define WM5100_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */ 937#define WM5100_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */ 938#define WM5100_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */ 939 940/* 941 * R264 (0x108) - Clocking 8 942 */ 943#define WM5100_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */ 944#define WM5100_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */ 945#define WM5100_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */ 946 947/* 948 * R288 (0x120) - ASRC_ENABLE 949 */ 950#define WM5100_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */ 951#define WM5100_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */ 952#define WM5100_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */ 953#define WM5100_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */ 954#define WM5100_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */ 955#define WM5100_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */ 956#define WM5100_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */ 957#define WM5100_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */ 958#define WM5100_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */ 959#define WM5100_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */ 960#define WM5100_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */ 961#define WM5100_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */ 962#define WM5100_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */ 963#define WM5100_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */ 964#define WM5100_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */ 965#define WM5100_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */ 966 967/* 968 * R289 (0x121) - ASRC_STATUS 969 */ 970#define WM5100_ASRC2L_ENA_STS 0x0008 /* ASRC2L_ENA_STS */ 971#define WM5100_ASRC2L_ENA_STS_MASK 0x0008 /* ASRC2L_ENA_STS */ 972#define WM5100_ASRC2L_ENA_STS_SHIFT 3 /* ASRC2L_ENA_STS */ 973#define WM5100_ASRC2L_ENA_STS_WIDTH 1 /* ASRC2L_ENA_STS */ 974#define WM5100_ASRC2R_ENA_STS 0x0004 /* ASRC2R_ENA_STS */ 975#define WM5100_ASRC2R_ENA_STS_MASK 0x0004 /* ASRC2R_ENA_STS */ 976#define WM5100_ASRC2R_ENA_STS_SHIFT 2 /* ASRC2R_ENA_STS */ 977#define WM5100_ASRC2R_ENA_STS_WIDTH 1 /* ASRC2R_ENA_STS */ 978#define WM5100_ASRC1L_ENA_STS 0x0002 /* ASRC1L_ENA_STS */ 979#define WM5100_ASRC1L_ENA_STS_MASK 0x0002 /* ASRC1L_ENA_STS */ 980#define WM5100_ASRC1L_ENA_STS_SHIFT 1 /* ASRC1L_ENA_STS */ 981#define WM5100_ASRC1L_ENA_STS_WIDTH 1 /* ASRC1L_ENA_STS */ 982#define WM5100_ASRC1R_ENA_STS 0x0001 /* ASRC1R_ENA_STS */ 983#define WM5100_ASRC1R_ENA_STS_MASK 0x0001 /* ASRC1R_ENA_STS */ 984#define WM5100_ASRC1R_ENA_STS_SHIFT 0 /* ASRC1R_ENA_STS */ 985#define WM5100_ASRC1R_ENA_STS_WIDTH 1 /* ASRC1R_ENA_STS */ 986 987/* 988 * R290 (0x122) - ASRC_RATE1 989 */ 990#define WM5100_ASRC_RATE1_MASK 0x0006 /* ASRC_RATE1 - [2:1] */ 991#define WM5100_ASRC_RATE1_SHIFT 1 /* ASRC_RATE1 - [2:1] */ 992#define WM5100_ASRC_RATE1_WIDTH 2 /* ASRC_RATE1 - [2:1] */ 993 994/* 995 * R321 (0x141) - ISRC 1 CTRL 1 996 */ 997#define WM5100_ISRC1_DFS_ENA 0x2000 /* ISRC1_DFS_ENA */ 998#define WM5100_ISRC1_DFS_ENA_MASK 0x2000 /* ISRC1_DFS_ENA */ 999#define WM5100_ISRC1_DFS_ENA_SHIFT 13 /* ISRC1_DFS_ENA */ 1000#define WM5100_ISRC1_DFS_ENA_WIDTH 1 /* ISRC1_DFS_ENA */ 1001#define WM5100_ISRC1_CLK_SEL_MASK 0x0300 /* ISRC1_CLK_SEL - [9:8] */ 1002#define WM5100_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [9:8] */ 1003#define WM5100_ISRC1_CLK_SEL_WIDTH 2 /* ISRC1_CLK_SEL - [9:8] */ 1004#define WM5100_ISRC1_FSH_MASK 0x000C /* ISRC1_FSH - [3:2] */ 1005#define WM5100_ISRC1_FSH_SHIFT 2 /* ISRC1_FSH - [3:2] */ 1006#define WM5100_ISRC1_FSH_WIDTH 2 /* ISRC1_FSH - [3:2] */ 1007#define WM5100_ISRC1_FSL_MASK 0x0003 /* ISRC1_FSL - [1:0] */ 1008#define WM5100_ISRC1_FSL_SHIFT 0 /* ISRC1_FSL - [1:0] */ 1009#define WM5100_ISRC1_FSL_WIDTH 2 /* ISRC1_FSL - [1:0] */ 1010 1011/* 1012 * R322 (0x142) - ISRC 1 CTRL 2 1013 */ 1014#define WM5100_ISRC1_INT1_ENA 0x8000 /* ISRC1_INT1_ENA */ 1015#define WM5100_ISRC1_INT1_ENA_MASK 0x8000 /* ISRC1_INT1_ENA */ 1016#define WM5100_ISRC1_INT1_ENA_SHIFT 15 /* ISRC1_INT1_ENA */ 1017#define WM5100_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */ 1018#define WM5100_ISRC1_INT2_ENA 0x4000 /* ISRC1_INT2_ENA */ 1019#define WM5100_ISRC1_INT2_ENA_MASK 0x4000 /* ISRC1_INT2_ENA */ 1020#define WM5100_ISRC1_INT2_ENA_SHIFT 14 /* ISRC1_INT2_ENA */ 1021#define WM5100_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */ 1022#define WM5100_ISRC1_INT3_ENA 0x2000 /* ISRC1_INT3_ENA */ 1023#define WM5100_ISRC1_INT3_ENA_MASK 0x2000 /* ISRC1_INT3_ENA */ 1024#define WM5100_ISRC1_INT3_ENA_SHIFT 13 /* ISRC1_INT3_ENA */ 1025#define WM5100_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */ 1026#define WM5100_ISRC1_INT4_ENA 0x1000 /* ISRC1_INT4_ENA */ 1027#define WM5100_ISRC1_INT4_ENA_MASK 0x1000 /* ISRC1_INT4_ENA */ 1028#define WM5100_ISRC1_INT4_ENA_SHIFT 12 /* ISRC1_INT4_ENA */ 1029#define WM5100_ISRC1_INT4_ENA_WIDTH 1 /* ISRC1_INT4_ENA */ 1030#define WM5100_ISRC1_DEC1_ENA 0x0200 /* ISRC1_DEC1_ENA */ 1031#define WM5100_ISRC1_DEC1_ENA_MASK 0x0200 /* ISRC1_DEC1_ENA */ 1032#define WM5100_ISRC1_DEC1_ENA_SHIFT 9 /* ISRC1_DEC1_ENA */ 1033#define WM5100_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */ 1034#define WM5100_ISRC1_DEC2_ENA 0x0100 /* ISRC1_DEC2_ENA */ 1035#define WM5100_ISRC1_DEC2_ENA_MASK 0x0100 /* ISRC1_DEC2_ENA */ 1036#define WM5100_ISRC1_DEC2_ENA_SHIFT 8 /* ISRC1_DEC2_ENA */ 1037#define WM5100_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */ 1038#define WM5100_ISRC1_DEC3_ENA 0x0080 /* ISRC1_DEC3_ENA */ 1039#define WM5100_ISRC1_DEC3_ENA_MASK 0x0080 /* ISRC1_DEC3_ENA */ 1040#define WM5100_ISRC1_DEC3_ENA_SHIFT 7 /* ISRC1_DEC3_ENA */ 1041#define WM5100_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */ 1042#define WM5100_ISRC1_DEC4_ENA 0x0040 /* ISRC1_DEC4_ENA */ 1043#define WM5100_ISRC1_DEC4_ENA_MASK 0x0040 /* ISRC1_DEC4_ENA */ 1044#define WM5100_ISRC1_DEC4_ENA_SHIFT 6 /* ISRC1_DEC4_ENA */ 1045#define WM5100_ISRC1_DEC4_ENA_WIDTH 1 /* ISRC1_DEC4_ENA */ 1046#define WM5100_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */ 1047#define WM5100_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */ 1048#define WM5100_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */ 1049#define WM5100_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */ 1050 1051/* 1052 * R323 (0x143) - ISRC 2 CTRL1 1053 */ 1054#define WM5100_ISRC2_DFS_ENA 0x2000 /* ISRC2_DFS_ENA */ 1055#define WM5100_ISRC2_DFS_ENA_MASK 0x2000 /* ISRC2_DFS_ENA */ 1056#define WM5100_ISRC2_DFS_ENA_SHIFT 13 /* ISRC2_DFS_ENA */ 1057#define WM5100_ISRC2_DFS_ENA_WIDTH 1 /* ISRC2_DFS_ENA */ 1058#define WM5100_ISRC2_CLK_SEL_MASK 0x0300 /* ISRC2_CLK_SEL - [9:8] */ 1059#define WM5100_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [9:8] */ 1060#define WM5100_ISRC2_CLK_SEL_WIDTH 2 /* ISRC2_CLK_SEL - [9:8] */ 1061#define WM5100_ISRC2_FSH_MASK 0x000C /* ISRC2_FSH - [3:2] */ 1062#define WM5100_ISRC2_FSH_SHIFT 2 /* ISRC2_FSH - [3:2] */ 1063#define WM5100_ISRC2_FSH_WIDTH 2 /* ISRC2_FSH - [3:2] */ 1064#define WM5100_ISRC2_FSL_MASK 0x0003 /* ISRC2_FSL - [1:0] */ 1065#define WM5100_ISRC2_FSL_SHIFT 0 /* ISRC2_FSL - [1:0] */ 1066#define WM5100_ISRC2_FSL_WIDTH 2 /* ISRC2_FSL - [1:0] */ 1067 1068/* 1069 * R324 (0x144) - ISRC 2 CTRL 2 1070 */ 1071#define WM5100_ISRC2_INT1_ENA 0x8000 /* ISRC2_INT1_ENA */ 1072#define WM5100_ISRC2_INT1_ENA_MASK 0x8000 /* ISRC2_INT1_ENA */ 1073#define WM5100_ISRC2_INT1_ENA_SHIFT 15 /* ISRC2_INT1_ENA */ 1074#define WM5100_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */ 1075#define WM5100_ISRC2_INT2_ENA 0x4000 /* ISRC2_INT2_ENA */ 1076#define WM5100_ISRC2_INT2_ENA_MASK 0x4000 /* ISRC2_INT2_ENA */ 1077#define WM5100_ISRC2_INT2_ENA_SHIFT 14 /* ISRC2_INT2_ENA */ 1078#define WM5100_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */ 1079#define WM5100_ISRC2_INT3_ENA 0x2000 /* ISRC2_INT3_ENA */ 1080#define WM5100_ISRC2_INT3_ENA_MASK 0x2000 /* ISRC2_INT3_ENA */ 1081#define WM5100_ISRC2_INT3_ENA_SHIFT 13 /* ISRC2_INT3_ENA */ 1082#define WM5100_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */ 1083#define WM5100_ISRC2_INT4_ENA 0x1000 /* ISRC2_INT4_ENA */ 1084#define WM5100_ISRC2_INT4_ENA_MASK 0x1000 /* ISRC2_INT4_ENA */ 1085#define WM5100_ISRC2_INT4_ENA_SHIFT 12 /* ISRC2_INT4_ENA */ 1086#define WM5100_ISRC2_INT4_ENA_WIDTH 1 /* ISRC2_INT4_ENA */ 1087#define WM5100_ISRC2_DEC1_ENA 0x0200 /* ISRC2_DEC1_ENA */ 1088#define WM5100_ISRC2_DEC1_ENA_MASK 0x0200 /* ISRC2_DEC1_ENA */ 1089#define WM5100_ISRC2_DEC1_ENA_SHIFT 9 /* ISRC2_DEC1_ENA */ 1090#define WM5100_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */ 1091#define WM5100_ISRC2_DEC2_ENA 0x0100 /* ISRC2_DEC2_ENA */ 1092#define WM5100_ISRC2_DEC2_ENA_MASK 0x0100 /* ISRC2_DEC2_ENA */ 1093#define WM5100_ISRC2_DEC2_ENA_SHIFT 8 /* ISRC2_DEC2_ENA */ 1094#define WM5100_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */ 1095#define WM5100_ISRC2_DEC3_ENA 0x0080 /* ISRC2_DEC3_ENA */ 1096#define WM5100_ISRC2_DEC3_ENA_MASK 0x0080 /* ISRC2_DEC3_ENA */ 1097#define WM5100_ISRC2_DEC3_ENA_SHIFT 7 /* ISRC2_DEC3_ENA */ 1098#define WM5100_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */ 1099#define WM5100_ISRC2_DEC4_ENA 0x0040 /* ISRC2_DEC4_ENA */ 1100#define WM5100_ISRC2_DEC4_ENA_MASK 0x0040 /* ISRC2_DEC4_ENA */ 1101#define WM5100_ISRC2_DEC4_ENA_SHIFT 6 /* ISRC2_DEC4_ENA */ 1102#define WM5100_ISRC2_DEC4_ENA_WIDTH 1 /* ISRC2_DEC4_ENA */ 1103#define WM5100_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */ 1104#define WM5100_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */ 1105#define WM5100_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */ 1106#define WM5100_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */ 1107 1108/* 1109 * R386 (0x182) - FLL1 Control 1 1110 */ 1111#define WM5100_FLL1_ENA 0x0001 /* FLL1_ENA */ 1112#define WM5100_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */ 1113#define WM5100_FLL1_ENA_SHIFT 0 /* FLL1_ENA */ 1114#define WM5100_FLL1_ENA_WIDTH 1 /* FLL1_ENA */ 1115 1116/* 1117 * R387 (0x183) - FLL1 Control 2 1118 */ 1119#define WM5100_FLL1_OUTDIV_MASK 0x3F00 /* FLL1_OUTDIV - [13:8] */ 1120#define WM5100_FLL1_OUTDIV_SHIFT 8 /* FLL1_OUTDIV - [13:8] */ 1121#define WM5100_FLL1_OUTDIV_WIDTH 6 /* FLL1_OUTDIV - [13:8] */ 1122#define WM5100_FLL1_FRATIO_MASK 0x0007 /* FLL1_FRATIO - [2:0] */ 1123#define WM5100_FLL1_FRATIO_SHIFT 0 /* FLL1_FRATIO - [2:0] */ 1124#define WM5100_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [2:0] */ 1125 1126/* 1127 * R388 (0x184) - FLL1 Control 3 1128 */ 1129#define WM5100_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */ 1130#define WM5100_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */ 1131#define WM5100_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */ 1132 1133/* 1134 * R390 (0x186) - FLL1 Control 5 1135 */ 1136#define WM5100_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */ 1137#define WM5100_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */ 1138#define WM5100_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */ 1139 1140/* 1141 * R391 (0x187) - FLL1 Control 6 1142 */ 1143#define WM5100_FLL1_REFCLK_DIV_MASK 0x00C0 /* FLL1_REFCLK_DIV - [7:6] */ 1144#define WM5100_FLL1_REFCLK_DIV_SHIFT 6 /* FLL1_REFCLK_DIV - [7:6] */ 1145#define WM5100_FLL1_REFCLK_DIV_WIDTH 2 /* FLL1_REFCLK_DIV - [7:6] */ 1146#define WM5100_FLL1_REFCLK_SRC_MASK 0x000F /* FLL1_REFCLK_SRC - [3:0] */ 1147#define WM5100_FLL1_REFCLK_SRC_SHIFT 0 /* FLL1_REFCLK_SRC - [3:0] */ 1148#define WM5100_FLL1_REFCLK_SRC_WIDTH 4 /* FLL1_REFCLK_SRC - [3:0] */ 1149 1150/* 1151 * R392 (0x188) - FLL1 EFS 1 1152 */ 1153#define WM5100_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */ 1154#define WM5100_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */ 1155#define WM5100_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */ 1156 1157/* 1158 * R418 (0x1A2) - FLL2 Control 1 1159 */ 1160#define WM5100_FLL2_ENA 0x0001 /* FLL2_ENA */ 1161#define WM5100_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */ 1162#define WM5100_FLL2_ENA_SHIFT 0 /* FLL2_ENA */ 1163#define WM5100_FLL2_ENA_WIDTH 1 /* FLL2_ENA */ 1164 1165/* 1166 * R419 (0x1A3) - FLL2 Control 2 1167 */ 1168#define WM5100_FLL2_OUTDIV_MASK 0x3F00 /* FLL2_OUTDIV - [13:8] */ 1169#define WM5100_FLL2_OUTDIV_SHIFT 8 /* FLL2_OUTDIV - [13:8] */ 1170#define WM5100_FLL2_OUTDIV_WIDTH 6 /* FLL2_OUTDIV - [13:8] */ 1171#define WM5100_FLL2_FRATIO_MASK 0x0007 /* FLL2_FRATIO - [2:0] */ 1172#define WM5100_FLL2_FRATIO_SHIFT 0 /* FLL2_FRATIO - [2:0] */ 1173#define WM5100_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [2:0] */ 1174 1175/* 1176 * R420 (0x1A4) - FLL2 Control 3 1177 */ 1178#define WM5100_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */ 1179#define WM5100_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */ 1180#define WM5100_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */ 1181 1182/* 1183 * R422 (0x1A6) - FLL2 Control 5 1184 */ 1185#define WM5100_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */ 1186#define WM5100_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */ 1187#define WM5100_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */ 1188 1189/* 1190 * R423 (0x1A7) - FLL2 Control 6 1191 */ 1192#define WM5100_FLL2_REFCLK_DIV_MASK 0x00C0 /* FLL2_REFCLK_DIV - [7:6] */ 1193#define WM5100_FLL2_REFCLK_DIV_SHIFT 6 /* FLL2_REFCLK_DIV - [7:6] */ 1194#define WM5100_FLL2_REFCLK_DIV_WIDTH 2 /* FLL2_REFCLK_DIV - [7:6] */ 1195#define WM5100_FLL2_REFCLK_SRC_MASK 0x000F /* FLL2_REFCLK_SRC - [3:0] */ 1196#define WM5100_FLL2_REFCLK_SRC_SHIFT 0 /* FLL2_REFCLK_SRC - [3:0] */ 1197#define WM5100_FLL2_REFCLK_SRC_WIDTH 4 /* FLL2_REFCLK_SRC - [3:0] */ 1198 1199/* 1200 * R424 (0x1A8) - FLL2 EFS 1 1201 */ 1202#define WM5100_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */ 1203#define WM5100_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */ 1204#define WM5100_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */ 1205 1206/* 1207 * R512 (0x200) - Mic Charge Pump 1 1208 */ 1209#define WM5100_CP2_BYPASS 0x0020 /* CP2_BYPASS */ 1210#define WM5100_CP2_BYPASS_MASK 0x0020 /* CP2_BYPASS */ 1211#define WM5100_CP2_BYPASS_SHIFT 5 /* CP2_BYPASS */ 1212#define WM5100_CP2_BYPASS_WIDTH 1 /* CP2_BYPASS */ 1213#define WM5100_CP2_ENA 0x0001 /* CP2_ENA */ 1214#define WM5100_CP2_ENA_MASK 0x0001 /* CP2_ENA */ 1215#define WM5100_CP2_ENA_SHIFT 0 /* CP2_ENA */ 1216#define WM5100_CP2_ENA_WIDTH 1 /* CP2_ENA */ 1217 1218/* 1219 * R513 (0x201) - Mic Charge Pump 2 1220 */ 1221#define WM5100_LDO2_VSEL_MASK 0xF800 /* LDO2_VSEL - [15:11] */ 1222#define WM5100_LDO2_VSEL_SHIFT 11 /* LDO2_VSEL - [15:11] */ 1223#define WM5100_LDO2_VSEL_WIDTH 5 /* LDO2_VSEL - [15:11] */ 1224 1225/* 1226 * R514 (0x202) - HP Charge Pump 1 1227 */ 1228#define WM5100_CP1_ENA 0x0001 /* CP1_ENA */ 1229#define WM5100_CP1_ENA_MASK 0x0001 /* CP1_ENA */ 1230#define WM5100_CP1_ENA_SHIFT 0 /* CP1_ENA */ 1231#define WM5100_CP1_ENA_WIDTH 1 /* CP1_ENA */ 1232 1233/* 1234 * R529 (0x211) - LDO1 Control 1235 */ 1236#define WM5100_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */ 1237#define WM5100_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */ 1238#define WM5100_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */ 1239#define WM5100_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */ 1240 1241/* 1242 * R533 (0x215) - Mic Bias Ctrl 1 1243 */ 1244#define WM5100_MICB1_DISCH 0x0040 /* MICB1_DISCH */ 1245#define WM5100_MICB1_DISCH_MASK 0x0040 /* MICB1_DISCH */ 1246#define WM5100_MICB1_DISCH_SHIFT 6 /* MICB1_DISCH */ 1247#define WM5100_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */ 1248#define WM5100_MICB1_RATE 0x0020 /* MICB1_RATE */ 1249#define WM5100_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */ 1250#define WM5100_MICB1_RATE_SHIFT 5 /* MICB1_RATE */ 1251#define WM5100_MICB1_RATE_WIDTH 1 /* MICB1_RATE */ 1252#define WM5100_MICB1_LVL_MASK 0x001C /* MICB1_LVL - [4:2] */ 1253#define WM5100_MICB1_LVL_SHIFT 2 /* MICB1_LVL - [4:2] */ 1254#define WM5100_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [4:2] */ 1255#define WM5100_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */ 1256#define WM5100_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */ 1257#define WM5100_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */ 1258#define WM5100_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */ 1259#define WM5100_MICB1_ENA 0x0001 /* MICB1_ENA */ 1260#define WM5100_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */ 1261#define WM5100_MICB1_ENA_SHIFT 0 /* MICB1_ENA */ 1262#define WM5100_MICB1_ENA_WIDTH 1 /* MICB1_ENA */ 1263 1264/* 1265 * R534 (0x216) - Mic Bias Ctrl 2 1266 */ 1267#define WM5100_MICB2_DISCH 0x0040 /* MICB2_DISCH */ 1268#define WM5100_MICB2_DISCH_MASK 0x0040 /* MICB2_DISCH */ 1269#define WM5100_MICB2_DISCH_SHIFT 6 /* MICB2_DISCH */ 1270#define WM5100_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */ 1271#define WM5100_MICB2_RATE 0x0020 /* MICB2_RATE */ 1272#define WM5100_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */ 1273#define WM5100_MICB2_RATE_SHIFT 5 /* MICB2_RATE */ 1274#define WM5100_MICB2_RATE_WIDTH 1 /* MICB2_RATE */ 1275#define WM5100_MICB2_LVL_MASK 0x001C /* MICB2_LVL - [4:2] */ 1276#define WM5100_MICB2_LVL_SHIFT 2 /* MICB2_LVL - [4:2] */ 1277#define WM5100_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [4:2] */ 1278#define WM5100_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */ 1279#define WM5100_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */ 1280#define WM5100_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */ 1281#define WM5100_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */ 1282#define WM5100_MICB2_ENA 0x0001 /* MICB2_ENA */ 1283#define WM5100_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */ 1284#define WM5100_MICB2_ENA_SHIFT 0 /* MICB2_ENA */ 1285#define WM5100_MICB2_ENA_WIDTH 1 /* MICB2_ENA */ 1286 1287/* 1288 * R535 (0x217) - Mic Bias Ctrl 3 1289 */ 1290#define WM5100_MICB3_DISCH 0x0040 /* MICB3_DISCH */ 1291#define WM5100_MICB3_DISCH_MASK 0x0040 /* MICB3_DISCH */ 1292#define WM5100_MICB3_DISCH_SHIFT 6 /* MICB3_DISCH */ 1293#define WM5100_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */ 1294#define WM5100_MICB3_RATE 0x0020 /* MICB3_RATE */ 1295#define WM5100_MICB3_RATE_MASK 0x0020 /* MICB3_RATE */ 1296#define WM5100_MICB3_RATE_SHIFT 5 /* MICB3_RATE */ 1297#define WM5100_MICB3_RATE_WIDTH 1 /* MICB3_RATE */ 1298#define WM5100_MICB3_LVL_MASK 0x001C /* MICB3_LVL - [4:2] */ 1299#define WM5100_MICB3_LVL_SHIFT 2 /* MICB3_LVL - [4:2] */ 1300#define WM5100_MICB3_LVL_WIDTH 3 /* MICB3_LVL - [4:2] */ 1301#define WM5100_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */ 1302#define WM5100_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */ 1303#define WM5100_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */ 1304#define WM5100_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */ 1305#define WM5100_MICB3_ENA 0x0001 /* MICB3_ENA */ 1306#define WM5100_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */ 1307#define WM5100_MICB3_ENA_SHIFT 0 /* MICB3_ENA */ 1308#define WM5100_MICB3_ENA_WIDTH 1 /* MICB3_ENA */ 1309 1310/* 1311 * R640 (0x280) - Accessory Detect Mode 1 1312 */ 1313#define WM5100_ACCDET_BIAS_SRC_MASK 0xC000 /* ACCDET_BIAS_SRC - [15:14] */ 1314#define WM5100_ACCDET_BIAS_SRC_SHIFT 14 /* ACCDET_BIAS_SRC - [15:14] */ 1315#define WM5100_ACCDET_BIAS_SRC_WIDTH 2 /* ACCDET_BIAS_SRC - [15:14] */ 1316#define WM5100_ACCDET_SRC 0x2000 /* ACCDET_SRC */ 1317#define WM5100_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */ 1318#define WM5100_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */ 1319#define WM5100_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */ 1320#define WM5100_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */ 1321#define WM5100_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */ 1322#define WM5100_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */ 1323 1324/* 1325 * R648 (0x288) - Headphone Detect 1 1326 */ 1327#define WM5100_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */ 1328#define WM5100_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */ 1329#define WM5100_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */ 1330#define WM5100_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */ 1331#define WM5100_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */ 1332#define WM5100_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */ 1333#define WM5100_HP_STEP_SIZE 0x0002 /* HP_STEP_SIZE */ 1334#define WM5100_HP_STEP_SIZE_MASK 0x0002 /* HP_STEP_SIZE */ 1335#define WM5100_HP_STEP_SIZE_SHIFT 1 /* HP_STEP_SIZE */ 1336#define WM5100_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */ 1337#define WM5100_HP_POLL 0x0001 /* HP_POLL */ 1338#define WM5100_HP_POLL_MASK 0x0001 /* HP_POLL */ 1339#define WM5100_HP_POLL_SHIFT 0 /* HP_POLL */ 1340#define WM5100_HP_POLL_WIDTH 1 /* HP_POLL */ 1341 1342/* 1343 * R649 (0x289) - Headphone Detect 2 1344 */ 1345#define WM5100_HP_DONE 0x0080 /* HP_DONE */ 1346#define WM5100_HP_DONE_MASK 0x0080 /* HP_DONE */ 1347#define WM5100_HP_DONE_SHIFT 7 /* HP_DONE */ 1348#define WM5100_HP_DONE_WIDTH 1 /* HP_DONE */ 1349#define WM5100_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */ 1350#define WM5100_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */ 1351#define WM5100_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */ 1352 1353/* 1354 * R656 (0x290) - Mic Detect 1 1355 */ 1356#define WM5100_ACCDET_BIAS_STARTTIME_MASK 0xF000 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1357#define WM5100_ACCDET_BIAS_STARTTIME_SHIFT 12 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1358#define WM5100_ACCDET_BIAS_STARTTIME_WIDTH 4 /* ACCDET_BIAS_STARTTIME - [15:12] */ 1359#define WM5100_ACCDET_RATE_MASK 0x0F00 /* ACCDET_RATE - [11:8] */ 1360#define WM5100_ACCDET_RATE_SHIFT 8 /* ACCDET_RATE - [11:8] */ 1361#define WM5100_ACCDET_RATE_WIDTH 4 /* ACCDET_RATE - [11:8] */ 1362#define WM5100_ACCDET_DBTIME 0x0002 /* ACCDET_DBTIME */ 1363#define WM5100_ACCDET_DBTIME_MASK 0x0002 /* ACCDET_DBTIME */ 1364#define WM5100_ACCDET_DBTIME_SHIFT 1 /* ACCDET_DBTIME */ 1365#define WM5100_ACCDET_DBTIME_WIDTH 1 /* ACCDET_DBTIME */ 1366#define WM5100_ACCDET_ENA 0x0001 /* ACCDET_ENA */ 1367#define WM5100_ACCDET_ENA_MASK 0x0001 /* ACCDET_ENA */ 1368#define WM5100_ACCDET_ENA_SHIFT 0 /* ACCDET_ENA */ 1369#define WM5100_ACCDET_ENA_WIDTH 1 /* ACCDET_ENA */ 1370 1371/* 1372 * R657 (0x291) - Mic Detect 2 1373 */ 1374#define WM5100_ACCDET_LVL_SEL_MASK 0x00FF /* ACCDET_LVL_SEL - [7:0] */ 1375#define WM5100_ACCDET_LVL_SEL_SHIFT 0 /* ACCDET_LVL_SEL - [7:0] */ 1376#define WM5100_ACCDET_LVL_SEL_WIDTH 8 /* ACCDET_LVL_SEL - [7:0] */ 1377 1378/* 1379 * R658 (0x292) - Mic Detect 3 1380 */ 1381#define WM5100_ACCDET_LVL_MASK 0x07FC /* ACCDET_LVL - [10:2] */ 1382#define WM5100_ACCDET_LVL_SHIFT 2 /* ACCDET_LVL - [10:2] */ 1383#define WM5100_ACCDET_LVL_WIDTH 9 /* ACCDET_LVL - [10:2] */ 1384#define WM5100_ACCDET_VALID 0x0002 /* ACCDET_VALID */ 1385#define WM5100_ACCDET_VALID_MASK 0x0002 /* ACCDET_VALID */ 1386#define WM5100_ACCDET_VALID_SHIFT 1 /* ACCDET_VALID */ 1387#define WM5100_ACCDET_VALID_WIDTH 1 /* ACCDET_VALID */ 1388#define WM5100_ACCDET_STS 0x0001 /* ACCDET_STS */ 1389#define WM5100_ACCDET_STS_MASK 0x0001 /* ACCDET_STS */ 1390#define WM5100_ACCDET_STS_SHIFT 0 /* ACCDET_STS */ 1391#define WM5100_ACCDET_STS_WIDTH 1 /* ACCDET_STS */ 1392 1393/* 1394 * R699 (0x2BB) - Misc Control 1395 */ 1396#define WM5100_HPCOM_SRC 0x200 /* HPCOM_SRC */ 1397#define WM5100_HPCOM_SRC_SHIFT 9 /* HPCOM_SRC */ 1398 1399/* 1400 * R769 (0x301) - Input Enables 1401 */ 1402#define WM5100_IN4L_ENA 0x0080 /* IN4L_ENA */ 1403#define WM5100_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */ 1404#define WM5100_IN4L_ENA_SHIFT 7 /* IN4L_ENA */ 1405#define WM5100_IN4L_ENA_WIDTH 1 /* IN4L_ENA */ 1406#define WM5100_IN4R_ENA 0x0040 /* IN4R_ENA */ 1407#define WM5100_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */ 1408#define WM5100_IN4R_ENA_SHIFT 6 /* IN4R_ENA */ 1409#define WM5100_IN4R_ENA_WIDTH 1 /* IN4R_ENA */ 1410#define WM5100_IN3L_ENA 0x0020 /* IN3L_ENA */ 1411#define WM5100_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */ 1412#define WM5100_IN3L_ENA_SHIFT 5 /* IN3L_ENA */ 1413#define WM5100_IN3L_ENA_WIDTH 1 /* IN3L_ENA */ 1414#define WM5100_IN3R_ENA 0x0010 /* IN3R_ENA */ 1415#define WM5100_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */ 1416#define WM5100_IN3R_ENA_SHIFT 4 /* IN3R_ENA */ 1417#define WM5100_IN3R_ENA_WIDTH 1 /* IN3R_ENA */ 1418#define WM5100_IN2L_ENA 0x0008 /* IN2L_ENA */ 1419#define WM5100_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */ 1420#define WM5100_IN2L_ENA_SHIFT 3 /* IN2L_ENA */ 1421#define WM5100_IN2L_ENA_WIDTH 1 /* IN2L_ENA */ 1422#define WM5100_IN2R_ENA 0x0004 /* IN2R_ENA */ 1423#define WM5100_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */ 1424#define WM5100_IN2R_ENA_SHIFT 2 /* IN2R_ENA */ 1425#define WM5100_IN2R_ENA_WIDTH 1 /* IN2R_ENA */ 1426#define WM5100_IN1L_ENA 0x0002 /* IN1L_ENA */ 1427#define WM5100_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */ 1428#define WM5100_IN1L_ENA_SHIFT 1 /* IN1L_ENA */ 1429#define WM5100_IN1L_ENA_WIDTH 1 /* IN1L_ENA */ 1430#define WM5100_IN1R_ENA 0x0001 /* IN1R_ENA */ 1431#define WM5100_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */ 1432#define WM5100_IN1R_ENA_SHIFT 0 /* IN1R_ENA */ 1433#define WM5100_IN1R_ENA_WIDTH 1 /* IN1R_ENA */ 1434 1435/* 1436 * R770 (0x302) - Input Enables Status 1437 */ 1438#define WM5100_IN4L_ENA_STS 0x0080 /* IN4L_ENA_STS */ 1439#define WM5100_IN4L_ENA_STS_MASK 0x0080 /* IN4L_ENA_STS */ 1440#define WM5100_IN4L_ENA_STS_SHIFT 7 /* IN4L_ENA_STS */ 1441#define WM5100_IN4L_ENA_STS_WIDTH 1 /* IN4L_ENA_STS */ 1442#define WM5100_IN4R_ENA_STS 0x0040 /* IN4R_ENA_STS */ 1443#define WM5100_IN4R_ENA_STS_MASK 0x0040 /* IN4R_ENA_STS */ 1444#define WM5100_IN4R_ENA_STS_SHIFT 6 /* IN4R_ENA_STS */ 1445#define WM5100_IN4R_ENA_STS_WIDTH 1 /* IN4R_ENA_STS */ 1446#define WM5100_IN3L_ENA_STS 0x0020 /* IN3L_ENA_STS */ 1447#define WM5100_IN3L_ENA_STS_MASK 0x0020 /* IN3L_ENA_STS */ 1448#define WM5100_IN3L_ENA_STS_SHIFT 5 /* IN3L_ENA_STS */ 1449#define WM5100_IN3L_ENA_STS_WIDTH 1 /* IN3L_ENA_STS */ 1450#define WM5100_IN3R_ENA_STS 0x0010 /* IN3R_ENA_STS */ 1451#define WM5100_IN3R_ENA_STS_MASK 0x0010 /* IN3R_ENA_STS */ 1452#define WM5100_IN3R_ENA_STS_SHIFT 4 /* IN3R_ENA_STS */ 1453#define WM5100_IN3R_ENA_STS_WIDTH 1 /* IN3R_ENA_STS */ 1454#define WM5100_IN2L_ENA_STS 0x0008 /* IN2L_ENA_STS */ 1455#define WM5100_IN2L_ENA_STS_MASK 0x0008 /* IN2L_ENA_STS */ 1456#define WM5100_IN2L_ENA_STS_SHIFT 3 /* IN2L_ENA_STS */ 1457#define WM5100_IN2L_ENA_STS_WIDTH 1 /* IN2L_ENA_STS */ 1458#define WM5100_IN2R_ENA_STS 0x0004 /* IN2R_ENA_STS */ 1459#define WM5100_IN2R_ENA_STS_MASK 0x0004 /* IN2R_ENA_STS */ 1460#define WM5100_IN2R_ENA_STS_SHIFT 2 /* IN2R_ENA_STS */ 1461#define WM5100_IN2R_ENA_STS_WIDTH 1 /* IN2R_ENA_STS */ 1462#define WM5100_IN1L_ENA_STS 0x0002 /* IN1L_ENA_STS */ 1463#define WM5100_IN1L_ENA_STS_MASK 0x0002 /* IN1L_ENA_STS */ 1464#define WM5100_IN1L_ENA_STS_SHIFT 1 /* IN1L_ENA_STS */ 1465#define WM5100_IN1L_ENA_STS_WIDTH 1 /* IN1L_ENA_STS */ 1466#define WM5100_IN1R_ENA_STS 0x0001 /* IN1R_ENA_STS */ 1467#define WM5100_IN1R_ENA_STS_MASK 0x0001 /* IN1R_ENA_STS */ 1468#define WM5100_IN1R_ENA_STS_SHIFT 0 /* IN1R_ENA_STS */ 1469#define WM5100_IN1R_ENA_STS_WIDTH 1 /* IN1R_ENA_STS */ 1470 1471/* 1472 * R784 (0x310) - IN1L Control 1473 */ 1474#define WM5100_IN_RATE_MASK 0xC000 /* IN_RATE - [15:14] */ 1475#define WM5100_IN_RATE_SHIFT 14 /* IN_RATE - [15:14] */ 1476#define WM5100_IN_RATE_WIDTH 2 /* IN_RATE - [15:14] */ 1477#define WM5100_IN1_OSR 0x2000 /* IN1_OSR */ 1478#define WM5100_IN1_OSR_MASK 0x2000 /* IN1_OSR */ 1479#define WM5100_IN1_OSR_SHIFT 13 /* IN1_OSR */ 1480#define WM5100_IN1_OSR_WIDTH 1 /* IN1_OSR */ 1481#define WM5100_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */ 1482#define WM5100_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */ 1483#define WM5100_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */ 1484#define WM5100_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */ 1485#define WM5100_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */ 1486#define WM5100_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */ 1487#define WM5100_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */ 1488#define WM5100_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */ 1489#define WM5100_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */ 1490 1491/* 1492 * R785 (0x311) - IN1R Control 1493 */ 1494#define WM5100_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */ 1495#define WM5100_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */ 1496#define WM5100_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */ 1497 1498/* 1499 * R786 (0x312) - IN2L Control 1500 */ 1501#define WM5100_IN2_OSR 0x2000 /* IN2_OSR */ 1502#define WM5100_IN2_OSR_MASK 0x2000 /* IN2_OSR */ 1503#define WM5100_IN2_OSR_SHIFT 13 /* IN2_OSR */ 1504#define WM5100_IN2_OSR_WIDTH 1 /* IN2_OSR */ 1505#define WM5100_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */ 1506#define WM5100_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */ 1507#define WM5100_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */ 1508#define WM5100_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */ 1509#define WM5100_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */ 1510#define WM5100_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */ 1511#define WM5100_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */ 1512#define WM5100_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */ 1513#define WM5100_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */ 1514 1515/* 1516 * R787 (0x313) - IN2R Control 1517 */ 1518#define WM5100_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */ 1519#define WM5100_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */ 1520#define WM5100_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */ 1521 1522/* 1523 * R788 (0x314) - IN3L Control 1524 */ 1525#define WM5100_IN3_OSR 0x2000 /* IN3_OSR */ 1526#define WM5100_IN3_OSR_MASK 0x2000 /* IN3_OSR */ 1527#define WM5100_IN3_OSR_SHIFT 13 /* IN3_OSR */ 1528#define WM5100_IN3_OSR_WIDTH 1 /* IN3_OSR */ 1529#define WM5100_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */ 1530#define WM5100_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */ 1531#define WM5100_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */ 1532#define WM5100_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */ 1533#define WM5100_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */ 1534#define WM5100_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */ 1535#define WM5100_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */ 1536#define WM5100_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */ 1537#define WM5100_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */ 1538 1539/* 1540 * R789 (0x315) - IN3R Control 1541 */ 1542#define WM5100_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */ 1543#define WM5100_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */ 1544#define WM5100_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */ 1545 1546/* 1547 * R790 (0x316) - IN4L Control 1548 */ 1549#define WM5100_IN4_OSR 0x2000 /* IN4_OSR */ 1550#define WM5100_IN4_OSR_MASK 0x2000 /* IN4_OSR */ 1551#define WM5100_IN4_OSR_SHIFT 13 /* IN4_OSR */ 1552#define WM5100_IN4_OSR_WIDTH 1 /* IN4_OSR */ 1553#define WM5100_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */ 1554#define WM5100_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */ 1555#define WM5100_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */ 1556#define WM5100_IN4_MODE_MASK 0x0600 /* IN4_MODE - [10:9] */ 1557#define WM5100_IN4_MODE_SHIFT 9 /* IN4_MODE - [10:9] */ 1558#define WM5100_IN4_MODE_WIDTH 2 /* IN4_MODE - [10:9] */ 1559#define WM5100_IN4L_PGA_VOL_MASK 0x00FE /* IN4L_PGA_VOL - [7:1] */ 1560#define WM5100_IN4L_PGA_VOL_SHIFT 1 /* IN4L_PGA_VOL - [7:1] */ 1561#define WM5100_IN4L_PGA_VOL_WIDTH 7 /* IN4L_PGA_VOL - [7:1] */ 1562 1563/* 1564 * R791 (0x317) - IN4R Control 1565 */ 1566#define WM5100_IN4R_PGA_VOL_MASK 0x00FE /* IN4R_PGA_VOL - [7:1] */ 1567#define WM5100_IN4R_PGA_VOL_SHIFT 1 /* IN4R_PGA_VOL - [7:1] */ 1568#define WM5100_IN4R_PGA_VOL_WIDTH 7 /* IN4R_PGA_VOL - [7:1] */ 1569 1570/* 1571 * R792 (0x318) - RXANC_SRC 1572 */ 1573#define WM5100_IN_RXANC_SEL_MASK 0x0007 /* IN_RXANC_SEL - [2:0] */ 1574#define WM5100_IN_RXANC_SEL_SHIFT 0 /* IN_RXANC_SEL - [2:0] */ 1575#define WM5100_IN_RXANC_SEL_WIDTH 3 /* IN_RXANC_SEL - [2:0] */ 1576 1577/* 1578 * R793 (0x319) - Input Volume Ramp 1579 */ 1580#define WM5100_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */ 1581#define WM5100_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */ 1582#define WM5100_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */ 1583#define WM5100_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */ 1584#define WM5100_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */ 1585#define WM5100_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */ 1586 1587/* 1588 * R800 (0x320) - ADC Digital Volume 1L 1589 */ 1590#define WM5100_IN_VU 0x0200 /* IN_VU */ 1591#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1592#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1593#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1594#define WM5100_IN1L_MUTE 0x0100 /* IN1L_MUTE */ 1595#define WM5100_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */ 1596#define WM5100_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */ 1597#define WM5100_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */ 1598#define WM5100_IN1L_VOL_MASK 0x00FF /* IN1L_VOL - [7:0] */ 1599#define WM5100_IN1L_VOL_SHIFT 0 /* IN1L_VOL - [7:0] */ 1600#define WM5100_IN1L_VOL_WIDTH 8 /* IN1L_VOL - [7:0] */ 1601 1602/* 1603 * R801 (0x321) - ADC Digital Volume 1R 1604 */ 1605#define WM5100_IN_VU 0x0200 /* IN_VU */ 1606#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1607#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1608#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1609#define WM5100_IN1R_MUTE 0x0100 /* IN1R_MUTE */ 1610#define WM5100_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */ 1611#define WM5100_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */ 1612#define WM5100_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */ 1613#define WM5100_IN1R_VOL_MASK 0x00FF /* IN1R_VOL - [7:0] */ 1614#define WM5100_IN1R_VOL_SHIFT 0 /* IN1R_VOL - [7:0] */ 1615#define WM5100_IN1R_VOL_WIDTH 8 /* IN1R_VOL - [7:0] */ 1616 1617/* 1618 * R802 (0x322) - ADC Digital Volume 2L 1619 */ 1620#define WM5100_IN_VU 0x0200 /* IN_VU */ 1621#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1622#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1623#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1624#define WM5100_IN2L_MUTE 0x0100 /* IN2L_MUTE */ 1625#define WM5100_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */ 1626#define WM5100_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */ 1627#define WM5100_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */ 1628#define WM5100_IN2L_VOL_MASK 0x00FF /* IN2L_VOL - [7:0] */ 1629#define WM5100_IN2L_VOL_SHIFT 0 /* IN2L_VOL - [7:0] */ 1630#define WM5100_IN2L_VOL_WIDTH 8 /* IN2L_VOL - [7:0] */ 1631 1632/* 1633 * R803 (0x323) - ADC Digital Volume 2R 1634 */ 1635#define WM5100_IN_VU 0x0200 /* IN_VU */ 1636#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1637#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1638#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1639#define WM5100_IN2R_MUTE 0x0100 /* IN2R_MUTE */ 1640#define WM5100_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */ 1641#define WM5100_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */ 1642#define WM5100_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */ 1643#define WM5100_IN2R_VOL_MASK 0x00FF /* IN2R_VOL - [7:0] */ 1644#define WM5100_IN2R_VOL_SHIFT 0 /* IN2R_VOL - [7:0] */ 1645#define WM5100_IN2R_VOL_WIDTH 8 /* IN2R_VOL - [7:0] */ 1646 1647/* 1648 * R804 (0x324) - ADC Digital Volume 3L 1649 */ 1650#define WM5100_IN_VU 0x0200 /* IN_VU */ 1651#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1652#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1653#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1654#define WM5100_IN3L_MUTE 0x0100 /* IN3L_MUTE */ 1655#define WM5100_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */ 1656#define WM5100_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */ 1657#define WM5100_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */ 1658#define WM5100_IN3L_VOL_MASK 0x00FF /* IN3L_VOL - [7:0] */ 1659#define WM5100_IN3L_VOL_SHIFT 0 /* IN3L_VOL - [7:0] */ 1660#define WM5100_IN3L_VOL_WIDTH 8 /* IN3L_VOL - [7:0] */ 1661 1662/* 1663 * R805 (0x325) - ADC Digital Volume 3R 1664 */ 1665#define WM5100_IN_VU 0x0200 /* IN_VU */ 1666#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1667#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1668#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1669#define WM5100_IN3R_MUTE 0x0100 /* IN3R_MUTE */ 1670#define WM5100_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */ 1671#define WM5100_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */ 1672#define WM5100_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */ 1673#define WM5100_IN3R_VOL_MASK 0x00FF /* IN3R_VOL - [7:0] */ 1674#define WM5100_IN3R_VOL_SHIFT 0 /* IN3R_VOL - [7:0] */ 1675#define WM5100_IN3R_VOL_WIDTH 8 /* IN3R_VOL - [7:0] */ 1676 1677/* 1678 * R806 (0x326) - ADC Digital Volume 4L 1679 */ 1680#define WM5100_IN_VU 0x0200 /* IN_VU */ 1681#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1682#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1683#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1684#define WM5100_IN4L_MUTE 0x0100 /* IN4L_MUTE */ 1685#define WM5100_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */ 1686#define WM5100_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */ 1687#define WM5100_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */ 1688#define WM5100_IN4L_VOL_MASK 0x00FF /* IN4L_VOL - [7:0] */ 1689#define WM5100_IN4L_VOL_SHIFT 0 /* IN4L_VOL - [7:0] */ 1690#define WM5100_IN4L_VOL_WIDTH 8 /* IN4L_VOL - [7:0] */ 1691 1692/* 1693 * R807 (0x327) - ADC Digital Volume 4R 1694 */ 1695#define WM5100_IN_VU 0x0200 /* IN_VU */ 1696#define WM5100_IN_VU_MASK 0x0200 /* IN_VU */ 1697#define WM5100_IN_VU_SHIFT 9 /* IN_VU */ 1698#define WM5100_IN_VU_WIDTH 1 /* IN_VU */ 1699#define WM5100_IN4R_MUTE 0x0100 /* IN4R_MUTE */ 1700#define WM5100_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */ 1701#define WM5100_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */ 1702#define WM5100_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */ 1703#define WM5100_IN4R_VOL_MASK 0x00FF /* IN4R_VOL - [7:0] */ 1704#define WM5100_IN4R_VOL_SHIFT 0 /* IN4R_VOL - [7:0] */ 1705#define WM5100_IN4R_VOL_WIDTH 8 /* IN4R_VOL - [7:0] */ 1706 1707/* 1708 * R1025 (0x401) - Output Enables 2 1709 */ 1710#define WM5100_OUT6L_ENA 0x0800 /* OUT6L_ENA */ 1711#define WM5100_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */ 1712#define WM5100_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */ 1713#define WM5100_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */ 1714#define WM5100_OUT6R_ENA 0x0400 /* OUT6R_ENA */ 1715#define WM5100_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */ 1716#define WM5100_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */ 1717#define WM5100_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */ 1718#define WM5100_OUT5L_ENA 0x0200 /* OUT5L_ENA */ 1719#define WM5100_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */ 1720#define WM5100_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */ 1721#define WM5100_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */ 1722#define WM5100_OUT5R_ENA 0x0100 /* OUT5R_ENA */ 1723#define WM5100_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */ 1724#define WM5100_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */ 1725#define WM5100_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */ 1726#define WM5100_OUT4L_ENA 0x0080 /* OUT4L_ENA */ 1727#define WM5100_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */ 1728#define WM5100_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */ 1729#define WM5100_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */ 1730#define WM5100_OUT4R_ENA 0x0040 /* OUT4R_ENA */ 1731#define WM5100_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */ 1732#define WM5100_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */ 1733#define WM5100_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */ 1734 1735/* 1736 * R1026 (0x402) - Output Status 1 1737 */ 1738#define WM5100_OUT3L_ENA_STS 0x0020 /* OUT3L_ENA_STS */ 1739#define WM5100_OUT3L_ENA_STS_MASK 0x0020 /* OUT3L_ENA_STS */ 1740#define WM5100_OUT3L_ENA_STS_SHIFT 5 /* OUT3L_ENA_STS */ 1741#define WM5100_OUT3L_ENA_STS_WIDTH 1 /* OUT3L_ENA_STS */ 1742#define WM5100_OUT3R_ENA_STS 0x0010 /* OUT3R_ENA_STS */ 1743#define WM5100_OUT3R_ENA_STS_MASK 0x0010 /* OUT3R_ENA_STS */ 1744#define WM5100_OUT3R_ENA_STS_SHIFT 4 /* OUT3R_ENA_STS */ 1745#define WM5100_OUT3R_ENA_STS_WIDTH 1 /* OUT3R_ENA_STS */ 1746#define WM5100_OUT2L_ENA_STS 0x0008 /* OUT2L_ENA_STS */ 1747#define WM5100_OUT2L_ENA_STS_MASK 0x0008 /* OUT2L_ENA_STS */ 1748#define WM5100_OUT2L_ENA_STS_SHIFT 3 /* OUT2L_ENA_STS */ 1749#define WM5100_OUT2L_ENA_STS_WIDTH 1 /* OUT2L_ENA_STS */ 1750#define WM5100_OUT2R_ENA_STS 0x0004 /* OUT2R_ENA_STS */ 1751#define WM5100_OUT2R_ENA_STS_MASK 0x0004 /* OUT2R_ENA_STS */ 1752#define WM5100_OUT2R_ENA_STS_SHIFT 2 /* OUT2R_ENA_STS */ 1753#define WM5100_OUT2R_ENA_STS_WIDTH 1 /* OUT2R_ENA_STS */ 1754#define WM5100_OUT1L_ENA_STS 0x0002 /* OUT1L_ENA_STS */ 1755#define WM5100_OUT1L_ENA_STS_MASK 0x0002 /* OUT1L_ENA_STS */ 1756#define WM5100_OUT1L_ENA_STS_SHIFT 1 /* OUT1L_ENA_STS */ 1757#define WM5100_OUT1L_ENA_STS_WIDTH 1 /* OUT1L_ENA_STS */ 1758#define WM5100_OUT1R_ENA_STS 0x0001 /* OUT1R_ENA_STS */ 1759#define WM5100_OUT1R_ENA_STS_MASK 0x0001 /* OUT1R_ENA_STS */ 1760#define WM5100_OUT1R_ENA_STS_SHIFT 0 /* OUT1R_ENA_STS */ 1761#define WM5100_OUT1R_ENA_STS_WIDTH 1 /* OUT1R_ENA_STS */ 1762 1763/* 1764 * R1027 (0x403) - Output Status 2 1765 */ 1766#define WM5100_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */ 1767#define WM5100_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */ 1768#define WM5100_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */ 1769#define WM5100_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */ 1770#define WM5100_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */ 1771#define WM5100_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */ 1772#define WM5100_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */ 1773#define WM5100_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */ 1774#define WM5100_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */ 1775#define WM5100_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */ 1776#define WM5100_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */ 1777#define WM5100_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */ 1778#define WM5100_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */ 1779#define WM5100_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */ 1780#define WM5100_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */ 1781#define WM5100_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */ 1782#define WM5100_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */ 1783#define WM5100_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */ 1784#define WM5100_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */ 1785#define WM5100_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */ 1786#define WM5100_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */ 1787#define WM5100_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */ 1788#define WM5100_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */ 1789#define WM5100_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */ 1790 1791/* 1792 * R1032 (0x408) - Channel Enables 1 1793 */ 1794#define WM5100_HP3L_ENA 0x0020 /* HP3L_ENA */ 1795#define WM5100_HP3L_ENA_MASK 0x0020 /* HP3L_ENA */ 1796#define WM5100_HP3L_ENA_SHIFT 5 /* HP3L_ENA */ 1797#define WM5100_HP3L_ENA_WIDTH 1 /* HP3L_ENA */ 1798#define WM5100_HP3R_ENA 0x0010 /* HP3R_ENA */ 1799#define WM5100_HP3R_ENA_MASK 0x0010 /* HP3R_ENA */ 1800#define WM5100_HP3R_ENA_SHIFT 4 /* HP3R_ENA */ 1801#define WM5100_HP3R_ENA_WIDTH 1 /* HP3R_ENA */ 1802#define WM5100_HP2L_ENA 0x0008 /* HP2L_ENA */ 1803#define WM5100_HP2L_ENA_MASK 0x0008 /* HP2L_ENA */ 1804#define WM5100_HP2L_ENA_SHIFT 3 /* HP2L_ENA */ 1805#define WM5100_HP2L_ENA_WIDTH 1 /* HP2L_ENA */ 1806#define WM5100_HP2R_ENA 0x0004 /* HP2R_ENA */ 1807#define WM5100_HP2R_ENA_MASK 0x0004 /* HP2R_ENA */ 1808#define WM5100_HP2R_ENA_SHIFT 2 /* HP2R_ENA */ 1809#define WM5100_HP2R_ENA_WIDTH 1 /* HP2R_ENA */ 1810#define WM5100_HP1L_ENA 0x0002 /* HP1L_ENA */ 1811#define WM5100_HP1L_ENA_MASK 0x0002 /* HP1L_ENA */ 1812#define WM5100_HP1L_ENA_SHIFT 1 /* HP1L_ENA */ 1813#define WM5100_HP1L_ENA_WIDTH 1 /* HP1L_ENA */ 1814#define WM5100_HP1R_ENA 0x0001 /* HP1R_ENA */ 1815#define WM5100_HP1R_ENA_MASK 0x0001 /* HP1R_ENA */ 1816#define WM5100_HP1R_ENA_SHIFT 0 /* HP1R_ENA */ 1817#define WM5100_HP1R_ENA_WIDTH 1 /* HP1R_ENA */ 1818 1819/* 1820 * R1040 (0x410) - Out Volume 1L 1821 */ 1822#define WM5100_OUT_RATE_MASK 0xC000 /* OUT_RATE - [15:14] */ 1823#define WM5100_OUT_RATE_SHIFT 14 /* OUT_RATE - [15:14] */ 1824#define WM5100_OUT_RATE_WIDTH 2 /* OUT_RATE - [15:14] */ 1825#define WM5100_OUT1_OSR 0x2000 /* OUT1_OSR */ 1826#define WM5100_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */ 1827#define WM5100_OUT1_OSR_SHIFT 13 /* OUT1_OSR */ 1828#define WM5100_OUT1_OSR_WIDTH 1 /* OUT1_OSR */ 1829#define WM5100_OUT1_MONO 0x1000 /* OUT1_MONO */ 1830#define WM5100_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */ 1831#define WM5100_OUT1_MONO_SHIFT 12 /* OUT1_MONO */ 1832#define WM5100_OUT1_MONO_WIDTH 1 /* OUT1_MONO */ 1833#define WM5100_OUT1L_ANC_SRC 0x0800 /* OUT1L_ANC_SRC */ 1834#define WM5100_OUT1L_ANC_SRC_MASK 0x0800 /* OUT1L_ANC_SRC */ 1835#define WM5100_OUT1L_ANC_SRC_SHIFT 11 /* OUT1L_ANC_SRC */ 1836#define WM5100_OUT1L_ANC_SRC_WIDTH 1 /* OUT1L_ANC_SRC */ 1837#define WM5100_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */ 1838#define WM5100_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */ 1839#define WM5100_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */ 1840 1841/* 1842 * R1041 (0x411) - Out Volume 1R 1843 */ 1844#define WM5100_OUT1R_ANC_SRC 0x0800 /* OUT1R_ANC_SRC */ 1845#define WM5100_OUT1R_ANC_SRC_MASK 0x0800 /* OUT1R_ANC_SRC */ 1846#define WM5100_OUT1R_ANC_SRC_SHIFT 11 /* OUT1R_ANC_SRC */ 1847#define WM5100_OUT1R_ANC_SRC_WIDTH 1 /* OUT1R_ANC_SRC */ 1848#define WM5100_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */ 1849#define WM5100_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */ 1850#define WM5100_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */ 1851 1852/* 1853 * R1042 (0x412) - DAC Volume Limit 1L 1854 */ 1855#define WM5100_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */ 1856#define WM5100_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */ 1857#define WM5100_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */ 1858 1859/* 1860 * R1043 (0x413) - DAC Volume Limit 1R 1861 */ 1862#define WM5100_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */ 1863#define WM5100_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */ 1864#define WM5100_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */ 1865 1866/* 1867 * R1044 (0x414) - Out Volume 2L 1868 */ 1869#define WM5100_OUT2_OSR 0x2000 /* OUT2_OSR */ 1870#define WM5100_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */ 1871#define WM5100_OUT2_OSR_SHIFT 13 /* OUT2_OSR */ 1872#define WM5100_OUT2_OSR_WIDTH 1 /* OUT2_OSR */ 1873#define WM5100_OUT2_MONO 0x1000 /* OUT2_MONO */ 1874#define WM5100_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */ 1875#define WM5100_OUT2_MONO_SHIFT 12 /* OUT2_MONO */ 1876#define WM5100_OUT2_MONO_WIDTH 1 /* OUT2_MONO */ 1877#define WM5100_OUT2L_ANC_SRC 0x0800 /* OUT2L_ANC_SRC */ 1878#define WM5100_OUT2L_ANC_SRC_MASK 0x0800 /* OUT2L_ANC_SRC */ 1879#define WM5100_OUT2L_ANC_SRC_SHIFT 11 /* OUT2L_ANC_SRC */ 1880#define WM5100_OUT2L_ANC_SRC_WIDTH 1 /* OUT2L_ANC_SRC */ 1881#define WM5100_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */ 1882#define WM5100_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */ 1883#define WM5100_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */ 1884 1885/* 1886 * R1045 (0x415) - Out Volume 2R 1887 */ 1888#define WM5100_OUT2R_ANC_SRC 0x0800 /* OUT2R_ANC_SRC */ 1889#define WM5100_OUT2R_ANC_SRC_MASK 0x0800 /* OUT2R_ANC_SRC */ 1890#define WM5100_OUT2R_ANC_SRC_SHIFT 11 /* OUT2R_ANC_SRC */ 1891#define WM5100_OUT2R_ANC_SRC_WIDTH 1 /* OUT2R_ANC_SRC */ 1892#define WM5100_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */ 1893#define WM5100_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */ 1894#define WM5100_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */ 1895 1896/* 1897 * R1046 (0x416) - DAC Volume Limit 2L 1898 */ 1899#define WM5100_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */ 1900#define WM5100_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */ 1901#define WM5100_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */ 1902 1903/* 1904 * R1047 (0x417) - DAC Volume Limit 2R 1905 */ 1906#define WM5100_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */ 1907#define WM5100_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */ 1908#define WM5100_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */ 1909 1910/* 1911 * R1048 (0x418) - Out Volume 3L 1912 */ 1913#define WM5100_OUT3_OSR 0x2000 /* OUT3_OSR */ 1914#define WM5100_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */ 1915#define WM5100_OUT3_OSR_SHIFT 13 /* OUT3_OSR */ 1916#define WM5100_OUT3_OSR_WIDTH 1 /* OUT3_OSR */ 1917#define WM5100_OUT3_MONO 0x1000 /* OUT3_MONO */ 1918#define WM5100_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */ 1919#define WM5100_OUT3_MONO_SHIFT 12 /* OUT3_MONO */ 1920#define WM5100_OUT3_MONO_WIDTH 1 /* OUT3_MONO */ 1921#define WM5100_OUT3L_ANC_SRC 0x0800 /* OUT3L_ANC_SRC */ 1922#define WM5100_OUT3L_ANC_SRC_MASK 0x0800 /* OUT3L_ANC_SRC */ 1923#define WM5100_OUT3L_ANC_SRC_SHIFT 11 /* OUT3L_ANC_SRC */ 1924#define WM5100_OUT3L_ANC_SRC_WIDTH 1 /* OUT3L_ANC_SRC */ 1925#define WM5100_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */ 1926#define WM5100_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */ 1927#define WM5100_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */ 1928 1929/* 1930 * R1049 (0x419) - Out Volume 3R 1931 */ 1932#define WM5100_OUT3R_ANC_SRC 0x0800 /* OUT3R_ANC_SRC */ 1933#define WM5100_OUT3R_ANC_SRC_MASK 0x0800 /* OUT3R_ANC_SRC */ 1934#define WM5100_OUT3R_ANC_SRC_SHIFT 11 /* OUT3R_ANC_SRC */ 1935#define WM5100_OUT3R_ANC_SRC_WIDTH 1 /* OUT3R_ANC_SRC */ 1936#define WM5100_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */ 1937#define WM5100_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */ 1938#define WM5100_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */ 1939 1940/* 1941 * R1050 (0x41A) - DAC Volume Limit 3L 1942 */ 1943#define WM5100_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */ 1944#define WM5100_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */ 1945#define WM5100_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */ 1946 1947/* 1948 * R1051 (0x41B) - DAC Volume Limit 3R 1949 */ 1950#define WM5100_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */ 1951#define WM5100_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */ 1952#define WM5100_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */ 1953 1954/* 1955 * R1052 (0x41C) - Out Volume 4L 1956 */ 1957#define WM5100_OUT4_OSR 0x2000 /* OUT4_OSR */ 1958#define WM5100_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */ 1959#define WM5100_OUT4_OSR_SHIFT 13 /* OUT4_OSR */ 1960#define WM5100_OUT4_OSR_WIDTH 1 /* OUT4_OSR */ 1961#define WM5100_OUT4L_ANC_SRC 0x0800 /* OUT4L_ANC_SRC */ 1962#define WM5100_OUT4L_ANC_SRC_MASK 0x0800 /* OUT4L_ANC_SRC */ 1963#define WM5100_OUT4L_ANC_SRC_SHIFT 11 /* OUT4L_ANC_SRC */ 1964#define WM5100_OUT4L_ANC_SRC_WIDTH 1 /* OUT4L_ANC_SRC */ 1965#define WM5100_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */ 1966#define WM5100_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */ 1967#define WM5100_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */ 1968 1969/* 1970 * R1053 (0x41D) - Out Volume 4R 1971 */ 1972#define WM5100_OUT4R_ANC_SRC 0x0800 /* OUT4R_ANC_SRC */ 1973#define WM5100_OUT4R_ANC_SRC_MASK 0x0800 /* OUT4R_ANC_SRC */ 1974#define WM5100_OUT4R_ANC_SRC_SHIFT 11 /* OUT4R_ANC_SRC */ 1975#define WM5100_OUT4R_ANC_SRC_WIDTH 1 /* OUT4R_ANC_SRC */ 1976#define WM5100_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */ 1977#define WM5100_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */ 1978#define WM5100_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */ 1979 1980/* 1981 * R1054 (0x41E) - DAC Volume Limit 5L 1982 */ 1983#define WM5100_OUT5_OSR 0x2000 /* OUT5_OSR */ 1984#define WM5100_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */ 1985#define WM5100_OUT5_OSR_SHIFT 13 /* OUT5_OSR */ 1986#define WM5100_OUT5_OSR_WIDTH 1 /* OUT5_OSR */ 1987#define WM5100_OUT5L_ANC_SRC 0x0800 /* OUT5L_ANC_SRC */ 1988#define WM5100_OUT5L_ANC_SRC_MASK 0x0800 /* OUT5L_ANC_SRC */ 1989#define WM5100_OUT5L_ANC_SRC_SHIFT 11 /* OUT5L_ANC_SRC */ 1990#define WM5100_OUT5L_ANC_SRC_WIDTH 1 /* OUT5L_ANC_SRC */ 1991#define WM5100_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */ 1992#define WM5100_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */ 1993#define WM5100_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */ 1994 1995/* 1996 * R1055 (0x41F) - DAC Volume Limit 5R 1997 */ 1998#define WM5100_OUT5R_ANC_SRC 0x0800 /* OUT5R_ANC_SRC */ 1999#define WM5100_OUT5R_ANC_SRC_MASK 0x0800 /* OUT5R_ANC_SRC */ 2000#define WM5100_OUT5R_ANC_SRC_SHIFT 11 /* OUT5R_ANC_SRC */ 2001#define WM5100_OUT5R_ANC_SRC_WIDTH 1 /* OUT5R_ANC_SRC */ 2002#define WM5100_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */ 2003#define WM5100_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */ 2004#define WM5100_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */ 2005 2006/* 2007 * R1056 (0x420) - DAC Volume Limit 6L 2008 */ 2009#define WM5100_OUT6_OSR 0x2000 /* OUT6_OSR */ 2010#define WM5100_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */ 2011#define WM5100_OUT6_OSR_SHIFT 13 /* OUT6_OSR */ 2012#define WM5100_OUT6_OSR_WIDTH 1 /* OUT6_OSR */ 2013#define WM5100_OUT6L_ANC_SRC 0x0800 /* OUT6L_ANC_SRC */ 2014#define WM5100_OUT6L_ANC_SRC_MASK 0x0800 /* OUT6L_ANC_SRC */ 2015#define WM5100_OUT6L_ANC_SRC_SHIFT 11 /* OUT6L_ANC_SRC */ 2016#define WM5100_OUT6L_ANC_SRC_WIDTH 1 /* OUT6L_ANC_SRC */ 2017#define WM5100_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */ 2018#define WM5100_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */ 2019#define WM5100_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */ 2020 2021/* 2022 * R1057 (0x421) - DAC Volume Limit 6R 2023 */ 2024#define WM5100_OUT6R_ANC_SRC 0x0800 /* OUT6R_ANC_SRC */ 2025#define WM5100_OUT6R_ANC_SRC_MASK 0x0800 /* OUT6R_ANC_SRC */ 2026#define WM5100_OUT6R_ANC_SRC_SHIFT 11 /* OUT6R_ANC_SRC */ 2027#define WM5100_OUT6R_ANC_SRC_WIDTH 1 /* OUT6R_ANC_SRC */ 2028#define WM5100_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */ 2029#define WM5100_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */ 2030#define WM5100_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */ 2031 2032/* 2033 * R1088 (0x440) - DAC AEC Control 1 2034 */ 2035#define WM5100_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */ 2036#define WM5100_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */ 2037#define WM5100_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */ 2038#define WM5100_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */ 2039#define WM5100_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */ 2040#define WM5100_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */ 2041#define WM5100_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */ 2042#define WM5100_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */ 2043#define WM5100_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */ 2044#define WM5100_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */ 2045#define WM5100_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */ 2046 2047/* 2048 * R1089 (0x441) - Output Volume Ramp 2049 */ 2050#define WM5100_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */ 2051#define WM5100_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */ 2052#define WM5100_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */ 2053#define WM5100_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */ 2054#define WM5100_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */ 2055#define WM5100_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */ 2056 2057/* 2058 * R1152 (0x480) - DAC Digital Volume 1L 2059 */ 2060#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2061#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2062#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2063#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2064#define WM5100_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */ 2065#define WM5100_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */ 2066#define WM5100_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */ 2067#define WM5100_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */ 2068#define WM5100_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */ 2069#define WM5100_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */ 2070#define WM5100_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */ 2071 2072/* 2073 * R1153 (0x481) - DAC Digital Volume 1R 2074 */ 2075#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2076#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2077#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2078#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2079#define WM5100_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */ 2080#define WM5100_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */ 2081#define WM5100_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */ 2082#define WM5100_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */ 2083#define WM5100_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */ 2084#define WM5100_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */ 2085#define WM5100_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */ 2086 2087/* 2088 * R1154 (0x482) - DAC Digital Volume 2L 2089 */ 2090#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2091#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2092#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2093#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2094#define WM5100_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */ 2095#define WM5100_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */ 2096#define WM5100_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */ 2097#define WM5100_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */ 2098#define WM5100_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */ 2099#define WM5100_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */ 2100#define WM5100_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */ 2101 2102/* 2103 * R1155 (0x483) - DAC Digital Volume 2R 2104 */ 2105#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2106#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2107#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2108#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2109#define WM5100_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */ 2110#define WM5100_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */ 2111#define WM5100_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */ 2112#define WM5100_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */ 2113#define WM5100_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */ 2114#define WM5100_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */ 2115#define WM5100_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */ 2116 2117/* 2118 * R1156 (0x484) - DAC Digital Volume 3L 2119 */ 2120#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2121#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2122#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2123#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2124#define WM5100_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */ 2125#define WM5100_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */ 2126#define WM5100_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */ 2127#define WM5100_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */ 2128#define WM5100_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */ 2129#define WM5100_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */ 2130#define WM5100_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */ 2131 2132/* 2133 * R1157 (0x485) - DAC Digital Volume 3R 2134 */ 2135#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2136#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2137#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2138#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2139#define WM5100_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */ 2140#define WM5100_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */ 2141#define WM5100_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */ 2142#define WM5100_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */ 2143#define WM5100_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */ 2144#define WM5100_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */ 2145#define WM5100_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */ 2146 2147/* 2148 * R1158 (0x486) - DAC Digital Volume 4L 2149 */ 2150#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2151#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2152#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2153#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2154#define WM5100_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */ 2155#define WM5100_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */ 2156#define WM5100_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */ 2157#define WM5100_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */ 2158#define WM5100_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */ 2159#define WM5100_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */ 2160#define WM5100_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */ 2161 2162/* 2163 * R1159 (0x487) - DAC Digital Volume 4R 2164 */ 2165#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2166#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2167#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2168#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2169#define WM5100_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */ 2170#define WM5100_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */ 2171#define WM5100_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */ 2172#define WM5100_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */ 2173#define WM5100_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */ 2174#define WM5100_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */ 2175#define WM5100_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */ 2176 2177/* 2178 * R1160 (0x488) - DAC Digital Volume 5L 2179 */ 2180#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2181#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2182#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2183#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2184#define WM5100_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */ 2185#define WM5100_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */ 2186#define WM5100_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */ 2187#define WM5100_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */ 2188#define WM5100_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */ 2189#define WM5100_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */ 2190#define WM5100_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */ 2191 2192/* 2193 * R1161 (0x489) - DAC Digital Volume 5R 2194 */ 2195#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2196#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2197#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2198#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2199#define WM5100_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */ 2200#define WM5100_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */ 2201#define WM5100_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */ 2202#define WM5100_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */ 2203#define WM5100_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */ 2204#define WM5100_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */ 2205#define WM5100_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */ 2206 2207/* 2208 * R1162 (0x48A) - DAC Digital Volume 6L 2209 */ 2210#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2211#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2212#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2213#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2214#define WM5100_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */ 2215#define WM5100_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */ 2216#define WM5100_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */ 2217#define WM5100_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */ 2218#define WM5100_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */ 2219#define WM5100_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */ 2220#define WM5100_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */ 2221 2222/* 2223 * R1163 (0x48B) - DAC Digital Volume 6R 2224 */ 2225#define WM5100_OUT_VU 0x0200 /* OUT_VU */ 2226#define WM5100_OUT_VU_MASK 0x0200 /* OUT_VU */ 2227#define WM5100_OUT_VU_SHIFT 9 /* OUT_VU */ 2228#define WM5100_OUT_VU_WIDTH 1 /* OUT_VU */ 2229#define WM5100_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */ 2230#define WM5100_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */ 2231#define WM5100_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */ 2232#define WM5100_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */ 2233#define WM5100_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */ 2234#define WM5100_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */ 2235#define WM5100_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */ 2236 2237/* 2238 * R1216 (0x4C0) - PDM SPK1 CTRL 1 2239 */ 2240#define WM5100_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */ 2241#define WM5100_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */ 2242#define WM5100_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */ 2243#define WM5100_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */ 2244#define WM5100_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */ 2245#define WM5100_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */ 2246#define WM5100_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */ 2247#define WM5100_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */ 2248#define WM5100_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */ 2249#define WM5100_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */ 2250#define WM5100_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */ 2251#define WM5100_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */ 2252#define WM5100_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */ 2253#define WM5100_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */ 2254#define WM5100_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */ 2255 2256/* 2257 * R1217 (0x4C1) - PDM SPK1 CTRL 2 2258 */ 2259#define WM5100_SPK1_FMT 0x0001 /* SPK1_FMT */ 2260#define WM5100_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */ 2261#define WM5100_SPK1_FMT_SHIFT 0 /* SPK1_FMT */ 2262#define WM5100_SPK1_FMT_WIDTH 1 /* SPK1_FMT */ 2263 2264/* 2265 * R1218 (0x4C2) - PDM SPK2 CTRL 1 2266 */ 2267#define WM5100_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */ 2268#define WM5100_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */ 2269#define WM5100_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */ 2270#define WM5100_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */ 2271#define WM5100_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */ 2272#define WM5100_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */ 2273#define WM5100_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */ 2274#define WM5100_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */ 2275#define WM5100_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */ 2276#define WM5100_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */ 2277#define WM5100_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */ 2278#define WM5100_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */ 2279#define WM5100_SPK2_MUTE_SEQ1_MASK 0x00FF /* SPK2_MUTE_SEQ1 - [7:0] */ 2280#define WM5100_SPK2_MUTE_SEQ1_SHIFT 0 /* SPK2_MUTE_SEQ1 - [7:0] */ 2281#define WM5100_SPK2_MUTE_SEQ1_WIDTH 8 /* SPK2_MUTE_SEQ1 - [7:0] */ 2282 2283/* 2284 * R1219 (0x4C3) - PDM SPK2 CTRL 2 2285 */ 2286#define WM5100_SPK2_FMT 0x0001 /* SPK2_FMT */ 2287#define WM5100_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */ 2288#define WM5100_SPK2_FMT_SHIFT 0 /* SPK2_FMT */ 2289#define WM5100_SPK2_FMT_WIDTH 1 /* SPK2_FMT */ 2290 2291/* 2292 * R1280 (0x500) - Audio IF 1_1 2293 */ 2294#define WM5100_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */ 2295#define WM5100_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */ 2296#define WM5100_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */ 2297#define WM5100_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */ 2298#define WM5100_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */ 2299#define WM5100_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */ 2300#define WM5100_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */ 2301#define WM5100_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */ 2302#define WM5100_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */ 2303#define WM5100_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */ 2304#define WM5100_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */ 2305#define WM5100_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */ 2306#define WM5100_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */ 2307#define WM5100_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */ 2308#define WM5100_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */ 2309 2310/* 2311 * R1281 (0x501) - Audio IF 1_2 2312 */ 2313#define WM5100_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */ 2314#define WM5100_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */ 2315#define WM5100_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */ 2316#define WM5100_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */ 2317#define WM5100_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */ 2318#define WM5100_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */ 2319#define WM5100_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */ 2320#define WM5100_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */ 2321#define WM5100_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */ 2322#define WM5100_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */ 2323#define WM5100_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */ 2324#define WM5100_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */ 2325#define WM5100_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */ 2326#define WM5100_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */ 2327#define WM5100_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */ 2328#define WM5100_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */ 2329#define WM5100_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */ 2330#define WM5100_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */ 2331#define WM5100_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */ 2332#define WM5100_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */ 2333 2334/* 2335 * R1282 (0x502) - Audio IF 1_3 2336 */ 2337#define WM5100_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */ 2338#define WM5100_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */ 2339#define WM5100_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */ 2340#define WM5100_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */ 2341#define WM5100_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */ 2342#define WM5100_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */ 2343#define WM5100_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */ 2344#define WM5100_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */ 2345#define WM5100_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */ 2346#define WM5100_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */ 2347#define WM5100_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */ 2348#define WM5100_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */ 2349 2350/* 2351 * R1283 (0x503) - Audio IF 1_4 2352 */ 2353#define WM5100_AIF1_TRI 0x0040 /* AIF1_TRI */ 2354#define WM5100_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */ 2355#define WM5100_AIF1_TRI_SHIFT 6 /* AIF1_TRI */ 2356#define WM5100_AIF1_TRI_WIDTH 1 /* AIF1_TRI */ 2357#define WM5100_AIF1_RATE_MASK 0x0003 /* AIF1_RATE - [1:0] */ 2358#define WM5100_AIF1_RATE_SHIFT 0 /* AIF1_RATE - [1:0] */ 2359#define WM5100_AIF1_RATE_WIDTH 2 /* AIF1_RATE - [1:0] */ 2360 2361/* 2362 * R1284 (0x504) - Audio IF 1_5 2363 */ 2364#define WM5100_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */ 2365#define WM5100_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */ 2366#define WM5100_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */ 2367 2368/* 2369 * R1285 (0x505) - Audio IF 1_6 2370 */ 2371#define WM5100_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */ 2372#define WM5100_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */ 2373#define WM5100_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */ 2374 2375/* 2376 * R1286 (0x506) - Audio IF 1_7 2377 */ 2378#define WM5100_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */ 2379#define WM5100_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */ 2380#define WM5100_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */ 2381 2382/* 2383 * R1287 (0x507) - Audio IF 1_8 2384 */ 2385#define WM5100_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */ 2386#define WM5100_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */ 2387#define WM5100_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */ 2388#define WM5100_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */ 2389#define WM5100_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */ 2390#define WM5100_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */ 2391 2392/* 2393 * R1288 (0x508) - Audio IF 1_9 2394 */ 2395#define WM5100_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */ 2396#define WM5100_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */ 2397#define WM5100_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */ 2398#define WM5100_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */ 2399#define WM5100_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */ 2400#define WM5100_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */ 2401 2402/* 2403 * R1289 (0x509) - Audio IF 1_10 2404 */ 2405#define WM5100_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */ 2406#define WM5100_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */ 2407#define WM5100_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */ 2408 2409/* 2410 * R1290 (0x50A) - Audio IF 1_11 2411 */ 2412#define WM5100_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */ 2413#define WM5100_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */ 2414#define WM5100_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */ 2415 2416/* 2417 * R1291 (0x50B) - Audio IF 1_12 2418 */ 2419#define WM5100_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */ 2420#define WM5100_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */ 2421#define WM5100_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */ 2422 2423/* 2424 * R1292 (0x50C) - Audio IF 1_13 2425 */ 2426#define WM5100_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */ 2427#define WM5100_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */ 2428#define WM5100_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */ 2429 2430/* 2431 * R1293 (0x50D) - Audio IF 1_14 2432 */ 2433#define WM5100_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */ 2434#define WM5100_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */ 2435#define WM5100_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */ 2436 2437/* 2438 * R1294 (0x50E) - Audio IF 1_15 2439 */ 2440#define WM5100_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */ 2441#define WM5100_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */ 2442#define WM5100_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */ 2443 2444/* 2445 * R1295 (0x50F) - Audio IF 1_16 2446 */ 2447#define WM5100_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */ 2448#define WM5100_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */ 2449#define WM5100_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */ 2450 2451/* 2452 * R1296 (0x510) - Audio IF 1_17 2453 */ 2454#define WM5100_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */ 2455#define WM5100_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */ 2456#define WM5100_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */ 2457 2458/* 2459 * R1297 (0x511) - Audio IF 1_18 2460 */ 2461#define WM5100_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */ 2462#define WM5100_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */ 2463#define WM5100_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */ 2464 2465/* 2466 * R1298 (0x512) - Audio IF 1_19 2467 */ 2468#define WM5100_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */ 2469#define WM5100_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */ 2470#define WM5100_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */ 2471 2472/* 2473 * R1299 (0x513) - Audio IF 1_20 2474 */ 2475#define WM5100_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */ 2476#define WM5100_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */ 2477#define WM5100_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */ 2478 2479/* 2480 * R1300 (0x514) - Audio IF 1_21 2481 */ 2482#define WM5100_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */ 2483#define WM5100_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */ 2484#define WM5100_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */ 2485 2486/* 2487 * R1301 (0x515) - Audio IF 1_22 2488 */ 2489#define WM5100_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */ 2490#define WM5100_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */ 2491#define WM5100_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */ 2492 2493/* 2494 * R1302 (0x516) - Audio IF 1_23 2495 */ 2496#define WM5100_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */ 2497#define WM5100_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */ 2498#define WM5100_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */ 2499 2500/* 2501 * R1303 (0x517) - Audio IF 1_24 2502 */ 2503#define WM5100_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */ 2504#define WM5100_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */ 2505#define WM5100_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */ 2506 2507/* 2508 * R1304 (0x518) - Audio IF 1_25 2509 */ 2510#define WM5100_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */ 2511#define WM5100_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */ 2512#define WM5100_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */ 2513 2514/* 2515 * R1305 (0x519) - Audio IF 1_26 2516 */ 2517#define WM5100_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */ 2518#define WM5100_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */ 2519#define WM5100_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */ 2520#define WM5100_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */ 2521#define WM5100_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */ 2522#define WM5100_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */ 2523#define WM5100_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */ 2524#define WM5100_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */ 2525#define WM5100_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */ 2526#define WM5100_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */ 2527#define WM5100_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */ 2528#define WM5100_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */ 2529#define WM5100_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */ 2530#define WM5100_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */ 2531#define WM5100_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */ 2532#define WM5100_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */ 2533#define WM5100_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */ 2534#define WM5100_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */ 2535#define WM5100_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */ 2536#define WM5100_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */ 2537#define WM5100_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */ 2538#define WM5100_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */ 2539#define WM5100_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */ 2540#define WM5100_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */ 2541#define WM5100_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */ 2542#define WM5100_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */ 2543#define WM5100_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */ 2544#define WM5100_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */ 2545#define WM5100_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */ 2546#define WM5100_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */ 2547#define WM5100_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */ 2548#define WM5100_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */ 2549 2550/* 2551 * R1306 (0x51A) - Audio IF 1_27 2552 */ 2553#define WM5100_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */ 2554#define WM5100_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */ 2555#define WM5100_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */ 2556#define WM5100_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */ 2557#define WM5100_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */ 2558#define WM5100_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */ 2559#define WM5100_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */ 2560#define WM5100_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */ 2561#define WM5100_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */ 2562#define WM5100_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */ 2563#define WM5100_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */ 2564#define WM5100_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */ 2565#define WM5100_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */ 2566#define WM5100_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */ 2567#define WM5100_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */ 2568#define WM5100_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */ 2569#define WM5100_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */ 2570#define WM5100_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */ 2571#define WM5100_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */ 2572#define WM5100_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */ 2573#define WM5100_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */ 2574#define WM5100_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */ 2575#define WM5100_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */ 2576#define WM5100_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */ 2577#define WM5100_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */ 2578#define WM5100_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */ 2579#define WM5100_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */ 2580#define WM5100_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */ 2581#define WM5100_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */ 2582#define WM5100_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */ 2583#define WM5100_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */ 2584#define WM5100_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */ 2585 2586/* 2587 * R1344 (0x540) - Audio IF 2_1 2588 */ 2589#define WM5100_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */ 2590#define WM5100_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */ 2591#define WM5100_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */ 2592#define WM5100_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */ 2593#define WM5100_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */ 2594#define WM5100_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */ 2595#define WM5100_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */ 2596#define WM5100_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */ 2597#define WM5100_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */ 2598#define WM5100_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */ 2599#define WM5100_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */ 2600#define WM5100_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */ 2601#define WM5100_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */ 2602#define WM5100_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */ 2603#define WM5100_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */ 2604 2605/* 2606 * R1345 (0x541) - Audio IF 2_2 2607 */ 2608#define WM5100_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */ 2609#define WM5100_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */ 2610#define WM5100_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */ 2611#define WM5100_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */ 2612#define WM5100_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */ 2613#define WM5100_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */ 2614#define WM5100_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */ 2615#define WM5100_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */ 2616#define WM5100_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */ 2617#define WM5100_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */ 2618#define WM5100_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */ 2619#define WM5100_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */ 2620#define WM5100_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */ 2621#define WM5100_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */ 2622#define WM5100_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */ 2623#define WM5100_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */ 2624#define WM5100_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */ 2625#define WM5100_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */ 2626#define WM5100_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */ 2627#define WM5100_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */ 2628 2629/* 2630 * R1346 (0x542) - Audio IF 2_3 2631 */ 2632#define WM5100_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */ 2633#define WM5100_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */ 2634#define WM5100_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */ 2635#define WM5100_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */ 2636#define WM5100_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */ 2637#define WM5100_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */ 2638#define WM5100_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */ 2639#define WM5100_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */ 2640#define WM5100_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */ 2641#define WM5100_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */ 2642#define WM5100_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */ 2643#define WM5100_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */ 2644 2645/* 2646 * R1347 (0x543) - Audio IF 2_4 2647 */ 2648#define WM5100_AIF2_TRI 0x0040 /* AIF2_TRI */ 2649#define WM5100_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */ 2650#define WM5100_AIF2_TRI_SHIFT 6 /* AIF2_TRI */ 2651#define WM5100_AIF2_TRI_WIDTH 1 /* AIF2_TRI */ 2652#define WM5100_AIF2_RATE_MASK 0x0003 /* AIF2_RATE - [1:0] */ 2653#define WM5100_AIF2_RATE_SHIFT 0 /* AIF2_RATE - [1:0] */ 2654#define WM5100_AIF2_RATE_WIDTH 2 /* AIF2_RATE - [1:0] */ 2655 2656/* 2657 * R1348 (0x544) - Audio IF 2_5 2658 */ 2659#define WM5100_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */ 2660#define WM5100_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */ 2661#define WM5100_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */ 2662 2663/* 2664 * R1349 (0x545) - Audio IF 2_6 2665 */ 2666#define WM5100_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */ 2667#define WM5100_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */ 2668#define WM5100_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */ 2669 2670/* 2671 * R1350 (0x546) - Audio IF 2_7 2672 */ 2673#define WM5100_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */ 2674#define WM5100_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */ 2675#define WM5100_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */ 2676 2677/* 2678 * R1351 (0x547) - Audio IF 2_8 2679 */ 2680#define WM5100_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */ 2681#define WM5100_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */ 2682#define WM5100_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */ 2683#define WM5100_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */ 2684#define WM5100_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */ 2685#define WM5100_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */ 2686 2687/* 2688 * R1352 (0x548) - Audio IF 2_9 2689 */ 2690#define WM5100_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */ 2691#define WM5100_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */ 2692#define WM5100_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */ 2693#define WM5100_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */ 2694#define WM5100_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */ 2695#define WM5100_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */ 2696 2697/* 2698 * R1353 (0x549) - Audio IF 2_10 2699 */ 2700#define WM5100_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */ 2701#define WM5100_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */ 2702#define WM5100_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */ 2703 2704/* 2705 * R1354 (0x54A) - Audio IF 2_11 2706 */ 2707#define WM5100_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */ 2708#define WM5100_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */ 2709#define WM5100_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */ 2710 2711/* 2712 * R1361 (0x551) - Audio IF 2_18 2713 */ 2714#define WM5100_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */ 2715#define WM5100_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */ 2716#define WM5100_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */ 2717 2718/* 2719 * R1362 (0x552) - Audio IF 2_19 2720 */ 2721#define WM5100_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */ 2722#define WM5100_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */ 2723#define WM5100_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */ 2724 2725/* 2726 * R1369 (0x559) - Audio IF 2_26 2727 */ 2728#define WM5100_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */ 2729#define WM5100_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */ 2730#define WM5100_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */ 2731#define WM5100_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */ 2732#define WM5100_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */ 2733#define WM5100_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */ 2734#define WM5100_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */ 2735#define WM5100_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */ 2736 2737/* 2738 * R1370 (0x55A) - Audio IF 2_27 2739 */ 2740#define WM5100_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */ 2741#define WM5100_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */ 2742#define WM5100_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */ 2743#define WM5100_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */ 2744#define WM5100_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */ 2745#define WM5100_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */ 2746#define WM5100_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */ 2747#define WM5100_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */ 2748 2749/* 2750 * R1408 (0x580) - Audio IF 3_1 2751 */ 2752#define WM5100_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */ 2753#define WM5100_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */ 2754#define WM5100_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */ 2755#define WM5100_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */ 2756#define WM5100_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */ 2757#define WM5100_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */ 2758#define WM5100_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */ 2759#define WM5100_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */ 2760#define WM5100_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */ 2761#define WM5100_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */ 2762#define WM5100_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */ 2763#define WM5100_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */ 2764#define WM5100_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */ 2765#define WM5100_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */ 2766#define WM5100_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */ 2767 2768/* 2769 * R1409 (0x581) - Audio IF 3_2 2770 */ 2771#define WM5100_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */ 2772#define WM5100_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */ 2773#define WM5100_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */ 2774#define WM5100_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */ 2775#define WM5100_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */ 2776#define WM5100_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */ 2777#define WM5100_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */ 2778#define WM5100_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */ 2779#define WM5100_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */ 2780#define WM5100_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */ 2781#define WM5100_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */ 2782#define WM5100_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */ 2783#define WM5100_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */ 2784#define WM5100_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */ 2785#define WM5100_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */ 2786#define WM5100_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */ 2787#define WM5100_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */ 2788#define WM5100_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */ 2789#define WM5100_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */ 2790#define WM5100_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */ 2791 2792/* 2793 * R1410 (0x582) - Audio IF 3_3 2794 */ 2795#define WM5100_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */ 2796#define WM5100_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */ 2797#define WM5100_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */ 2798#define WM5100_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */ 2799#define WM5100_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */ 2800#define WM5100_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */ 2801#define WM5100_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */ 2802#define WM5100_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */ 2803#define WM5100_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */ 2804#define WM5100_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */ 2805#define WM5100_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */ 2806#define WM5100_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */ 2807 2808/* 2809 * R1411 (0x583) - Audio IF 3_4 2810 */ 2811#define WM5100_AIF3_TRI 0x0040 /* AIF3_TRI */ 2812#define WM5100_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */ 2813#define WM5100_AIF3_TRI_SHIFT 6 /* AIF3_TRI */ 2814#define WM5100_AIF3_TRI_WIDTH 1 /* AIF3_TRI */ 2815#define WM5100_AIF3_RATE_MASK 0x0003 /* AIF3_RATE - [1:0] */ 2816#define WM5100_AIF3_RATE_SHIFT 0 /* AIF3_RATE - [1:0] */ 2817#define WM5100_AIF3_RATE_WIDTH 2 /* AIF3_RATE - [1:0] */ 2818 2819/* 2820 * R1412 (0x584) - Audio IF 3_5 2821 */ 2822#define WM5100_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */ 2823#define WM5100_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */ 2824#define WM5100_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */ 2825 2826/* 2827 * R1413 (0x585) - Audio IF 3_6 2828 */ 2829#define WM5100_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */ 2830#define WM5100_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */ 2831#define WM5100_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */ 2832 2833/* 2834 * R1414 (0x586) - Audio IF 3_7 2835 */ 2836#define WM5100_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */ 2837#define WM5100_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */ 2838#define WM5100_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */ 2839 2840/* 2841 * R1415 (0x587) - Audio IF 3_8 2842 */ 2843#define WM5100_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */ 2844#define WM5100_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */ 2845#define WM5100_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */ 2846#define WM5100_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */ 2847#define WM5100_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */ 2848#define WM5100_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */ 2849 2850/* 2851 * R1416 (0x588) - Audio IF 3_9 2852 */ 2853#define WM5100_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */ 2854#define WM5100_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */ 2855#define WM5100_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */ 2856#define WM5100_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */ 2857#define WM5100_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */ 2858#define WM5100_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */ 2859 2860/* 2861 * R1417 (0x589) - Audio IF 3_10 2862 */ 2863#define WM5100_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */ 2864#define WM5100_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */ 2865#define WM5100_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */ 2866 2867/* 2868 * R1418 (0x58A) - Audio IF 3_11 2869 */ 2870#define WM5100_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */ 2871#define WM5100_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */ 2872#define WM5100_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */ 2873 2874/* 2875 * R1425 (0x591) - Audio IF 3_18 2876 */ 2877#define WM5100_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */ 2878#define WM5100_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */ 2879#define WM5100_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */ 2880 2881/* 2882 * R1426 (0x592) - Audio IF 3_19 2883 */ 2884#define WM5100_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */ 2885#define WM5100_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */ 2886#define WM5100_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */ 2887 2888/* 2889 * R1433 (0x599) - Audio IF 3_26 2890 */ 2891#define WM5100_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */ 2892#define WM5100_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */ 2893#define WM5100_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */ 2894#define WM5100_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */ 2895#define WM5100_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */ 2896#define WM5100_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */ 2897#define WM5100_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */ 2898#define WM5100_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */ 2899 2900/* 2901 * R1434 (0x59A) - Audio IF 3_27 2902 */ 2903#define WM5100_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */ 2904#define WM5100_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */ 2905#define WM5100_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */ 2906#define WM5100_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */ 2907#define WM5100_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */ 2908#define WM5100_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */ 2909#define WM5100_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */ 2910#define WM5100_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */ 2911 2912#define WM5100_MIXER_VOL_MASK 0x00FE /* MIXER_VOL - [7:1] */ 2913#define WM5100_MIXER_VOL_SHIFT 1 /* MIXER_VOL - [7:1] */ 2914#define WM5100_MIXER_VOL_WIDTH 7 /* MIXER_VOL - [7:1] */ 2915 2916/* 2917 * R3072 (0xC00) - GPIO CTRL 1 2918 */ 2919#define WM5100_GP1_DIR 0x8000 /* GP1_DIR */ 2920#define WM5100_GP1_DIR_MASK 0x8000 /* GP1_DIR */ 2921#define WM5100_GP1_DIR_SHIFT 15 /* GP1_DIR */ 2922#define WM5100_GP1_DIR_WIDTH 1 /* GP1_DIR */ 2923#define WM5100_GP1_PU 0x4000 /* GP1_PU */ 2924#define WM5100_GP1_PU_MASK 0x4000 /* GP1_PU */ 2925#define WM5100_GP1_PU_SHIFT 14 /* GP1_PU */ 2926#define WM5100_GP1_PU_WIDTH 1 /* GP1_PU */ 2927#define WM5100_GP1_PD 0x2000 /* GP1_PD */ 2928#define WM5100_GP1_PD_MASK 0x2000 /* GP1_PD */ 2929#define WM5100_GP1_PD_SHIFT 13 /* GP1_PD */ 2930#define WM5100_GP1_PD_WIDTH 1 /* GP1_PD */ 2931#define WM5100_GP1_POL 0x0400 /* GP1_POL */ 2932#define WM5100_GP1_POL_MASK 0x0400 /* GP1_POL */ 2933#define WM5100_GP1_POL_SHIFT 10 /* GP1_POL */ 2934#define WM5100_GP1_POL_WIDTH 1 /* GP1_POL */ 2935#define WM5100_GP1_OP_CFG 0x0200 /* GP1_OP_CFG */ 2936#define WM5100_GP1_OP_CFG_MASK 0x0200 /* GP1_OP_CFG */ 2937#define WM5100_GP1_OP_CFG_SHIFT 9 /* GP1_OP_CFG */ 2938#define WM5100_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 2939#define WM5100_GP1_DB 0x0100 /* GP1_DB */ 2940#define WM5100_GP1_DB_MASK 0x0100 /* GP1_DB */ 2941#define WM5100_GP1_DB_SHIFT 8 /* GP1_DB */ 2942#define WM5100_GP1_DB_WIDTH 1 /* GP1_DB */ 2943#define WM5100_GP1_LVL 0x0040 /* GP1_LVL */ 2944#define WM5100_GP1_LVL_MASK 0x0040 /* GP1_LVL */ 2945#define WM5100_GP1_LVL_SHIFT 6 /* GP1_LVL */ 2946#define WM5100_GP1_LVL_WIDTH 1 /* GP1_LVL */ 2947#define WM5100_GP1_FN_MASK 0x003F /* GP1_FN - [5:0] */ 2948#define WM5100_GP1_FN_SHIFT 0 /* GP1_FN - [5:0] */ 2949#define WM5100_GP1_FN_WIDTH 6 /* GP1_FN - [5:0] */ 2950 2951/* 2952 * R3073 (0xC01) - GPIO CTRL 2 2953 */ 2954#define WM5100_GP2_DIR 0x8000 /* GP2_DIR */ 2955#define WM5100_GP2_DIR_MASK 0x8000 /* GP2_DIR */ 2956#define WM5100_GP2_DIR_SHIFT 15 /* GP2_DIR */ 2957#define WM5100_GP2_DIR_WIDTH 1 /* GP2_DIR */ 2958#define WM5100_GP2_PU 0x4000 /* GP2_PU */ 2959#define WM5100_GP2_PU_MASK 0x4000 /* GP2_PU */ 2960#define WM5100_GP2_PU_SHIFT 14 /* GP2_PU */ 2961#define WM5100_GP2_PU_WIDTH 1 /* GP2_PU */ 2962#define WM5100_GP2_PD 0x2000 /* GP2_PD */ 2963#define WM5100_GP2_PD_MASK 0x2000 /* GP2_PD */ 2964#define WM5100_GP2_PD_SHIFT 13 /* GP2_PD */ 2965#define WM5100_GP2_PD_WIDTH 1 /* GP2_PD */ 2966#define WM5100_GP2_POL 0x0400 /* GP2_POL */ 2967#define WM5100_GP2_POL_MASK 0x0400 /* GP2_POL */ 2968#define WM5100_GP2_POL_SHIFT 10 /* GP2_POL */ 2969#define WM5100_GP2_POL_WIDTH 1 /* GP2_POL */ 2970#define WM5100_GP2_OP_CFG 0x0200 /* GP2_OP_CFG */ 2971#define WM5100_GP2_OP_CFG_MASK 0x0200 /* GP2_OP_CFG */ 2972#define WM5100_GP2_OP_CFG_SHIFT 9 /* GP2_OP_CFG */ 2973#define WM5100_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 2974#define WM5100_GP2_DB 0x0100 /* GP2_DB */ 2975#define WM5100_GP2_DB_MASK 0x0100 /* GP2_DB */ 2976#define WM5100_GP2_DB_SHIFT 8 /* GP2_DB */ 2977#define WM5100_GP2_DB_WIDTH 1 /* GP2_DB */ 2978#define WM5100_GP2_LVL 0x0040 /* GP2_LVL */ 2979#define WM5100_GP2_LVL_MASK 0x0040 /* GP2_LVL */ 2980#define WM5100_GP2_LVL_SHIFT 6 /* GP2_LVL */ 2981#define WM5100_GP2_LVL_WIDTH 1 /* GP2_LVL */ 2982#define WM5100_GP2_FN_MASK 0x003F /* GP2_FN - [5:0] */ 2983#define WM5100_GP2_FN_SHIFT 0 /* GP2_FN - [5:0] */ 2984#define WM5100_GP2_FN_WIDTH 6 /* GP2_FN - [5:0] */ 2985 2986/* 2987 * R3074 (0xC02) - GPIO CTRL 3 2988 */ 2989#define WM5100_GP3_DIR 0x8000 /* GP3_DIR */ 2990#define WM5100_GP3_DIR_MASK 0x8000 /* GP3_DIR */ 2991#define WM5100_GP3_DIR_SHIFT 15 /* GP3_DIR */ 2992#define WM5100_GP3_DIR_WIDTH 1 /* GP3_DIR */ 2993#define WM5100_GP3_PU 0x4000 /* GP3_PU */ 2994#define WM5100_GP3_PU_MASK 0x4000 /* GP3_PU */ 2995#define WM5100_GP3_PU_SHIFT 14 /* GP3_PU */ 2996#define WM5100_GP3_PU_WIDTH 1 /* GP3_PU */ 2997#define WM5100_GP3_PD 0x2000 /* GP3_PD */ 2998#define WM5100_GP3_PD_MASK 0x2000 /* GP3_PD */ 2999#define WM5100_GP3_PD_SHIFT 13 /* GP3_PD */ 3000#define WM5100_GP3_PD_WIDTH 1 /* GP3_PD */ 3001#define WM5100_GP3_POL 0x0400 /* GP3_POL */ 3002#define WM5100_GP3_POL_MASK 0x0400 /* GP3_POL */ 3003#define WM5100_GP3_POL_SHIFT 10 /* GP3_POL */ 3004#define WM5100_GP3_POL_WIDTH 1 /* GP3_POL */ 3005#define WM5100_GP3_OP_CFG 0x0200 /* GP3_OP_CFG */ 3006#define WM5100_GP3_OP_CFG_MASK 0x0200 /* GP3_OP_CFG */ 3007#define WM5100_GP3_OP_CFG_SHIFT 9 /* GP3_OP_CFG */ 3008#define WM5100_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 3009#define WM5100_GP3_DB 0x0100 /* GP3_DB */ 3010#define WM5100_GP3_DB_MASK 0x0100 /* GP3_DB */ 3011#define WM5100_GP3_DB_SHIFT 8 /* GP3_DB */ 3012#define WM5100_GP3_DB_WIDTH 1 /* GP3_DB */ 3013#define WM5100_GP3_LVL 0x0040 /* GP3_LVL */ 3014#define WM5100_GP3_LVL_MASK 0x0040 /* GP3_LVL */ 3015#define WM5100_GP3_LVL_SHIFT 6 /* GP3_LVL */ 3016#define WM5100_GP3_LVL_WIDTH 1 /* GP3_LVL */ 3017#define WM5100_GP3_FN_MASK 0x003F /* GP3_FN - [5:0] */ 3018#define WM5100_GP3_FN_SHIFT 0 /* GP3_FN - [5:0] */ 3019#define WM5100_GP3_FN_WIDTH 6 /* GP3_FN - [5:0] */ 3020 3021/* 3022 * R3075 (0xC03) - GPIO CTRL 4 3023 */ 3024#define WM5100_GP4_DIR 0x8000 /* GP4_DIR */ 3025#define WM5100_GP4_DIR_MASK 0x8000 /* GP4_DIR */ 3026#define WM5100_GP4_DIR_SHIFT 15 /* GP4_DIR */ 3027#define WM5100_GP4_DIR_WIDTH 1 /* GP4_DIR */ 3028#define WM5100_GP4_PU 0x4000 /* GP4_PU */ 3029#define WM5100_GP4_PU_MASK 0x4000 /* GP4_PU */ 3030#define WM5100_GP4_PU_SHIFT 14 /* GP4_PU */ 3031#define WM5100_GP4_PU_WIDTH 1 /* GP4_PU */ 3032#define WM5100_GP4_PD 0x2000 /* GP4_PD */ 3033#define WM5100_GP4_PD_MASK 0x2000 /* GP4_PD */ 3034#define WM5100_GP4_PD_SHIFT 13 /* GP4_PD */ 3035#define WM5100_GP4_PD_WIDTH 1 /* GP4_PD */ 3036#define WM5100_GP4_POL 0x0400 /* GP4_POL */ 3037#define WM5100_GP4_POL_MASK 0x0400 /* GP4_POL */ 3038#define WM5100_GP4_POL_SHIFT 10 /* GP4_POL */ 3039#define WM5100_GP4_POL_WIDTH 1 /* GP4_POL */ 3040#define WM5100_GP4_OP_CFG 0x0200 /* GP4_OP_CFG */ 3041#define WM5100_GP4_OP_CFG_MASK 0x0200 /* GP4_OP_CFG */ 3042#define WM5100_GP4_OP_CFG_SHIFT 9 /* GP4_OP_CFG */ 3043#define WM5100_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 3044#define WM5100_GP4_DB 0x0100 /* GP4_DB */ 3045#define WM5100_GP4_DB_MASK 0x0100 /* GP4_DB */ 3046#define WM5100_GP4_DB_SHIFT 8 /* GP4_DB */ 3047#define WM5100_GP4_DB_WIDTH 1 /* GP4_DB */ 3048#define WM5100_GP4_LVL 0x0040 /* GP4_LVL */ 3049#define WM5100_GP4_LVL_MASK 0x0040 /* GP4_LVL */ 3050#define WM5100_GP4_LVL_SHIFT 6 /* GP4_LVL */ 3051#define WM5100_GP4_LVL_WIDTH 1 /* GP4_LVL */ 3052#define WM5100_GP4_FN_MASK 0x003F /* GP4_FN - [5:0] */ 3053#define WM5100_GP4_FN_SHIFT 0 /* GP4_FN - [5:0] */ 3054#define WM5100_GP4_FN_WIDTH 6 /* GP4_FN - [5:0] */ 3055 3056/* 3057 * R3076 (0xC04) - GPIO CTRL 5 3058 */ 3059#define WM5100_GP5_DIR 0x8000 /* GP5_DIR */ 3060#define WM5100_GP5_DIR_MASK 0x8000 /* GP5_DIR */ 3061#define WM5100_GP5_DIR_SHIFT 15 /* GP5_DIR */ 3062#define WM5100_GP5_DIR_WIDTH 1 /* GP5_DIR */ 3063#define WM5100_GP5_PU 0x4000 /* GP5_PU */ 3064#define WM5100_GP5_PU_MASK 0x4000 /* GP5_PU */ 3065#define WM5100_GP5_PU_SHIFT 14 /* GP5_PU */ 3066#define WM5100_GP5_PU_WIDTH 1 /* GP5_PU */ 3067#define WM5100_GP5_PD 0x2000 /* GP5_PD */ 3068#define WM5100_GP5_PD_MASK 0x2000 /* GP5_PD */ 3069#define WM5100_GP5_PD_SHIFT 13 /* GP5_PD */ 3070#define WM5100_GP5_PD_WIDTH 1 /* GP5_PD */ 3071#define WM5100_GP5_POL 0x0400 /* GP5_POL */ 3072#define WM5100_GP5_POL_MASK 0x0400 /* GP5_POL */ 3073#define WM5100_GP5_POL_SHIFT 10 /* GP5_POL */ 3074#define WM5100_GP5_POL_WIDTH 1 /* GP5_POL */ 3075#define WM5100_GP5_OP_CFG 0x0200 /* GP5_OP_CFG */ 3076#define WM5100_GP5_OP_CFG_MASK 0x0200 /* GP5_OP_CFG */ 3077#define WM5100_GP5_OP_CFG_SHIFT 9 /* GP5_OP_CFG */ 3078#define WM5100_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 3079#define WM5100_GP5_DB 0x0100 /* GP5_DB */ 3080#define WM5100_GP5_DB_MASK 0x0100 /* GP5_DB */ 3081#define WM5100_GP5_DB_SHIFT 8 /* GP5_DB */ 3082#define WM5100_GP5_DB_WIDTH 1 /* GP5_DB */ 3083#define WM5100_GP5_LVL 0x0040 /* GP5_LVL */ 3084#define WM5100_GP5_LVL_MASK 0x0040 /* GP5_LVL */ 3085#define WM5100_GP5_LVL_SHIFT 6 /* GP5_LVL */ 3086#define WM5100_GP5_LVL_WIDTH 1 /* GP5_LVL */ 3087#define WM5100_GP5_FN_MASK 0x003F /* GP5_FN - [5:0] */ 3088#define WM5100_GP5_FN_SHIFT 0 /* GP5_FN - [5:0] */ 3089#define WM5100_GP5_FN_WIDTH 6 /* GP5_FN - [5:0] */ 3090 3091/* 3092 * R3077 (0xC05) - GPIO CTRL 6 3093 */ 3094#define WM5100_GP6_DIR 0x8000 /* GP6_DIR */ 3095#define WM5100_GP6_DIR_MASK 0x8000 /* GP6_DIR */ 3096#define WM5100_GP6_DIR_SHIFT 15 /* GP6_DIR */ 3097#define WM5100_GP6_DIR_WIDTH 1 /* GP6_DIR */ 3098#define WM5100_GP6_PU 0x4000 /* GP6_PU */ 3099#define WM5100_GP6_PU_MASK 0x4000 /* GP6_PU */ 3100#define WM5100_GP6_PU_SHIFT 14 /* GP6_PU */ 3101#define WM5100_GP6_PU_WIDTH 1 /* GP6_PU */ 3102#define WM5100_GP6_PD 0x2000 /* GP6_PD */ 3103#define WM5100_GP6_PD_MASK 0x2000 /* GP6_PD */ 3104#define WM5100_GP6_PD_SHIFT 13 /* GP6_PD */ 3105#define WM5100_GP6_PD_WIDTH 1 /* GP6_PD */ 3106#define WM5100_GP6_POL 0x0400 /* GP6_POL */ 3107#define WM5100_GP6_POL_MASK 0x0400 /* GP6_POL */ 3108#define WM5100_GP6_POL_SHIFT 10 /* GP6_POL */ 3109#define WM5100_GP6_POL_WIDTH 1 /* GP6_POL */ 3110#define WM5100_GP6_OP_CFG 0x0200 /* GP6_OP_CFG */ 3111#define WM5100_GP6_OP_CFG_MASK 0x0200 /* GP6_OP_CFG */ 3112#define WM5100_GP6_OP_CFG_SHIFT 9 /* GP6_OP_CFG */ 3113#define WM5100_GP6_OP_CFG_WIDTH 1 /* GP6_OP_CFG */ 3114#define WM5100_GP6_DB 0x0100 /* GP6_DB */ 3115#define WM5100_GP6_DB_MASK 0x0100 /* GP6_DB */ 3116#define WM5100_GP6_DB_SHIFT 8 /* GP6_DB */ 3117#define WM5100_GP6_DB_WIDTH 1 /* GP6_DB */ 3118#define WM5100_GP6_LVL 0x0040 /* GP6_LVL */ 3119#define WM5100_GP6_LVL_MASK 0x0040 /* GP6_LVL */ 3120#define WM5100_GP6_LVL_SHIFT 6 /* GP6_LVL */ 3121#define WM5100_GP6_LVL_WIDTH 1 /* GP6_LVL */ 3122#define WM5100_GP6_FN_MASK 0x003F /* GP6_FN - [5:0] */ 3123#define WM5100_GP6_FN_SHIFT 0 /* GP6_FN - [5:0] */ 3124#define WM5100_GP6_FN_WIDTH 6 /* GP6_FN - [5:0] */ 3125 3126/* 3127 * R3107 (0xC23) - Misc Pad Ctrl 1 3128 */ 3129#define WM5100_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */ 3130#define WM5100_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */ 3131#define WM5100_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */ 3132#define WM5100_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */ 3133#define WM5100_MCLK2_PD 0x2000 /* MCLK2_PD */ 3134#define WM5100_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */ 3135#define WM5100_MCLK2_PD_SHIFT 13 /* MCLK2_PD */ 3136#define WM5100_MCLK2_PD_WIDTH 1 /* MCLK2_PD */ 3137#define WM5100_MCLK1_PD 0x1000 /* MCLK1_PD */ 3138#define WM5100_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */ 3139#define WM5100_MCLK1_PD_SHIFT 12 /* MCLK1_PD */ 3140#define WM5100_MCLK1_PD_WIDTH 1 /* MCLK1_PD */ 3141#define WM5100_RESET_PU 0x0002 /* RESET_PU */ 3142#define WM5100_RESET_PU_MASK 0x0002 /* RESET_PU */ 3143#define WM5100_RESET_PU_SHIFT 1 /* RESET_PU */ 3144#define WM5100_RESET_PU_WIDTH 1 /* RESET_PU */ 3145#define WM5100_ADDR_PD 0x0001 /* ADDR_PD */ 3146#define WM5100_ADDR_PD_MASK 0x0001 /* ADDR_PD */ 3147#define WM5100_ADDR_PD_SHIFT 0 /* ADDR_PD */ 3148#define WM5100_ADDR_PD_WIDTH 1 /* ADDR_PD */ 3149 3150/* 3151 * R3108 (0xC24) - Misc Pad Ctrl 2 3152 */ 3153#define WM5100_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */ 3154#define WM5100_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */ 3155#define WM5100_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */ 3156#define WM5100_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */ 3157#define WM5100_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */ 3158#define WM5100_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */ 3159#define WM5100_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */ 3160#define WM5100_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */ 3161#define WM5100_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */ 3162#define WM5100_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */ 3163#define WM5100_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */ 3164#define WM5100_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */ 3165#define WM5100_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */ 3166#define WM5100_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */ 3167#define WM5100_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */ 3168#define WM5100_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */ 3169 3170/* 3171 * R3109 (0xC25) - Misc Pad Ctrl 3 3172 */ 3173#define WM5100_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */ 3174#define WM5100_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */ 3175#define WM5100_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */ 3176#define WM5100_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */ 3177#define WM5100_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */ 3178#define WM5100_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */ 3179#define WM5100_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */ 3180#define WM5100_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */ 3181#define WM5100_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */ 3182#define WM5100_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */ 3183#define WM5100_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */ 3184#define WM5100_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */ 3185#define WM5100_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */ 3186#define WM5100_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */ 3187#define WM5100_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */ 3188#define WM5100_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */ 3189#define WM5100_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */ 3190#define WM5100_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */ 3191#define WM5100_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */ 3192#define WM5100_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */ 3193#define WM5100_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */ 3194#define WM5100_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */ 3195#define WM5100_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */ 3196#define WM5100_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */ 3197 3198/* 3199 * R3110 (0xC26) - Misc Pad Ctrl 4 3200 */ 3201#define WM5100_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */ 3202#define WM5100_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */ 3203#define WM5100_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */ 3204#define WM5100_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */ 3205#define WM5100_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */ 3206#define WM5100_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */ 3207#define WM5100_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */ 3208#define WM5100_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */ 3209#define WM5100_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */ 3210#define WM5100_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */ 3211#define WM5100_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */ 3212#define WM5100_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */ 3213#define WM5100_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */ 3214#define WM5100_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */ 3215#define WM5100_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */ 3216#define WM5100_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */ 3217#define WM5100_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */ 3218#define WM5100_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */ 3219#define WM5100_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */ 3220#define WM5100_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */ 3221#define WM5100_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */ 3222#define WM5100_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */ 3223#define WM5100_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */ 3224#define WM5100_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */ 3225 3226/* 3227 * R3111 (0xC27) - Misc Pad Ctrl 5 3228 */ 3229#define WM5100_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */ 3230#define WM5100_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */ 3231#define WM5100_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */ 3232#define WM5100_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */ 3233#define WM5100_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */ 3234#define WM5100_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */ 3235#define WM5100_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */ 3236#define WM5100_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */ 3237#define WM5100_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */ 3238#define WM5100_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */ 3239#define WM5100_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */ 3240#define WM5100_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */ 3241#define WM5100_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */ 3242#define WM5100_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */ 3243#define WM5100_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */ 3244#define WM5100_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */ 3245#define WM5100_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */ 3246#define WM5100_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */ 3247#define WM5100_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */ 3248#define WM5100_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */ 3249#define WM5100_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */ 3250#define WM5100_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */ 3251#define WM5100_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */ 3252#define WM5100_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */ 3253 3254/* 3255 * R3112 (0xC28) - Misc GPIO 1 3256 */ 3257#define WM5100_OPCLK_SEL_MASK 0x0003 /* OPCLK_SEL - [1:0] */ 3258#define WM5100_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [1:0] */ 3259#define WM5100_OPCLK_SEL_WIDTH 2 /* OPCLK_SEL - [1:0] */ 3260 3261/* 3262 * R3328 (0xD00) - Interrupt Status 1 3263 */ 3264#define WM5100_GP6_EINT 0x0020 /* GP6_EINT */ 3265#define WM5100_GP6_EINT_MASK 0x0020 /* GP6_EINT */ 3266#define WM5100_GP6_EINT_SHIFT 5 /* GP6_EINT */ 3267#define WM5100_GP6_EINT_WIDTH 1 /* GP6_EINT */ 3268#define WM5100_GP5_EINT 0x0010 /* GP5_EINT */ 3269#define WM5100_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 3270#define WM5100_GP5_EINT_SHIFT 4 /* GP5_EINT */ 3271#define WM5100_GP5_EINT_WIDTH 1 /* GP5_EINT */ 3272#define WM5100_GP4_EINT 0x0008 /* GP4_EINT */ 3273#define WM5100_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 3274#define WM5100_GP4_EINT_SHIFT 3 /* GP4_EINT */ 3275#define WM5100_GP4_EINT_WIDTH 1 /* GP4_EINT */ 3276#define WM5100_GP3_EINT 0x0004 /* GP3_EINT */ 3277#define WM5100_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 3278#define WM5100_GP3_EINT_SHIFT 2 /* GP3_EINT */ 3279#define WM5100_GP3_EINT_WIDTH 1 /* GP3_EINT */ 3280#define WM5100_GP2_EINT 0x0002 /* GP2_EINT */ 3281#define WM5100_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 3282#define WM5100_GP2_EINT_SHIFT 1 /* GP2_EINT */ 3283#define WM5100_GP2_EINT_WIDTH 1 /* GP2_EINT */ 3284#define WM5100_GP1_EINT 0x0001 /* GP1_EINT */ 3285#define WM5100_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 3286#define WM5100_GP1_EINT_SHIFT 0 /* GP1_EINT */ 3287#define WM5100_GP1_EINT_WIDTH 1 /* GP1_EINT */ 3288 3289/* 3290 * R3329 (0xD01) - Interrupt Status 2 3291 */ 3292#define WM5100_DSP_IRQ6_EINT 0x0020 /* DSP_IRQ6_EINT */ 3293#define WM5100_DSP_IRQ6_EINT_MASK 0x0020 /* DSP_IRQ6_EINT */ 3294#define WM5100_DSP_IRQ6_EINT_SHIFT 5 /* DSP_IRQ6_EINT */ 3295#define WM5100_DSP_IRQ6_EINT_WIDTH 1 /* DSP_IRQ6_EINT */ 3296#define WM5100_DSP_IRQ5_EINT 0x0010 /* DSP_IRQ5_EINT */ 3297#define WM5100_DSP_IRQ5_EINT_MASK 0x0010 /* DSP_IRQ5_EINT */ 3298#define WM5100_DSP_IRQ5_EINT_SHIFT 4 /* DSP_IRQ5_EINT */ 3299#define WM5100_DSP_IRQ5_EINT_WIDTH 1 /* DSP_IRQ5_EINT */ 3300#define WM5100_DSP_IRQ4_EINT 0x0008 /* DSP_IRQ4_EINT */ 3301#define WM5100_DSP_IRQ4_EINT_MASK 0x0008 /* DSP_IRQ4_EINT */ 3302#define WM5100_DSP_IRQ4_EINT_SHIFT 3 /* DSP_IRQ4_EINT */ 3303#define WM5100_DSP_IRQ4_EINT_WIDTH 1 /* DSP_IRQ4_EINT */ 3304#define WM5100_DSP_IRQ3_EINT 0x0004 /* DSP_IRQ3_EINT */ 3305#define WM5100_DSP_IRQ3_EINT_MASK 0x0004 /* DSP_IRQ3_EINT */ 3306#define WM5100_DSP_IRQ3_EINT_SHIFT 2 /* DSP_IRQ3_EINT */ 3307#define WM5100_DSP_IRQ3_EINT_WIDTH 1 /* DSP_IRQ3_EINT */ 3308#define WM5100_DSP_IRQ2_EINT 0x0002 /* DSP_IRQ2_EINT */ 3309#define WM5100_DSP_IRQ2_EINT_MASK 0x0002 /* DSP_IRQ2_EINT */ 3310#define WM5100_DSP_IRQ2_EINT_SHIFT 1 /* DSP_IRQ2_EINT */ 3311#define WM5100_DSP_IRQ2_EINT_WIDTH 1 /* DSP_IRQ2_EINT */ 3312#define WM5100_DSP_IRQ1_EINT 0x0001 /* DSP_IRQ1_EINT */ 3313#define WM5100_DSP_IRQ1_EINT_MASK 0x0001 /* DSP_IRQ1_EINT */ 3314#define WM5100_DSP_IRQ1_EINT_SHIFT 0 /* DSP_IRQ1_EINT */ 3315#define WM5100_DSP_IRQ1_EINT_WIDTH 1 /* DSP_IRQ1_EINT */ 3316 3317/* 3318 * R3330 (0xD02) - Interrupt Status 3 3319 */ 3320#define WM5100_SPK_SHUTDOWN_WARN_EINT 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3321#define WM5100_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT */ 3322#define WM5100_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT */ 3323#define WM5100_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT */ 3324#define WM5100_SPK_SHUTDOWN_EINT 0x4000 /* SPK_SHUTDOWN_EINT */ 3325#define WM5100_SPK_SHUTDOWN_EINT_MASK 0x4000 /* SPK_SHUTDOWN_EINT */ 3326#define WM5100_SPK_SHUTDOWN_EINT_SHIFT 14 /* SPK_SHUTDOWN_EINT */ 3327#define WM5100_SPK_SHUTDOWN_EINT_WIDTH 1 /* SPK_SHUTDOWN_EINT */ 3328#define WM5100_HPDET_EINT 0x2000 /* HPDET_EINT */ 3329#define WM5100_HPDET_EINT_MASK 0x2000 /* HPDET_EINT */ 3330#define WM5100_HPDET_EINT_SHIFT 13 /* HPDET_EINT */ 3331#define WM5100_HPDET_EINT_WIDTH 1 /* HPDET_EINT */ 3332#define WM5100_ACCDET_EINT 0x1000 /* ACCDET_EINT */ 3333#define WM5100_ACCDET_EINT_MASK 0x1000 /* ACCDET_EINT */ 3334#define WM5100_ACCDET_EINT_SHIFT 12 /* ACCDET_EINT */ 3335#define WM5100_ACCDET_EINT_WIDTH 1 /* ACCDET_EINT */ 3336#define WM5100_DRC_SIG_DET_EINT 0x0200 /* DRC_SIG_DET_EINT */ 3337#define WM5100_DRC_SIG_DET_EINT_MASK 0x0200 /* DRC_SIG_DET_EINT */ 3338#define WM5100_DRC_SIG_DET_EINT_SHIFT 9 /* DRC_SIG_DET_EINT */ 3339#define WM5100_DRC_SIG_DET_EINT_WIDTH 1 /* DRC_SIG_DET_EINT */ 3340#define WM5100_ASRC2_LOCK_EINT 0x0100 /* ASRC2_LOCK_EINT */ 3341#define WM5100_ASRC2_LOCK_EINT_MASK 0x0100 /* ASRC2_LOCK_EINT */ 3342#define WM5100_ASRC2_LOCK_EINT_SHIFT 8 /* ASRC2_LOCK_EINT */ 3343#define WM5100_ASRC2_LOCK_EINT_WIDTH 1 /* ASRC2_LOCK_EINT */ 3344#define WM5100_ASRC1_LOCK_EINT 0x0080 /* ASRC1_LOCK_EINT */ 3345#define WM5100_ASRC1_LOCK_EINT_MASK 0x0080 /* ASRC1_LOCK_EINT */ 3346#define WM5100_ASRC1_LOCK_EINT_SHIFT 7 /* ASRC1_LOCK_EINT */ 3347#define WM5100_ASRC1_LOCK_EINT_WIDTH 1 /* ASRC1_LOCK_EINT */ 3348#define WM5100_FLL2_LOCK_EINT 0x0008 /* FLL2_LOCK_EINT */ 3349#define WM5100_FLL2_LOCK_EINT_MASK 0x0008 /* FLL2_LOCK_EINT */ 3350#define WM5100_FLL2_LOCK_EINT_SHIFT 3 /* FLL2_LOCK_EINT */ 3351#define WM5100_FLL2_LOCK_EINT_WIDTH 1 /* FLL2_LOCK_EINT */ 3352#define WM5100_FLL1_LOCK_EINT 0x0004 /* FLL1_LOCK_EINT */ 3353#define WM5100_FLL1_LOCK_EINT_MASK 0x0004 /* FLL1_LOCK_EINT */ 3354#define WM5100_FLL1_LOCK_EINT_SHIFT 2 /* FLL1_LOCK_EINT */ 3355#define WM5100_FLL1_LOCK_EINT_WIDTH 1 /* FLL1_LOCK_EINT */ 3356#define WM5100_CLKGEN_ERR_EINT 0x0002 /* CLKGEN_ERR_EINT */ 3357#define WM5100_CLKGEN_ERR_EINT_MASK 0x0002 /* CLKGEN_ERR_EINT */ 3358#define WM5100_CLKGEN_ERR_EINT_SHIFT 1 /* CLKGEN_ERR_EINT */ 3359#define WM5100_CLKGEN_ERR_EINT_WIDTH 1 /* CLKGEN_ERR_EINT */ 3360#define WM5100_CLKGEN_ERR_ASYNC_EINT 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3361#define WM5100_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT */ 3362#define WM5100_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT */ 3363#define WM5100_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT */ 3364 3365/* 3366 * R3331 (0xD03) - Interrupt Status 4 3367 */ 3368#define WM5100_AIF3_ERR_EINT 0x2000 /* AIF3_ERR_EINT */ 3369#define WM5100_AIF3_ERR_EINT_MASK 0x2000 /* AIF3_ERR_EINT */ 3370#define WM5100_AIF3_ERR_EINT_SHIFT 13 /* AIF3_ERR_EINT */ 3371#define WM5100_AIF3_ERR_EINT_WIDTH 1 /* AIF3_ERR_EINT */ 3372#define WM5100_AIF2_ERR_EINT 0x1000 /* AIF2_ERR_EINT */ 3373#define WM5100_AIF2_ERR_EINT_MASK 0x1000 /* AIF2_ERR_EINT */ 3374#define WM5100_AIF2_ERR_EINT_SHIFT 12 /* AIF2_ERR_EINT */ 3375#define WM5100_AIF2_ERR_EINT_WIDTH 1 /* AIF2_ERR_EINT */ 3376#define WM5100_AIF1_ERR_EINT 0x0800 /* AIF1_ERR_EINT */ 3377#define WM5100_AIF1_ERR_EINT_MASK 0x0800 /* AIF1_ERR_EINT */ 3378#define WM5100_AIF1_ERR_EINT_SHIFT 11 /* AIF1_ERR_EINT */ 3379#define WM5100_AIF1_ERR_EINT_WIDTH 1 /* AIF1_ERR_EINT */ 3380#define WM5100_CTRLIF_ERR_EINT 0x0400 /* CTRLIF_ERR_EINT */ 3381#define WM5100_CTRLIF_ERR_EINT_MASK 0x0400 /* CTRLIF_ERR_EINT */ 3382#define WM5100_CTRLIF_ERR_EINT_SHIFT 10 /* CTRLIF_ERR_EINT */ 3383#define WM5100_CTRLIF_ERR_EINT_WIDTH 1 /* CTRLIF_ERR_EINT */ 3384#define WM5100_ISRC2_UNDERCLOCKED_EINT 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3385#define WM5100_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* ISRC2_UNDERCLOCKED_EINT */ 3386#define WM5100_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* ISRC2_UNDERCLOCKED_EINT */ 3387#define WM5100_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC2_UNDERCLOCKED_EINT */ 3388#define WM5100_ISRC1_UNDERCLOCKED_EINT 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3389#define WM5100_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* ISRC1_UNDERCLOCKED_EINT */ 3390#define WM5100_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* ISRC1_UNDERCLOCKED_EINT */ 3391#define WM5100_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* ISRC1_UNDERCLOCKED_EINT */ 3392#define WM5100_FX_UNDERCLOCKED_EINT 0x0080 /* FX_UNDERCLOCKED_EINT */ 3393#define WM5100_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* FX_UNDERCLOCKED_EINT */ 3394#define WM5100_FX_UNDERCLOCKED_EINT_SHIFT 7 /* FX_UNDERCLOCKED_EINT */ 3395#define WM5100_FX_UNDERCLOCKED_EINT_WIDTH 1 /* FX_UNDERCLOCKED_EINT */ 3396#define WM5100_AIF3_UNDERCLOCKED_EINT 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3397#define WM5100_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* AIF3_UNDERCLOCKED_EINT */ 3398#define WM5100_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* AIF3_UNDERCLOCKED_EINT */ 3399#define WM5100_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* AIF3_UNDERCLOCKED_EINT */ 3400#define WM5100_AIF2_UNDERCLOCKED_EINT 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3401#define WM5100_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* AIF2_UNDERCLOCKED_EINT */ 3402#define WM5100_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* AIF2_UNDERCLOCKED_EINT */ 3403#define WM5100_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* AIF2_UNDERCLOCKED_EINT */ 3404#define WM5100_AIF1_UNDERCLOCKED_EINT 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3405#define WM5100_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* AIF1_UNDERCLOCKED_EINT */ 3406#define WM5100_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* AIF1_UNDERCLOCKED_EINT */ 3407#define WM5100_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* AIF1_UNDERCLOCKED_EINT */ 3408#define WM5100_ASRC_UNDERCLOCKED_EINT 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3409#define WM5100_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* ASRC_UNDERCLOCKED_EINT */ 3410#define WM5100_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* ASRC_UNDERCLOCKED_EINT */ 3411#define WM5100_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* ASRC_UNDERCLOCKED_EINT */ 3412#define WM5100_DAC_UNDERCLOCKED_EINT 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3413#define WM5100_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* DAC_UNDERCLOCKED_EINT */ 3414#define WM5100_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* DAC_UNDERCLOCKED_EINT */ 3415#define WM5100_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* DAC_UNDERCLOCKED_EINT */ 3416#define WM5100_ADC_UNDERCLOCKED_EINT 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3417#define WM5100_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* ADC_UNDERCLOCKED_EINT */ 3418#define WM5100_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* ADC_UNDERCLOCKED_EINT */ 3419#define WM5100_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* ADC_UNDERCLOCKED_EINT */ 3420#define WM5100_MIXER_UNDERCLOCKED_EINT 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3421#define WM5100_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* MIXER_UNDERCLOCKED_EINT */ 3422#define WM5100_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* MIXER_UNDERCLOCKED_EINT */ 3423#define WM5100_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* MIXER_UNDERCLOCKED_EINT */ 3424 3425/* 3426 * R3332 (0xD04) - Interrupt Raw Status 2 3427 */ 3428#define WM5100_DSP_IRQ6_STS 0x0020 /* DSP_IRQ6_STS */ 3429#define WM5100_DSP_IRQ6_STS_MASK 0x0020 /* DSP_IRQ6_STS */ 3430#define WM5100_DSP_IRQ6_STS_SHIFT 5 /* DSP_IRQ6_STS */ 3431#define WM5100_DSP_IRQ6_STS_WIDTH 1 /* DSP_IRQ6_STS */ 3432#define WM5100_DSP_IRQ5_STS 0x0010 /* DSP_IRQ5_STS */ 3433#define WM5100_DSP_IRQ5_STS_MASK 0x0010 /* DSP_IRQ5_STS */ 3434#define WM5100_DSP_IRQ5_STS_SHIFT 4 /* DSP_IRQ5_STS */ 3435#define WM5100_DSP_IRQ5_STS_WIDTH 1 /* DSP_IRQ5_STS */ 3436#define WM5100_DSP_IRQ4_STS 0x0008 /* DSP_IRQ4_STS */ 3437#define WM5100_DSP_IRQ4_STS_MASK 0x0008 /* DSP_IRQ4_STS */ 3438#define WM5100_DSP_IRQ4_STS_SHIFT 3 /* DSP_IRQ4_STS */ 3439#define WM5100_DSP_IRQ4_STS_WIDTH 1 /* DSP_IRQ4_STS */ 3440#define WM5100_DSP_IRQ3_STS 0x0004 /* DSP_IRQ3_STS */ 3441#define WM5100_DSP_IRQ3_STS_MASK 0x0004 /* DSP_IRQ3_STS */ 3442#define WM5100_DSP_IRQ3_STS_SHIFT 2 /* DSP_IRQ3_STS */ 3443#define WM5100_DSP_IRQ3_STS_WIDTH 1 /* DSP_IRQ3_STS */ 3444#define WM5100_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */ 3445#define WM5100_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */ 3446#define WM5100_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */ 3447#define WM5100_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */ 3448#define WM5100_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */ 3449#define WM5100_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */ 3450#define WM5100_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */ 3451#define WM5100_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */ 3452 3453/* 3454 * R3333 (0xD05) - Interrupt Raw Status 3 3455 */ 3456#define WM5100_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3457#define WM5100_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */ 3458#define WM5100_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */ 3459#define WM5100_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */ 3460#define WM5100_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */ 3461#define WM5100_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */ 3462#define WM5100_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */ 3463#define WM5100_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */ 3464#define WM5100_HPDET_STS 0x2000 /* HPDET_STS */ 3465#define WM5100_HPDET_STS_MASK 0x2000 /* HPDET_STS */ 3466#define WM5100_HPDET_STS_SHIFT 13 /* HPDET_STS */ 3467#define WM5100_HPDET_STS_WIDTH 1 /* HPDET_STS */ 3468#define WM5100_DRC_SID_DET_STS 0x0200 /* DRC_SID_DET_STS */ 3469#define WM5100_DRC_SID_DET_STS_MASK 0x0200 /* DRC_SID_DET_STS */ 3470#define WM5100_DRC_SID_DET_STS_SHIFT 9 /* DRC_SID_DET_STS */ 3471#define WM5100_DRC_SID_DET_STS_WIDTH 1 /* DRC_SID_DET_STS */ 3472#define WM5100_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */ 3473#define WM5100_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */ 3474#define WM5100_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */ 3475#define WM5100_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */ 3476#define WM5100_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */ 3477#define WM5100_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */ 3478#define WM5100_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */ 3479#define WM5100_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */ 3480#define WM5100_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */ 3481#define WM5100_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */ 3482#define WM5100_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */ 3483#define WM5100_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */ 3484#define WM5100_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */ 3485#define WM5100_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */ 3486#define WM5100_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */ 3487#define WM5100_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */ 3488#define WM5100_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */ 3489#define WM5100_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */ 3490#define WM5100_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */ 3491#define WM5100_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */ 3492#define WM5100_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3493#define WM5100_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */ 3494#define WM5100_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */ 3495#define WM5100_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */ 3496 3497/* 3498 * R3334 (0xD06) - Interrupt Raw Status 4 3499 */ 3500#define WM5100_AIF3_ERR_STS 0x2000 /* AIF3_ERR_STS */ 3501#define WM5100_AIF3_ERR_STS_MASK 0x2000 /* AIF3_ERR_STS */ 3502#define WM5100_AIF3_ERR_STS_SHIFT 13 /* AIF3_ERR_STS */ 3503#define WM5100_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */ 3504#define WM5100_AIF2_ERR_STS 0x1000 /* AIF2_ERR_STS */ 3505#define WM5100_AIF2_ERR_STS_MASK 0x1000 /* AIF2_ERR_STS */ 3506#define WM5100_AIF2_ERR_STS_SHIFT 12 /* AIF2_ERR_STS */ 3507#define WM5100_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */ 3508#define WM5100_AIF1_ERR_STS 0x0800 /* AIF1_ERR_STS */ 3509#define WM5100_AIF1_ERR_STS_MASK 0x0800 /* AIF1_ERR_STS */ 3510#define WM5100_AIF1_ERR_STS_SHIFT 11 /* AIF1_ERR_STS */ 3511#define WM5100_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */ 3512#define WM5100_CTRLIF_ERR_STS 0x0400 /* CTRLIF_ERR_STS */ 3513#define WM5100_CTRLIF_ERR_STS_MASK 0x0400 /* CTRLIF_ERR_STS */ 3514#define WM5100_CTRLIF_ERR_STS_SHIFT 10 /* CTRLIF_ERR_STS */ 3515#define WM5100_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */ 3516#define WM5100_ISRC2_UNDERCLOCKED_STS 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3517#define WM5100_ISRC2_UNDERCLOCKED_STS_MASK 0x0200 /* ISRC2_UNDERCLOCKED_STS */ 3518#define WM5100_ISRC2_UNDERCLOCKED_STS_SHIFT 9 /* ISRC2_UNDERCLOCKED_STS */ 3519#define WM5100_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */ 3520#define WM5100_ISRC1_UNDERCLOCKED_STS 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3521#define WM5100_ISRC1_UNDERCLOCKED_STS_MASK 0x0100 /* ISRC1_UNDERCLOCKED_STS */ 3522#define WM5100_ISRC1_UNDERCLOCKED_STS_SHIFT 8 /* ISRC1_UNDERCLOCKED_STS */ 3523#define WM5100_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */ 3524#define WM5100_FX_UNDERCLOCKED_STS 0x0080 /* FX_UNDERCLOCKED_STS */ 3525#define WM5100_FX_UNDERCLOCKED_STS_MASK 0x0080 /* FX_UNDERCLOCKED_STS */ 3526#define WM5100_FX_UNDERCLOCKED_STS_SHIFT 7 /* FX_UNDERCLOCKED_STS */ 3527#define WM5100_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */ 3528#define WM5100_AIF3_UNDERCLOCKED_STS 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3529#define WM5100_AIF3_UNDERCLOCKED_STS_MASK 0x0040 /* AIF3_UNDERCLOCKED_STS */ 3530#define WM5100_AIF3_UNDERCLOCKED_STS_SHIFT 6 /* AIF3_UNDERCLOCKED_STS */ 3531#define WM5100_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */ 3532#define WM5100_AIF2_UNDERCLOCKED_STS 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3533#define WM5100_AIF2_UNDERCLOCKED_STS_MASK 0x0020 /* AIF2_UNDERCLOCKED_STS */ 3534#define WM5100_AIF2_UNDERCLOCKED_STS_SHIFT 5 /* AIF2_UNDERCLOCKED_STS */ 3535#define WM5100_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */ 3536#define WM5100_AIF1_UNDERCLOCKED_STS 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3537#define WM5100_AIF1_UNDERCLOCKED_STS_MASK 0x0010 /* AIF1_UNDERCLOCKED_STS */ 3538#define WM5100_AIF1_UNDERCLOCKED_STS_SHIFT 4 /* AIF1_UNDERCLOCKED_STS */ 3539#define WM5100_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */ 3540#define WM5100_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3541#define WM5100_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */ 3542#define WM5100_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */ 3543#define WM5100_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */ 3544#define WM5100_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */ 3545#define WM5100_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */ 3546#define WM5100_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */ 3547#define WM5100_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */ 3548#define WM5100_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */ 3549#define WM5100_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */ 3550#define WM5100_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */ 3551#define WM5100_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */ 3552#define WM5100_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3553#define WM5100_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */ 3554#define WM5100_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */ 3555#define WM5100_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */ 3556 3557/* 3558 * R3335 (0xD07) - Interrupt Status 1 Mask 3559 */ 3560#define WM5100_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */ 3561#define WM5100_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */ 3562#define WM5100_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */ 3563#define WM5100_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */ 3564#define WM5100_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 3565#define WM5100_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 3566#define WM5100_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 3567#define WM5100_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 3568#define WM5100_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 3569#define WM5100_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 3570#define WM5100_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 3571#define WM5100_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 3572#define WM5100_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 3573#define WM5100_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 3574#define WM5100_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 3575#define WM5100_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 3576#define WM5100_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 3577#define WM5100_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 3578#define WM5100_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 3579#define WM5100_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 3580#define WM5100_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 3581#define WM5100_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 3582#define WM5100_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 3583#define WM5100_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 3584 3585/* 3586 * R3336 (0xD08) - Interrupt Status 2 Mask 3587 */ 3588#define WM5100_IM_DSP_IRQ6_EINT 0x0020 /* IM_DSP_IRQ6_EINT */ 3589#define WM5100_IM_DSP_IRQ6_EINT_MASK 0x0020 /* IM_DSP_IRQ6_EINT */ 3590#define WM5100_IM_DSP_IRQ6_EINT_SHIFT 5 /* IM_DSP_IRQ6_EINT */ 3591#define WM5100_IM_DSP_IRQ6_EINT_WIDTH 1 /* IM_DSP_IRQ6_EINT */ 3592#define WM5100_IM_DSP_IRQ5_EINT 0x0010 /* IM_DSP_IRQ5_EINT */ 3593#define WM5100_IM_DSP_IRQ5_EINT_MASK 0x0010 /* IM_DSP_IRQ5_EINT */ 3594#define WM5100_IM_DSP_IRQ5_EINT_SHIFT 4 /* IM_DSP_IRQ5_EINT */ 3595#define WM5100_IM_DSP_IRQ5_EINT_WIDTH 1 /* IM_DSP_IRQ5_EINT */ 3596#define WM5100_IM_DSP_IRQ4_EINT 0x0008 /* IM_DSP_IRQ4_EINT */ 3597#define WM5100_IM_DSP_IRQ4_EINT_MASK 0x0008 /* IM_DSP_IRQ4_EINT */ 3598#define WM5100_IM_DSP_IRQ4_EINT_SHIFT 3 /* IM_DSP_IRQ4_EINT */ 3599#define WM5100_IM_DSP_IRQ4_EINT_WIDTH 1 /* IM_DSP_IRQ4_EINT */ 3600#define WM5100_IM_DSP_IRQ3_EINT 0x0004 /* IM_DSP_IRQ3_EINT */ 3601#define WM5100_IM_DSP_IRQ3_EINT_MASK 0x0004 /* IM_DSP_IRQ3_EINT */ 3602#define WM5100_IM_DSP_IRQ3_EINT_SHIFT 2 /* IM_DSP_IRQ3_EINT */ 3603#define WM5100_IM_DSP_IRQ3_EINT_WIDTH 1 /* IM_DSP_IRQ3_EINT */ 3604#define WM5100_IM_DSP_IRQ2_EINT 0x0002 /* IM_DSP_IRQ2_EINT */ 3605#define WM5100_IM_DSP_IRQ2_EINT_MASK 0x0002 /* IM_DSP_IRQ2_EINT */ 3606#define WM5100_IM_DSP_IRQ2_EINT_SHIFT 1 /* IM_DSP_IRQ2_EINT */ 3607#define WM5100_IM_DSP_IRQ2_EINT_WIDTH 1 /* IM_DSP_IRQ2_EINT */ 3608#define WM5100_IM_DSP_IRQ1_EINT 0x0001 /* IM_DSP_IRQ1_EINT */ 3609#define WM5100_IM_DSP_IRQ1_EINT_MASK 0x0001 /* IM_DSP_IRQ1_EINT */ 3610#define WM5100_IM_DSP_IRQ1_EINT_SHIFT 0 /* IM_DSP_IRQ1_EINT */ 3611#define WM5100_IM_DSP_IRQ1_EINT_WIDTH 1 /* IM_DSP_IRQ1_EINT */ 3612 3613/* 3614 * R3337 (0xD09) - Interrupt Status 3 Mask 3615 */ 3616#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3617#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3618#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3619#define WM5100_IM_SPK_SHUTDOWN_WARN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT */ 3620#define WM5100_IM_SPK_SHUTDOWN_EINT 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3621#define WM5100_IM_SPK_SHUTDOWN_EINT_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT */ 3622#define WM5100_IM_SPK_SHUTDOWN_EINT_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT */ 3623#define WM5100_IM_SPK_SHUTDOWN_EINT_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT */ 3624#define WM5100_IM_HPDET_EINT 0x2000 /* IM_HPDET_EINT */ 3625#define WM5100_IM_HPDET_EINT_MASK 0x2000 /* IM_HPDET_EINT */ 3626#define WM5100_IM_HPDET_EINT_SHIFT 13 /* IM_HPDET_EINT */ 3627#define WM5100_IM_HPDET_EINT_WIDTH 1 /* IM_HPDET_EINT */ 3628#define WM5100_IM_ACCDET_EINT 0x1000 /* IM_ACCDET_EINT */ 3629#define WM5100_IM_ACCDET_EINT_MASK 0x1000 /* IM_ACCDET_EINT */ 3630#define WM5100_IM_ACCDET_EINT_SHIFT 12 /* IM_ACCDET_EINT */ 3631#define WM5100_IM_ACCDET_EINT_WIDTH 1 /* IM_ACCDET_EINT */ 3632#define WM5100_IM_DRC_SIG_DET_EINT 0x0200 /* IM_DRC_SIG_DET_EINT */ 3633#define WM5100_IM_DRC_SIG_DET_EINT_MASK 0x0200 /* IM_DRC_SIG_DET_EINT */ 3634#define WM5100_IM_DRC_SIG_DET_EINT_SHIFT 9 /* IM_DRC_SIG_DET_EINT */ 3635#define WM5100_IM_DRC_SIG_DET_EINT_WIDTH 1 /* IM_DRC_SIG_DET_EINT */ 3636#define WM5100_IM_ASRC2_LOCK_EINT 0x0100 /* IM_ASRC2_LOCK_EINT */ 3637#define WM5100_IM_ASRC2_LOCK_EINT_MASK 0x0100 /* IM_ASRC2_LOCK_EINT */ 3638#define WM5100_IM_ASRC2_LOCK_EINT_SHIFT 8 /* IM_ASRC2_LOCK_EINT */ 3639#define WM5100_IM_ASRC2_LOCK_EINT_WIDTH 1 /* IM_ASRC2_LOCK_EINT */ 3640#define WM5100_IM_ASRC1_LOCK_EINT 0x0080 /* IM_ASRC1_LOCK_EINT */ 3641#define WM5100_IM_ASRC1_LOCK_EINT_MASK 0x0080 /* IM_ASRC1_LOCK_EINT */ 3642#define WM5100_IM_ASRC1_LOCK_EINT_SHIFT 7 /* IM_ASRC1_LOCK_EINT */ 3643#define WM5100_IM_ASRC1_LOCK_EINT_WIDTH 1 /* IM_ASRC1_LOCK_EINT */ 3644#define WM5100_IM_FLL2_LOCK_EINT 0x0008 /* IM_FLL2_LOCK_EINT */ 3645#define WM5100_IM_FLL2_LOCK_EINT_MASK 0x0008 /* IM_FLL2_LOCK_EINT */ 3646#define WM5100_IM_FLL2_LOCK_EINT_SHIFT 3 /* IM_FLL2_LOCK_EINT */ 3647#define WM5100_IM_FLL2_LOCK_EINT_WIDTH 1 /* IM_FLL2_LOCK_EINT */ 3648#define WM5100_IM_FLL1_LOCK_EINT 0x0004 /* IM_FLL1_LOCK_EINT */ 3649#define WM5100_IM_FLL1_LOCK_EINT_MASK 0x0004 /* IM_FLL1_LOCK_EINT */ 3650#define WM5100_IM_FLL1_LOCK_EINT_SHIFT 2 /* IM_FLL1_LOCK_EINT */ 3651#define WM5100_IM_FLL1_LOCK_EINT_WIDTH 1 /* IM_FLL1_LOCK_EINT */ 3652#define WM5100_IM_CLKGEN_ERR_EINT 0x0002 /* IM_CLKGEN_ERR_EINT */ 3653#define WM5100_IM_CLKGEN_ERR_EINT_MASK 0x0002 /* IM_CLKGEN_ERR_EINT */ 3654#define WM5100_IM_CLKGEN_ERR_EINT_SHIFT 1 /* IM_CLKGEN_ERR_EINT */ 3655#define WM5100_IM_CLKGEN_ERR_EINT_WIDTH 1 /* IM_CLKGEN_ERR_EINT */ 3656#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3657#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3658#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3659#define WM5100_IM_CLKGEN_ERR_ASYNC_EINT_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT */ 3660 3661/* 3662 * R3338 (0xD0A) - Interrupt Status 4 Mask 3663 */ 3664#define WM5100_IM_AIF3_ERR_EINT 0x2000 /* IM_AIF3_ERR_EINT */ 3665#define WM5100_IM_AIF3_ERR_EINT_MASK 0x2000 /* IM_AIF3_ERR_EINT */ 3666#define WM5100_IM_AIF3_ERR_EINT_SHIFT 13 /* IM_AIF3_ERR_EINT */ 3667#define WM5100_IM_AIF3_ERR_EINT_WIDTH 1 /* IM_AIF3_ERR_EINT */ 3668#define WM5100_IM_AIF2_ERR_EINT 0x1000 /* IM_AIF2_ERR_EINT */ 3669#define WM5100_IM_AIF2_ERR_EINT_MASK 0x1000 /* IM_AIF2_ERR_EINT */ 3670#define WM5100_IM_AIF2_ERR_EINT_SHIFT 12 /* IM_AIF2_ERR_EINT */ 3671#define WM5100_IM_AIF2_ERR_EINT_WIDTH 1 /* IM_AIF2_ERR_EINT */ 3672#define WM5100_IM_AIF1_ERR_EINT 0x0800 /* IM_AIF1_ERR_EINT */ 3673#define WM5100_IM_AIF1_ERR_EINT_MASK 0x0800 /* IM_AIF1_ERR_EINT */ 3674#define WM5100_IM_AIF1_ERR_EINT_SHIFT 11 /* IM_AIF1_ERR_EINT */ 3675#define WM5100_IM_AIF1_ERR_EINT_WIDTH 1 /* IM_AIF1_ERR_EINT */ 3676#define WM5100_IM_CTRLIF_ERR_EINT 0x0400 /* IM_CTRLIF_ERR_EINT */ 3677#define WM5100_IM_CTRLIF_ERR_EINT_MASK 0x0400 /* IM_CTRLIF_ERR_EINT */ 3678#define WM5100_IM_CTRLIF_ERR_EINT_SHIFT 10 /* IM_CTRLIF_ERR_EINT */ 3679#define WM5100_IM_CTRLIF_ERR_EINT_WIDTH 1 /* IM_CTRLIF_ERR_EINT */ 3680#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3681#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_MASK 0x0200 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3682#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_SHIFT 9 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3683#define WM5100_IM_ISRC2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC2_UNDERCLOCKED_EINT */ 3684#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3685#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_MASK 0x0100 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3686#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_SHIFT 8 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3687#define WM5100_IM_ISRC1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ISRC1_UNDERCLOCKED_EINT */ 3688#define WM5100_IM_FX_UNDERCLOCKED_EINT 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3689#define WM5100_IM_FX_UNDERCLOCKED_EINT_MASK 0x0080 /* IM_FX_UNDERCLOCKED_EINT */ 3690#define WM5100_IM_FX_UNDERCLOCKED_EINT_SHIFT 7 /* IM_FX_UNDERCLOCKED_EINT */ 3691#define WM5100_IM_FX_UNDERCLOCKED_EINT_WIDTH 1 /* IM_FX_UNDERCLOCKED_EINT */ 3692#define WM5100_IM_AIF3_UNDERCLOCKED_EINT 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3693#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_MASK 0x0040 /* IM_AIF3_UNDERCLOCKED_EINT */ 3694#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_SHIFT 6 /* IM_AIF3_UNDERCLOCKED_EINT */ 3695#define WM5100_IM_AIF3_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF3_UNDERCLOCKED_EINT */ 3696#define WM5100_IM_AIF2_UNDERCLOCKED_EINT 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3697#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_MASK 0x0020 /* IM_AIF2_UNDERCLOCKED_EINT */ 3698#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_SHIFT 5 /* IM_AIF2_UNDERCLOCKED_EINT */ 3699#define WM5100_IM_AIF2_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF2_UNDERCLOCKED_EINT */ 3700#define WM5100_IM_AIF1_UNDERCLOCKED_EINT 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3701#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_MASK 0x0010 /* IM_AIF1_UNDERCLOCKED_EINT */ 3702#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_SHIFT 4 /* IM_AIF1_UNDERCLOCKED_EINT */ 3703#define WM5100_IM_AIF1_UNDERCLOCKED_EINT_WIDTH 1 /* IM_AIF1_UNDERCLOCKED_EINT */ 3704#define WM5100_IM_ASRC_UNDERCLOCKED_EINT 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3705#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_MASK 0x0008 /* IM_ASRC_UNDERCLOCKED_EINT */ 3706#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_SHIFT 3 /* IM_ASRC_UNDERCLOCKED_EINT */ 3707#define WM5100_IM_ASRC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ASRC_UNDERCLOCKED_EINT */ 3708#define WM5100_IM_DAC_UNDERCLOCKED_EINT 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3709#define WM5100_IM_DAC_UNDERCLOCKED_EINT_MASK 0x0004 /* IM_DAC_UNDERCLOCKED_EINT */ 3710#define WM5100_IM_DAC_UNDERCLOCKED_EINT_SHIFT 2 /* IM_DAC_UNDERCLOCKED_EINT */ 3711#define WM5100_IM_DAC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_DAC_UNDERCLOCKED_EINT */ 3712#define WM5100_IM_ADC_UNDERCLOCKED_EINT 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3713#define WM5100_IM_ADC_UNDERCLOCKED_EINT_MASK 0x0002 /* IM_ADC_UNDERCLOCKED_EINT */ 3714#define WM5100_IM_ADC_UNDERCLOCKED_EINT_SHIFT 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3715#define WM5100_IM_ADC_UNDERCLOCKED_EINT_WIDTH 1 /* IM_ADC_UNDERCLOCKED_EINT */ 3716#define WM5100_IM_MIXER_UNDERCLOCKED_EINT 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3717#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_MASK 0x0001 /* IM_MIXER_UNDERCLOCKED_EINT */ 3718#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_SHIFT 0 /* IM_MIXER_UNDERCLOCKED_EINT */ 3719#define WM5100_IM_MIXER_UNDERCLOCKED_EINT_WIDTH 1 /* IM_MIXER_UNDERCLOCKED_EINT */ 3720 3721/* 3722 * R3359 (0xD1F) - Interrupt Control 3723 */ 3724#define WM5100_IM_IRQ 0x0001 /* IM_IRQ */ 3725#define WM5100_IM_IRQ_MASK 0x0001 /* IM_IRQ */ 3726#define WM5100_IM_IRQ_SHIFT 0 /* IM_IRQ */ 3727#define WM5100_IM_IRQ_WIDTH 1 /* IM_IRQ */ 3728 3729/* 3730 * R3360 (0xD20) - IRQ Debounce 1 3731 */ 3732#define WM5100_SPK_SHUTDOWN_WARN_DB 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3733#define WM5100_SPK_SHUTDOWN_WARN_DB_MASK 0x0200 /* SPK_SHUTDOWN_WARN_DB */ 3734#define WM5100_SPK_SHUTDOWN_WARN_DB_SHIFT 9 /* SPK_SHUTDOWN_WARN_DB */ 3735#define WM5100_SPK_SHUTDOWN_WARN_DB_WIDTH 1 /* SPK_SHUTDOWN_WARN_DB */ 3736#define WM5100_SPK_SHUTDOWN_DB 0x0100 /* SPK_SHUTDOWN_DB */ 3737#define WM5100_SPK_SHUTDOWN_DB_MASK 0x0100 /* SPK_SHUTDOWN_DB */ 3738#define WM5100_SPK_SHUTDOWN_DB_SHIFT 8 /* SPK_SHUTDOWN_DB */ 3739#define WM5100_SPK_SHUTDOWN_DB_WIDTH 1 /* SPK_SHUTDOWN_DB */ 3740#define WM5100_FLL1_LOCK_IRQ_DB 0x0008 /* FLL1_LOCK_IRQ_DB */ 3741#define WM5100_FLL1_LOCK_IRQ_DB_MASK 0x0008 /* FLL1_LOCK_IRQ_DB */ 3742#define WM5100_FLL1_LOCK_IRQ_DB_SHIFT 3 /* FLL1_LOCK_IRQ_DB */ 3743#define WM5100_FLL1_LOCK_IRQ_DB_WIDTH 1 /* FLL1_LOCK_IRQ_DB */ 3744#define WM5100_FLL2_LOCK_IRQ_DB 0x0004 /* FLL2_LOCK_IRQ_DB */ 3745#define WM5100_FLL2_LOCK_IRQ_DB_MASK 0x0004 /* FLL2_LOCK_IRQ_DB */ 3746#define WM5100_FLL2_LOCK_IRQ_DB_SHIFT 2 /* FLL2_LOCK_IRQ_DB */ 3747#define WM5100_FLL2_LOCK_IRQ_DB_WIDTH 1 /* FLL2_LOCK_IRQ_DB */ 3748#define WM5100_CLKGEN_ERR_IRQ_DB 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3749#define WM5100_CLKGEN_ERR_IRQ_DB_MASK 0x0002 /* CLKGEN_ERR_IRQ_DB */ 3750#define WM5100_CLKGEN_ERR_IRQ_DB_SHIFT 1 /* CLKGEN_ERR_IRQ_DB */ 3751#define WM5100_CLKGEN_ERR_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_IRQ_DB */ 3752#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3753#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_MASK 0x0001 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3754#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_SHIFT 0 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3755#define WM5100_CLKGEN_ERR_ASYNC_IRQ_DB_WIDTH 1 /* CLKGEN_ERR_ASYNC_IRQ_DB */ 3756 3757/* 3758 * R3361 (0xD21) - IRQ Debounce 2 3759 */ 3760#define WM5100_AIF_ERR_DB 0x0001 /* AIF_ERR_DB */ 3761#define WM5100_AIF_ERR_DB_MASK 0x0001 /* AIF_ERR_DB */ 3762#define WM5100_AIF_ERR_DB_SHIFT 0 /* AIF_ERR_DB */ 3763#define WM5100_AIF_ERR_DB_WIDTH 1 /* AIF_ERR_DB */ 3764 3765/* 3766 * R3584 (0xE00) - FX_Ctrl 3767 */ 3768#define WM5100_FX_STS_MASK 0xFFC0 /* FX_STS - [15:6] */ 3769#define WM5100_FX_STS_SHIFT 6 /* FX_STS - [15:6] */ 3770#define WM5100_FX_STS_WIDTH 10 /* FX_STS - [15:6] */ 3771#define WM5100_FX_RATE_MASK 0x0003 /* FX_RATE - [1:0] */ 3772#define WM5100_FX_RATE_SHIFT 0 /* FX_RATE - [1:0] */ 3773#define WM5100_FX_RATE_WIDTH 2 /* FX_RATE - [1:0] */ 3774 3775/* 3776 * R3600 (0xE10) - EQ1_1 3777 */ 3778#define WM5100_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */ 3779#define WM5100_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */ 3780#define WM5100_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */ 3781#define WM5100_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */ 3782#define WM5100_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */ 3783#define WM5100_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */ 3784#define WM5100_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */ 3785#define WM5100_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */ 3786#define WM5100_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */ 3787#define WM5100_EQ1_ENA 0x0001 /* EQ1_ENA */ 3788#define WM5100_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */ 3789#define WM5100_EQ1_ENA_SHIFT 0 /* EQ1_ENA */ 3790#define WM5100_EQ1_ENA_WIDTH 1 /* EQ1_ENA */ 3791 3792/* 3793 * R3601 (0xE11) - EQ1_2 3794 */ 3795#define WM5100_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */ 3796#define WM5100_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */ 3797#define WM5100_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */ 3798#define WM5100_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */ 3799#define WM5100_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */ 3800#define WM5100_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */ 3801 3802/* 3803 * R3602 (0xE12) - EQ1_3 3804 */ 3805#define WM5100_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */ 3806#define WM5100_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */ 3807#define WM5100_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */ 3808 3809/* 3810 * R3603 (0xE13) - EQ1_4 3811 */ 3812#define WM5100_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */ 3813#define WM5100_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */ 3814#define WM5100_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */ 3815 3816/* 3817 * R3604 (0xE14) - EQ1_5 3818 */ 3819#define WM5100_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */ 3820#define WM5100_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */ 3821#define WM5100_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */ 3822 3823/* 3824 * R3605 (0xE15) - EQ1_6 3825 */ 3826#define WM5100_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */ 3827#define WM5100_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */ 3828#define WM5100_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */ 3829 3830/* 3831 * R3606 (0xE16) - EQ1_7 3832 */ 3833#define WM5100_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */ 3834#define WM5100_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */ 3835#define WM5100_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */ 3836 3837/* 3838 * R3607 (0xE17) - EQ1_8 3839 */ 3840#define WM5100_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */ 3841#define WM5100_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */ 3842#define WM5100_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */ 3843 3844/* 3845 * R3608 (0xE18) - EQ1_9 3846 */ 3847#define WM5100_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */ 3848#define WM5100_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */ 3849#define WM5100_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */ 3850 3851/* 3852 * R3609 (0xE19) - EQ1_10 3853 */ 3854#define WM5100_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */ 3855#define WM5100_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */ 3856#define WM5100_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */ 3857 3858/* 3859 * R3610 (0xE1A) - EQ1_11 3860 */ 3861#define WM5100_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */ 3862#define WM5100_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */ 3863#define WM5100_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */ 3864 3865/* 3866 * R3611 (0xE1B) - EQ1_12 3867 */ 3868#define WM5100_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */ 3869#define WM5100_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */ 3870#define WM5100_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */ 3871 3872/* 3873 * R3612 (0xE1C) - EQ1_13 3874 */ 3875#define WM5100_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */ 3876#define WM5100_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */ 3877#define WM5100_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */ 3878 3879/* 3880 * R3613 (0xE1D) - EQ1_14 3881 */ 3882#define WM5100_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */ 3883#define WM5100_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */ 3884#define WM5100_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */ 3885 3886/* 3887 * R3614 (0xE1E) - EQ1_15 3888 */ 3889#define WM5100_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */ 3890#define WM5100_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */ 3891#define WM5100_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */ 3892 3893/* 3894 * R3615 (0xE1F) - EQ1_16 3895 */ 3896#define WM5100_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */ 3897#define WM5100_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */ 3898#define WM5100_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */ 3899 3900/* 3901 * R3616 (0xE20) - EQ1_17 3902 */ 3903#define WM5100_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */ 3904#define WM5100_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */ 3905#define WM5100_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */ 3906 3907/* 3908 * R3617 (0xE21) - EQ1_18 3909 */ 3910#define WM5100_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */ 3911#define WM5100_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */ 3912#define WM5100_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */ 3913 3914/* 3915 * R3618 (0xE22) - EQ1_19 3916 */ 3917#define WM5100_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */ 3918#define WM5100_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */ 3919#define WM5100_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */ 3920 3921/* 3922 * R3619 (0xE23) - EQ1_20 3923 */ 3924#define WM5100_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */ 3925#define WM5100_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */ 3926#define WM5100_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */ 3927 3928/* 3929 * R3622 (0xE26) - EQ2_1 3930 */ 3931#define WM5100_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */ 3932#define WM5100_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */ 3933#define WM5100_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */ 3934#define WM5100_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */ 3935#define WM5100_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */ 3936#define WM5100_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */ 3937#define WM5100_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */ 3938#define WM5100_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */ 3939#define WM5100_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */ 3940#define WM5100_EQ2_ENA 0x0001 /* EQ2_ENA */ 3941#define WM5100_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */ 3942#define WM5100_EQ2_ENA_SHIFT 0 /* EQ2_ENA */ 3943#define WM5100_EQ2_ENA_WIDTH 1 /* EQ2_ENA */ 3944 3945/* 3946 * R3623 (0xE27) - EQ2_2 3947 */ 3948#define WM5100_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */ 3949#define WM5100_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */ 3950#define WM5100_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */ 3951#define WM5100_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */ 3952#define WM5100_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */ 3953#define WM5100_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */ 3954 3955/* 3956 * R3624 (0xE28) - EQ2_3 3957 */ 3958#define WM5100_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */ 3959#define WM5100_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */ 3960#define WM5100_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */ 3961 3962/* 3963 * R3625 (0xE29) - EQ2_4 3964 */ 3965#define WM5100_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */ 3966#define WM5100_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */ 3967#define WM5100_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */ 3968 3969/* 3970 * R3626 (0xE2A) - EQ2_5 3971 */ 3972#define WM5100_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */ 3973#define WM5100_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */ 3974#define WM5100_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */ 3975 3976/* 3977 * R3627 (0xE2B) - EQ2_6 3978 */ 3979#define WM5100_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */ 3980#define WM5100_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */ 3981#define WM5100_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */ 3982 3983/* 3984 * R3628 (0xE2C) - EQ2_7 3985 */ 3986#define WM5100_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */ 3987#define WM5100_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */ 3988#define WM5100_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */ 3989 3990/* 3991 * R3629 (0xE2D) - EQ2_8 3992 */ 3993#define WM5100_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */ 3994#define WM5100_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */ 3995#define WM5100_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */ 3996 3997/* 3998 * R3630 (0xE2E) - EQ2_9 3999 */ 4000#define WM5100_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */ 4001#define WM5100_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */ 4002#define WM5100_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */ 4003 4004/* 4005 * R3631 (0xE2F) - EQ2_10 4006 */ 4007#define WM5100_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */ 4008#define WM5100_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */ 4009#define WM5100_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */ 4010 4011/* 4012 * R3632 (0xE30) - EQ2_11 4013 */ 4014#define WM5100_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */ 4015#define WM5100_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */ 4016#define WM5100_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */ 4017 4018/* 4019 * R3633 (0xE31) - EQ2_12 4020 */ 4021#define WM5100_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */ 4022#define WM5100_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */ 4023#define WM5100_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */ 4024 4025/* 4026 * R3634 (0xE32) - EQ2_13 4027 */ 4028#define WM5100_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */ 4029#define WM5100_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */ 4030#define WM5100_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */ 4031 4032/* 4033 * R3635 (0xE33) - EQ2_14 4034 */ 4035#define WM5100_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */ 4036#define WM5100_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */ 4037#define WM5100_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */ 4038 4039/* 4040 * R3636 (0xE34) - EQ2_15 4041 */ 4042#define WM5100_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */ 4043#define WM5100_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */ 4044#define WM5100_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */ 4045 4046/* 4047 * R3637 (0xE35) - EQ2_16 4048 */ 4049#define WM5100_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */ 4050#define WM5100_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */ 4051#define WM5100_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */ 4052 4053/* 4054 * R3638 (0xE36) - EQ2_17 4055 */ 4056#define WM5100_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */ 4057#define WM5100_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */ 4058#define WM5100_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */ 4059 4060/* 4061 * R3639 (0xE37) - EQ2_18 4062 */ 4063#define WM5100_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */ 4064#define WM5100_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */ 4065#define WM5100_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */ 4066 4067/* 4068 * R3640 (0xE38) - EQ2_19 4069 */ 4070#define WM5100_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */ 4071#define WM5100_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */ 4072#define WM5100_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */ 4073 4074/* 4075 * R3641 (0xE39) - EQ2_20 4076 */ 4077#define WM5100_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */ 4078#define WM5100_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */ 4079#define WM5100_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */ 4080 4081/* 4082 * R3644 (0xE3C) - EQ3_1 4083 */ 4084#define WM5100_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */ 4085#define WM5100_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */ 4086#define WM5100_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */ 4087#define WM5100_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */ 4088#define WM5100_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */ 4089#define WM5100_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */ 4090#define WM5100_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */ 4091#define WM5100_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */ 4092#define WM5100_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */ 4093#define WM5100_EQ3_ENA 0x0001 /* EQ3_ENA */ 4094#define WM5100_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */ 4095#define WM5100_EQ3_ENA_SHIFT 0 /* EQ3_ENA */ 4096#define WM5100_EQ3_ENA_WIDTH 1 /* EQ3_ENA */ 4097 4098/* 4099 * R3645 (0xE3D) - EQ3_2 4100 */ 4101#define WM5100_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */ 4102#define WM5100_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */ 4103#define WM5100_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */ 4104#define WM5100_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */ 4105#define WM5100_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */ 4106#define WM5100_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */ 4107 4108/* 4109 * R3646 (0xE3E) - EQ3_3 4110 */ 4111#define WM5100_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */ 4112#define WM5100_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */ 4113#define WM5100_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */ 4114 4115/* 4116 * R3647 (0xE3F) - EQ3_4 4117 */ 4118#define WM5100_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */ 4119#define WM5100_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */ 4120#define WM5100_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */ 4121 4122/* 4123 * R3648 (0xE40) - EQ3_5 4124 */ 4125#define WM5100_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */ 4126#define WM5100_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */ 4127#define WM5100_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */ 4128 4129/* 4130 * R3649 (0xE41) - EQ3_6 4131 */ 4132#define WM5100_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */ 4133#define WM5100_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */ 4134#define WM5100_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */ 4135 4136/* 4137 * R3650 (0xE42) - EQ3_7 4138 */ 4139#define WM5100_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */ 4140#define WM5100_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */ 4141#define WM5100_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */ 4142 4143/* 4144 * R3651 (0xE43) - EQ3_8 4145 */ 4146#define WM5100_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */ 4147#define WM5100_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */ 4148#define WM5100_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */ 4149 4150/* 4151 * R3652 (0xE44) - EQ3_9 4152 */ 4153#define WM5100_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */ 4154#define WM5100_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */ 4155#define WM5100_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */ 4156 4157/* 4158 * R3653 (0xE45) - EQ3_10 4159 */ 4160#define WM5100_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */ 4161#define WM5100_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */ 4162#define WM5100_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */ 4163 4164/* 4165 * R3654 (0xE46) - EQ3_11 4166 */ 4167#define WM5100_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */ 4168#define WM5100_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */ 4169#define WM5100_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */ 4170 4171/* 4172 * R3655 (0xE47) - EQ3_12 4173 */ 4174#define WM5100_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */ 4175#define WM5100_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */ 4176#define WM5100_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */ 4177 4178/* 4179 * R3656 (0xE48) - EQ3_13 4180 */ 4181#define WM5100_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */ 4182#define WM5100_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */ 4183#define WM5100_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */ 4184 4185/* 4186 * R3657 (0xE49) - EQ3_14 4187 */ 4188#define WM5100_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */ 4189#define WM5100_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */ 4190#define WM5100_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */ 4191 4192/* 4193 * R3658 (0xE4A) - EQ3_15 4194 */ 4195#define WM5100_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */ 4196#define WM5100_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */ 4197#define WM5100_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */ 4198 4199/* 4200 * R3659 (0xE4B) - EQ3_16 4201 */ 4202#define WM5100_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */ 4203#define WM5100_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */ 4204#define WM5100_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */ 4205 4206/* 4207 * R3660 (0xE4C) - EQ3_17 4208 */ 4209#define WM5100_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */ 4210#define WM5100_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */ 4211#define WM5100_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */ 4212 4213/* 4214 * R3661 (0xE4D) - EQ3_18 4215 */ 4216#define WM5100_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */ 4217#define WM5100_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */ 4218#define WM5100_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */ 4219 4220/* 4221 * R3662 (0xE4E) - EQ3_19 4222 */ 4223#define WM5100_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */ 4224#define WM5100_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */ 4225#define WM5100_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */ 4226 4227/* 4228 * R3663 (0xE4F) - EQ3_20 4229 */ 4230#define WM5100_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */ 4231#define WM5100_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */ 4232#define WM5100_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */ 4233 4234/* 4235 * R3666 (0xE52) - EQ4_1 4236 */ 4237#define WM5100_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */ 4238#define WM5100_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */ 4239#define WM5100_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */ 4240#define WM5100_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */ 4241#define WM5100_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */ 4242#define WM5100_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */ 4243#define WM5100_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */ 4244#define WM5100_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */ 4245#define WM5100_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */ 4246#define WM5100_EQ4_ENA 0x0001 /* EQ4_ENA */ 4247#define WM5100_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */ 4248#define WM5100_EQ4_ENA_SHIFT 0 /* EQ4_ENA */ 4249#define WM5100_EQ4_ENA_WIDTH 1 /* EQ4_ENA */ 4250 4251/* 4252 * R3667 (0xE53) - EQ4_2 4253 */ 4254#define WM5100_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */ 4255#define WM5100_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */ 4256#define WM5100_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */ 4257#define WM5100_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */ 4258#define WM5100_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */ 4259#define WM5100_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */ 4260 4261/* 4262 * R3668 (0xE54) - EQ4_3 4263 */ 4264#define WM5100_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */ 4265#define WM5100_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */ 4266#define WM5100_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */ 4267 4268/* 4269 * R3669 (0xE55) - EQ4_4 4270 */ 4271#define WM5100_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */ 4272#define WM5100_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */ 4273#define WM5100_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */ 4274 4275/* 4276 * R3670 (0xE56) - EQ4_5 4277 */ 4278#define WM5100_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */ 4279#define WM5100_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */ 4280#define WM5100_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */ 4281 4282/* 4283 * R3671 (0xE57) - EQ4_6 4284 */ 4285#define WM5100_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */ 4286#define WM5100_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */ 4287#define WM5100_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */ 4288 4289/* 4290 * R3672 (0xE58) - EQ4_7 4291 */ 4292#define WM5100_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */ 4293#define WM5100_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */ 4294#define WM5100_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */ 4295 4296/* 4297 * R3673 (0xE59) - EQ4_8 4298 */ 4299#define WM5100_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */ 4300#define WM5100_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */ 4301#define WM5100_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */ 4302 4303/* 4304 * R3674 (0xE5A) - EQ4_9 4305 */ 4306#define WM5100_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */ 4307#define WM5100_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */ 4308#define WM5100_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */ 4309 4310/* 4311 * R3675 (0xE5B) - EQ4_10 4312 */ 4313#define WM5100_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */ 4314#define WM5100_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */ 4315#define WM5100_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */ 4316 4317/* 4318 * R3676 (0xE5C) - EQ4_11 4319 */ 4320#define WM5100_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */ 4321#define WM5100_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */ 4322#define WM5100_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */ 4323 4324/* 4325 * R3677 (0xE5D) - EQ4_12 4326 */ 4327#define WM5100_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */ 4328#define WM5100_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */ 4329#define WM5100_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */ 4330 4331/* 4332 * R3678 (0xE5E) - EQ4_13 4333 */ 4334#define WM5100_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */ 4335#define WM5100_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */ 4336#define WM5100_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */ 4337 4338/* 4339 * R3679 (0xE5F) - EQ4_14 4340 */ 4341#define WM5100_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */ 4342#define WM5100_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */ 4343#define WM5100_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */ 4344 4345/* 4346 * R3680 (0xE60) - EQ4_15 4347 */ 4348#define WM5100_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */ 4349#define WM5100_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */ 4350#define WM5100_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */ 4351 4352/* 4353 * R3681 (0xE61) - EQ4_16 4354 */ 4355#define WM5100_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */ 4356#define WM5100_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */ 4357#define WM5100_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */ 4358 4359/* 4360 * R3682 (0xE62) - EQ4_17 4361 */ 4362#define WM5100_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */ 4363#define WM5100_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */ 4364#define WM5100_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */ 4365 4366/* 4367 * R3683 (0xE63) - EQ4_18 4368 */ 4369#define WM5100_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */ 4370#define WM5100_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */ 4371#define WM5100_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */ 4372 4373/* 4374 * R3684 (0xE64) - EQ4_19 4375 */ 4376#define WM5100_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */ 4377#define WM5100_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */ 4378#define WM5100_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */ 4379 4380/* 4381 * R3685 (0xE65) - EQ4_20 4382 */ 4383#define WM5100_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */ 4384#define WM5100_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */ 4385#define WM5100_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */ 4386 4387/* 4388 * R3712 (0xE80) - DRC1 ctrl1 4389 */ 4390#define WM5100_DRC_SIG_DET_RMS_MASK 0xF800 /* DRC_SIG_DET_RMS - [15:11] */ 4391#define WM5100_DRC_SIG_DET_RMS_SHIFT 11 /* DRC_SIG_DET_RMS - [15:11] */ 4392#define WM5100_DRC_SIG_DET_RMS_WIDTH 5 /* DRC_SIG_DET_RMS - [15:11] */ 4393#define WM5100_DRC_SIG_DET_PK_MASK 0x0600 /* DRC_SIG_DET_PK - [10:9] */ 4394#define WM5100_DRC_SIG_DET_PK_SHIFT 9 /* DRC_SIG_DET_PK - [10:9] */ 4395#define WM5100_DRC_SIG_DET_PK_WIDTH 2 /* DRC_SIG_DET_PK - [10:9] */ 4396#define WM5100_DRC_NG_ENA 0x0100 /* DRC_NG_ENA */ 4397#define WM5100_DRC_NG_ENA_MASK 0x0100 /* DRC_NG_ENA */ 4398#define WM5100_DRC_NG_ENA_SHIFT 8 /* DRC_NG_ENA */ 4399#define WM5100_DRC_NG_ENA_WIDTH 1 /* DRC_NG_ENA */ 4400#define WM5100_DRC_SIG_DET_MODE 0x0080 /* DRC_SIG_DET_MODE */ 4401#define WM5100_DRC_SIG_DET_MODE_MASK 0x0080 /* DRC_SIG_DET_MODE */ 4402#define WM5100_DRC_SIG_DET_MODE_SHIFT 7 /* DRC_SIG_DET_MODE */ 4403#define WM5100_DRC_SIG_DET_MODE_WIDTH 1 /* DRC_SIG_DET_MODE */ 4404#define WM5100_DRC_SIG_DET 0x0040 /* DRC_SIG_DET */ 4405#define WM5100_DRC_SIG_DET_MASK 0x0040 /* DRC_SIG_DET */ 4406#define WM5100_DRC_SIG_DET_SHIFT 6 /* DRC_SIG_DET */ 4407#define WM5100_DRC_SIG_DET_WIDTH 1 /* DRC_SIG_DET */ 4408#define WM5100_DRC_KNEE2_OP_ENA 0x0020 /* DRC_KNEE2_OP_ENA */ 4409#define WM5100_DRC_KNEE2_OP_ENA_MASK 0x0020 /* DRC_KNEE2_OP_ENA */ 4410#define WM5100_DRC_KNEE2_OP_ENA_SHIFT 5 /* DRC_KNEE2_OP_ENA */ 4411#define WM5100_DRC_KNEE2_OP_ENA_WIDTH 1 /* DRC_KNEE2_OP_ENA */ 4412#define WM5100_DRC_QR 0x0010 /* DRC_QR */ 4413#define WM5100_DRC_QR_MASK 0x0010 /* DRC_QR */ 4414#define WM5100_DRC_QR_SHIFT 4 /* DRC_QR */ 4415#define WM5100_DRC_QR_WIDTH 1 /* DRC_QR */ 4416#define WM5100_DRC_ANTICLIP 0x0008 /* DRC_ANTICLIP */ 4417#define WM5100_DRC_ANTICLIP_MASK 0x0008 /* DRC_ANTICLIP */ 4418#define WM5100_DRC_ANTICLIP_SHIFT 3 /* DRC_ANTICLIP */ 4419#define WM5100_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ 4420#define WM5100_DRCL_ENA 0x0002 /* DRCL_ENA */ 4421#define WM5100_DRCL_ENA_MASK 0x0002 /* DRCL_ENA */ 4422#define WM5100_DRCL_ENA_SHIFT 1 /* DRCL_ENA */ 4423#define WM5100_DRCL_ENA_WIDTH 1 /* DRCL_ENA */ 4424#define WM5100_DRCR_ENA 0x0001 /* DRCR_ENA */ 4425#define WM5100_DRCR_ENA_MASK 0x0001 /* DRCR_ENA */ 4426#define WM5100_DRCR_ENA_SHIFT 0 /* DRCR_ENA */ 4427#define WM5100_DRCR_ENA_WIDTH 1 /* DRCR_ENA */ 4428 4429/* 4430 * R3713 (0xE81) - DRC1 ctrl2 4431 */ 4432#define WM5100_DRC_ATK_MASK 0x1E00 /* DRC_ATK - [12:9] */ 4433#define WM5100_DRC_ATK_SHIFT 9 /* DRC_ATK - [12:9] */ 4434#define WM5100_DRC_ATK_WIDTH 4 /* DRC_ATK - [12:9] */ 4435#define WM5100_DRC_DCY_MASK 0x01E0 /* DRC_DCY - [8:5] */ 4436#define WM5100_DRC_DCY_SHIFT 5 /* DRC_DCY - [8:5] */ 4437#define WM5100_DRC_DCY_WIDTH 4 /* DRC_DCY - [8:5] */ 4438#define WM5100_DRC_MINGAIN_MASK 0x001C /* DRC_MINGAIN - [4:2] */ 4439#define WM5100_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [4:2] */ 4440#define WM5100_DRC_MINGAIN_WIDTH 3 /* DRC_MINGAIN - [4:2] */ 4441#define WM5100_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 4442#define WM5100_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 4443#define WM5100_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 4444 4445/* 4446 * R3714 (0xE82) - DRC1 ctrl3 4447 */ 4448#define WM5100_DRC_NG_MINGAIN_MASK 0xF000 /* DRC_NG_MINGAIN - [15:12] */ 4449#define WM5100_DRC_NG_MINGAIN_SHIFT 12 /* DRC_NG_MINGAIN - [15:12] */ 4450#define WM5100_DRC_NG_MINGAIN_WIDTH 4 /* DRC_NG_MINGAIN - [15:12] */ 4451#define WM5100_DRC_NG_EXP_MASK 0x0C00 /* DRC_NG_EXP - [11:10] */ 4452#define WM5100_DRC_NG_EXP_SHIFT 10 /* DRC_NG_EXP - [11:10] */ 4453#define WM5100_DRC_NG_EXP_WIDTH 2 /* DRC_NG_EXP - [11:10] */ 4454#define WM5100_DRC_QR_THR_MASK 0x0300 /* DRC_QR_THR - [9:8] */ 4455#define WM5100_DRC_QR_THR_SHIFT 8 /* DRC_QR_THR - [9:8] */ 4456#define WM5100_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [9:8] */ 4457#define WM5100_DRC_QR_DCY_MASK 0x00C0 /* DRC_QR_DCY - [7:6] */ 4458#define WM5100_DRC_QR_DCY_SHIFT 6 /* DRC_QR_DCY - [7:6] */ 4459#define WM5100_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [7:6] */ 4460#define WM5100_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ 4461#define WM5100_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ 4462#define WM5100_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ 4463#define WM5100_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ 4464#define WM5100_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ 4465#define WM5100_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ 4466 4467/* 4468 * R3715 (0xE83) - DRC1 ctrl4 4469 */ 4470#define WM5100_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ 4471#define WM5100_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ 4472#define WM5100_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ 4473#define WM5100_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ 4474#define WM5100_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ 4475#define WM5100_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ 4476 4477/* 4478 * R3716 (0xE84) - DRC1 ctrl5 4479 */ 4480#define WM5100_DRC_KNEE2_IP_MASK 0x03E0 /* DRC_KNEE2_IP - [9:5] */ 4481#define WM5100_DRC_KNEE2_IP_SHIFT 5 /* DRC_KNEE2_IP - [9:5] */ 4482#define WM5100_DRC_KNEE2_IP_WIDTH 5 /* DRC_KNEE2_IP - [9:5] */ 4483#define WM5100_DRC_KNEE2_OP_MASK 0x001F /* DRC_KNEE2_OP - [4:0] */ 4484#define WM5100_DRC_KNEE2_OP_SHIFT 0 /* DRC_KNEE2_OP - [4:0] */ 4485#define WM5100_DRC_KNEE2_OP_WIDTH 5 /* DRC_KNEE2_OP - [4:0] */ 4486 4487/* 4488 * R3776 (0xEC0) - HPLPF1_1 4489 */ 4490#define WM5100_LHPF1_MODE 0x0002 /* LHPF1_MODE */ 4491#define WM5100_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */ 4492#define WM5100_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */ 4493#define WM5100_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */ 4494#define WM5100_LHPF1_ENA 0x0001 /* LHPF1_ENA */ 4495#define WM5100_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */ 4496#define WM5100_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */ 4497#define WM5100_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */ 4498 4499/* 4500 * R3777 (0xEC1) - HPLPF1_2 4501 */ 4502#define WM5100_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */ 4503#define WM5100_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */ 4504#define WM5100_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */ 4505 4506/* 4507 * R3780 (0xEC4) - HPLPF2_1 4508 */ 4509#define WM5100_LHPF2_MODE 0x0002 /* LHPF2_MODE */ 4510#define WM5100_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */ 4511#define WM5100_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */ 4512#define WM5100_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */ 4513#define WM5100_LHPF2_ENA 0x0001 /* LHPF2_ENA */ 4514#define WM5100_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */ 4515#define WM5100_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */ 4516#define WM5100_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */ 4517 4518/* 4519 * R3781 (0xEC5) - HPLPF2_2 4520 */ 4521#define WM5100_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */ 4522#define WM5100_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */ 4523#define WM5100_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */ 4524 4525/* 4526 * R3784 (0xEC8) - HPLPF3_1 4527 */ 4528#define WM5100_LHPF3_MODE 0x0002 /* LHPF3_MODE */ 4529#define WM5100_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */ 4530#define WM5100_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */ 4531#define WM5100_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */ 4532#define WM5100_LHPF3_ENA 0x0001 /* LHPF3_ENA */ 4533#define WM5100_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */ 4534#define WM5100_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */ 4535#define WM5100_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */ 4536 4537/* 4538 * R3785 (0xEC9) - HPLPF3_2 4539 */ 4540#define WM5100_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */ 4541#define WM5100_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */ 4542#define WM5100_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */ 4543 4544/* 4545 * R3788 (0xECC) - HPLPF4_1 4546 */ 4547#define WM5100_LHPF4_MODE 0x0002 /* LHPF4_MODE */ 4548#define WM5100_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */ 4549#define WM5100_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */ 4550#define WM5100_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */ 4551#define WM5100_LHPF4_ENA 0x0001 /* LHPF4_ENA */ 4552#define WM5100_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */ 4553#define WM5100_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */ 4554#define WM5100_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */ 4555 4556/* 4557 * R3789 (0xECD) - HPLPF4_2 4558 */ 4559#define WM5100_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */ 4560#define WM5100_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */ 4561#define WM5100_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */ 4562 4563/* 4564 * R16384 (0x4000) - DSP1 DM 0 4565 */ 4566#define WM5100_DSP1_DM_START_1_MASK 0x00FF /* DSP1_DM_START - [7:0] */ 4567#define WM5100_DSP1_DM_START_1_SHIFT 0 /* DSP1_DM_START - [7:0] */ 4568#define WM5100_DSP1_DM_START_1_WIDTH 8 /* DSP1_DM_START - [7:0] */ 4569 4570/* 4571 * R16385 (0x4001) - DSP1 DM 1 4572 */ 4573#define WM5100_DSP1_DM_START_MASK 0xFFFF /* DSP1_DM_START - [15:0] */ 4574#define WM5100_DSP1_DM_START_SHIFT 0 /* DSP1_DM_START - [15:0] */ 4575#define WM5100_DSP1_DM_START_WIDTH 16 /* DSP1_DM_START - [15:0] */ 4576 4577/* 4578 * R16386 (0x4002) - DSP1 DM 2 4579 */ 4580#define WM5100_DSP1_DM_1_1_MASK 0x00FF /* DSP1_DM_1 - [7:0] */ 4581#define WM5100_DSP1_DM_1_1_SHIFT 0 /* DSP1_DM_1 - [7:0] */ 4582#define WM5100_DSP1_DM_1_1_WIDTH 8 /* DSP1_DM_1 - [7:0] */ 4583 4584/* 4585 * R16387 (0x4003) - DSP1 DM 3 4586 */ 4587#define WM5100_DSP1_DM_1_MASK 0xFFFF /* DSP1_DM_1 - [15:0] */ 4588#define WM5100_DSP1_DM_1_SHIFT 0 /* DSP1_DM_1 - [15:0] */ 4589#define WM5100_DSP1_DM_1_WIDTH 16 /* DSP1_DM_1 - [15:0] */ 4590 4591/* 4592 * R16892 (0x41FC) - DSP1 DM 508 4593 */ 4594#define WM5100_DSP1_DM_254_1_MASK 0x00FF /* DSP1_DM_254 - [7:0] */ 4595#define WM5100_DSP1_DM_254_1_SHIFT 0 /* DSP1_DM_254 - [7:0] */ 4596#define WM5100_DSP1_DM_254_1_WIDTH 8 /* DSP1_DM_254 - [7:0] */ 4597 4598/* 4599 * R16893 (0x41FD) - DSP1 DM 509 4600 */ 4601#define WM5100_DSP1_DM_254_MASK 0xFFFF /* DSP1_DM_254 - [15:0] */ 4602#define WM5100_DSP1_DM_254_SHIFT 0 /* DSP1_DM_254 - [15:0] */ 4603#define WM5100_DSP1_DM_254_WIDTH 16 /* DSP1_DM_254 - [15:0] */ 4604 4605/* 4606 * R16894 (0x41FE) - DSP1 DM 510 4607 */ 4608#define WM5100_DSP1_DM_END_1_MASK 0x00FF /* DSP1_DM_END - [7:0] */ 4609#define WM5100_DSP1_DM_END_1_SHIFT 0 /* DSP1_DM_END - [7:0] */ 4610#define WM5100_DSP1_DM_END_1_WIDTH 8 /* DSP1_DM_END - [7:0] */ 4611 4612/* 4613 * R16895 (0x41FF) - DSP1 DM 511 4614 */ 4615#define WM5100_DSP1_DM_END_MASK 0xFFFF /* DSP1_DM_END - [15:0] */ 4616#define WM5100_DSP1_DM_END_SHIFT 0 /* DSP1_DM_END - [15:0] */ 4617#define WM5100_DSP1_DM_END_WIDTH 16 /* DSP1_DM_END - [15:0] */ 4618 4619/* 4620 * R18432 (0x4800) - DSP1 PM 0 4621 */ 4622#define WM5100_DSP1_PM_START_2_MASK 0x00FF /* DSP1_PM_START - [7:0] */ 4623#define WM5100_DSP1_PM_START_2_SHIFT 0 /* DSP1_PM_START - [7:0] */ 4624#define WM5100_DSP1_PM_START_2_WIDTH 8 /* DSP1_PM_START - [7:0] */ 4625 4626/* 4627 * R18433 (0x4801) - DSP1 PM 1 4628 */ 4629#define WM5100_DSP1_PM_START_1_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4630#define WM5100_DSP1_PM_START_1_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4631#define WM5100_DSP1_PM_START_1_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4632 4633/* 4634 * R18434 (0x4802) - DSP1 PM 2 4635 */ 4636#define WM5100_DSP1_PM_START_MASK 0xFFFF /* DSP1_PM_START - [15:0] */ 4637#define WM5100_DSP1_PM_START_SHIFT 0 /* DSP1_PM_START - [15:0] */ 4638#define WM5100_DSP1_PM_START_WIDTH 16 /* DSP1_PM_START - [15:0] */ 4639 4640/* 4641 * R18435 (0x4803) - DSP1 PM 3 4642 */ 4643#define WM5100_DSP1_PM_1_2_MASK 0x00FF /* DSP1_PM_1 - [7:0] */ 4644#define WM5100_DSP1_PM_1_2_SHIFT 0 /* DSP1_PM_1 - [7:0] */ 4645#define WM5100_DSP1_PM_1_2_WIDTH 8 /* DSP1_PM_1 - [7:0] */ 4646 4647/* 4648 * R18436 (0x4804) - DSP1 PM 4 4649 */ 4650#define WM5100_DSP1_PM_1_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4651#define WM5100_DSP1_PM_1_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4652#define WM5100_DSP1_PM_1_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4653 4654/* 4655 * R18437 (0x4805) - DSP1 PM 5 4656 */ 4657#define WM5100_DSP1_PM_1_MASK 0xFFFF /* DSP1_PM_1 - [15:0] */ 4658#define WM5100_DSP1_PM_1_SHIFT 0 /* DSP1_PM_1 - [15:0] */ 4659#define WM5100_DSP1_PM_1_WIDTH 16 /* DSP1_PM_1 - [15:0] */ 4660 4661/* 4662 * R19962 (0x4DFA) - DSP1 PM 1530 4663 */ 4664#define WM5100_DSP1_PM_510_2_MASK 0x00FF /* DSP1_PM_510 - [7:0] */ 4665#define WM5100_DSP1_PM_510_2_SHIFT 0 /* DSP1_PM_510 - [7:0] */ 4666#define WM5100_DSP1_PM_510_2_WIDTH 8 /* DSP1_PM_510 - [7:0] */ 4667 4668/* 4669 * R19963 (0x4DFB) - DSP1 PM 1531 4670 */ 4671#define WM5100_DSP1_PM_510_1_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4672#define WM5100_DSP1_PM_510_1_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4673#define WM5100_DSP1_PM_510_1_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4674 4675/* 4676 * R19964 (0x4DFC) - DSP1 PM 1532 4677 */ 4678#define WM5100_DSP1_PM_510_MASK 0xFFFF /* DSP1_PM_510 - [15:0] */ 4679#define WM5100_DSP1_PM_510_SHIFT 0 /* DSP1_PM_510 - [15:0] */ 4680#define WM5100_DSP1_PM_510_WIDTH 16 /* DSP1_PM_510 - [15:0] */ 4681 4682/* 4683 * R19965 (0x4DFD) - DSP1 PM 1533 4684 */ 4685#define WM5100_DSP1_PM_END_2_MASK 0x00FF /* DSP1_PM_END - [7:0] */ 4686#define WM5100_DSP1_PM_END_2_SHIFT 0 /* DSP1_PM_END - [7:0] */ 4687#define WM5100_DSP1_PM_END_2_WIDTH 8 /* DSP1_PM_END - [7:0] */ 4688 4689/* 4690 * R19966 (0x4DFE) - DSP1 PM 1534 4691 */ 4692#define WM5100_DSP1_PM_END_1_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4693#define WM5100_DSP1_PM_END_1_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4694#define WM5100_DSP1_PM_END_1_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4695 4696/* 4697 * R19967 (0x4DFF) - DSP1 PM 1535 4698 */ 4699#define WM5100_DSP1_PM_END_MASK 0xFFFF /* DSP1_PM_END - [15:0] */ 4700#define WM5100_DSP1_PM_END_SHIFT 0 /* DSP1_PM_END - [15:0] */ 4701#define WM5100_DSP1_PM_END_WIDTH 16 /* DSP1_PM_END - [15:0] */ 4702 4703/* 4704 * R20480 (0x5000) - DSP1 ZM 0 4705 */ 4706#define WM5100_DSP1_ZM_START_1_MASK 0x00FF /* DSP1_ZM_START - [7:0] */ 4707#define WM5100_DSP1_ZM_START_1_SHIFT 0 /* DSP1_ZM_START - [7:0] */ 4708#define WM5100_DSP1_ZM_START_1_WIDTH 8 /* DSP1_ZM_START - [7:0] */ 4709 4710/* 4711 * R20481 (0x5001) - DSP1 ZM 1 4712 */ 4713#define WM5100_DSP1_ZM_START_MASK 0xFFFF /* DSP1_ZM_START - [15:0] */ 4714#define WM5100_DSP1_ZM_START_SHIFT 0 /* DSP1_ZM_START - [15:0] */ 4715#define WM5100_DSP1_ZM_START_WIDTH 16 /* DSP1_ZM_START - [15:0] */ 4716 4717/* 4718 * R20482 (0x5002) - DSP1 ZM 2 4719 */ 4720#define WM5100_DSP1_ZM_1_1_MASK 0x00FF /* DSP1_ZM_1 - [7:0] */ 4721#define WM5100_DSP1_ZM_1_1_SHIFT 0 /* DSP1_ZM_1 - [7:0] */ 4722#define WM5100_DSP1_ZM_1_1_WIDTH 8 /* DSP1_ZM_1 - [7:0] */ 4723 4724/* 4725 * R20483 (0x5003) - DSP1 ZM 3 4726 */ 4727#define WM5100_DSP1_ZM_1_MASK 0xFFFF /* DSP1_ZM_1 - [15:0] */ 4728#define WM5100_DSP1_ZM_1_SHIFT 0 /* DSP1_ZM_1 - [15:0] */ 4729#define WM5100_DSP1_ZM_1_WIDTH 16 /* DSP1_ZM_1 - [15:0] */ 4730 4731/* 4732 * R22524 (0x57FC) - DSP1 ZM 2044 4733 */ 4734#define WM5100_DSP1_ZM_1022_1_MASK 0x00FF /* DSP1_ZM_1022 - [7:0] */ 4735#define WM5100_DSP1_ZM_1022_1_SHIFT 0 /* DSP1_ZM_1022 - [7:0] */ 4736#define WM5100_DSP1_ZM_1022_1_WIDTH 8 /* DSP1_ZM_1022 - [7:0] */ 4737 4738/* 4739 * R22525 (0x57FD) - DSP1 ZM 2045 4740 */ 4741#define WM5100_DSP1_ZM_1022_MASK 0xFFFF /* DSP1_ZM_1022 - [15:0] */ 4742#define WM5100_DSP1_ZM_1022_SHIFT 0 /* DSP1_ZM_1022 - [15:0] */ 4743#define WM5100_DSP1_ZM_1022_WIDTH 16 /* DSP1_ZM_1022 - [15:0] */ 4744 4745/* 4746 * R22526 (0x57FE) - DSP1 ZM 2046 4747 */ 4748#define WM5100_DSP1_ZM_END_1_MASK 0x00FF /* DSP1_ZM_END - [7:0] */ 4749#define WM5100_DSP1_ZM_END_1_SHIFT 0 /* DSP1_ZM_END - [7:0] */ 4750#define WM5100_DSP1_ZM_END_1_WIDTH 8 /* DSP1_ZM_END - [7:0] */ 4751 4752/* 4753 * R22527 (0x57FF) - DSP1 ZM 2047 4754 */ 4755#define WM5100_DSP1_ZM_END_MASK 0xFFFF /* DSP1_ZM_END - [15:0] */ 4756#define WM5100_DSP1_ZM_END_SHIFT 0 /* DSP1_ZM_END - [15:0] */ 4757#define WM5100_DSP1_ZM_END_WIDTH 16 /* DSP1_ZM_END - [15:0] */ 4758 4759/* 4760 * R24576 (0x6000) - DSP2 DM 0 4761 */ 4762#define WM5100_DSP2_DM_START_1_MASK 0x00FF /* DSP2_DM_START - [7:0] */ 4763#define WM5100_DSP2_DM_START_1_SHIFT 0 /* DSP2_DM_START - [7:0] */ 4764#define WM5100_DSP2_DM_START_1_WIDTH 8 /* DSP2_DM_START - [7:0] */ 4765 4766/* 4767 * R24577 (0x6001) - DSP2 DM 1 4768 */ 4769#define WM5100_DSP2_DM_START_MASK 0xFFFF /* DSP2_DM_START - [15:0] */ 4770#define WM5100_DSP2_DM_START_SHIFT 0 /* DSP2_DM_START - [15:0] */ 4771#define WM5100_DSP2_DM_START_WIDTH 16 /* DSP2_DM_START - [15:0] */ 4772 4773/* 4774 * R24578 (0x6002) - DSP2 DM 2 4775 */ 4776#define WM5100_DSP2_DM_1_1_MASK 0x00FF /* DSP2_DM_1 - [7:0] */ 4777#define WM5100_DSP2_DM_1_1_SHIFT 0 /* DSP2_DM_1 - [7:0] */ 4778#define WM5100_DSP2_DM_1_1_WIDTH 8 /* DSP2_DM_1 - [7:0] */ 4779 4780/* 4781 * R24579 (0x6003) - DSP2 DM 3 4782 */ 4783#define WM5100_DSP2_DM_1_MASK 0xFFFF /* DSP2_DM_1 - [15:0] */ 4784#define WM5100_DSP2_DM_1_SHIFT 0 /* DSP2_DM_1 - [15:0] */ 4785#define WM5100_DSP2_DM_1_WIDTH 16 /* DSP2_DM_1 - [15:0] */ 4786 4787/* 4788 * R25084 (0x61FC) - DSP2 DM 508 4789 */ 4790#define WM5100_DSP2_DM_254_1_MASK 0x00FF /* DSP2_DM_254 - [7:0] */ 4791#define WM5100_DSP2_DM_254_1_SHIFT 0 /* DSP2_DM_254 - [7:0] */ 4792#define WM5100_DSP2_DM_254_1_WIDTH 8 /* DSP2_DM_254 - [7:0] */ 4793 4794/* 4795 * R25085 (0x61FD) - DSP2 DM 509 4796 */ 4797#define WM5100_DSP2_DM_254_MASK 0xFFFF /* DSP2_DM_254 - [15:0] */ 4798#define WM5100_DSP2_DM_254_SHIFT 0 /* DSP2_DM_254 - [15:0] */ 4799#define WM5100_DSP2_DM_254_WIDTH 16 /* DSP2_DM_254 - [15:0] */ 4800 4801/* 4802 * R25086 (0x61FE) - DSP2 DM 510 4803 */ 4804#define WM5100_DSP2_DM_END_1_MASK 0x00FF /* DSP2_DM_END - [7:0] */ 4805#define WM5100_DSP2_DM_END_1_SHIFT 0 /* DSP2_DM_END - [7:0] */ 4806#define WM5100_DSP2_DM_END_1_WIDTH 8 /* DSP2_DM_END - [7:0] */ 4807 4808/* 4809 * R25087 (0x61FF) - DSP2 DM 511 4810 */ 4811#define WM5100_DSP2_DM_END_MASK 0xFFFF /* DSP2_DM_END - [15:0] */ 4812#define WM5100_DSP2_DM_END_SHIFT 0 /* DSP2_DM_END - [15:0] */ 4813#define WM5100_DSP2_DM_END_WIDTH 16 /* DSP2_DM_END - [15:0] */ 4814 4815/* 4816 * R26624 (0x6800) - DSP2 PM 0 4817 */ 4818#define WM5100_DSP2_PM_START_2_MASK 0x00FF /* DSP2_PM_START - [7:0] */ 4819#define WM5100_DSP2_PM_START_2_SHIFT 0 /* DSP2_PM_START - [7:0] */ 4820#define WM5100_DSP2_PM_START_2_WIDTH 8 /* DSP2_PM_START - [7:0] */ 4821 4822/* 4823 * R26625 (0x6801) - DSP2 PM 1 4824 */ 4825#define WM5100_DSP2_PM_START_1_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4826#define WM5100_DSP2_PM_START_1_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4827#define WM5100_DSP2_PM_START_1_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4828 4829/* 4830 * R26626 (0x6802) - DSP2 PM 2 4831 */ 4832#define WM5100_DSP2_PM_START_MASK 0xFFFF /* DSP2_PM_START - [15:0] */ 4833#define WM5100_DSP2_PM_START_SHIFT 0 /* DSP2_PM_START - [15:0] */ 4834#define WM5100_DSP2_PM_START_WIDTH 16 /* DSP2_PM_START - [15:0] */ 4835 4836/* 4837 * R26627 (0x6803) - DSP2 PM 3 4838 */ 4839#define WM5100_DSP2_PM_1_2_MASK 0x00FF /* DSP2_PM_1 - [7:0] */ 4840#define WM5100_DSP2_PM_1_2_SHIFT 0 /* DSP2_PM_1 - [7:0] */ 4841#define WM5100_DSP2_PM_1_2_WIDTH 8 /* DSP2_PM_1 - [7:0] */ 4842 4843/* 4844 * R26628 (0x6804) - DSP2 PM 4 4845 */ 4846#define WM5100_DSP2_PM_1_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 4847#define WM5100_DSP2_PM_1_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 4848#define WM5100_DSP2_PM_1_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 4849 4850/* 4851 * R26629 (0x6805) - DSP2 PM 5 4852 */ 4853#define WM5100_DSP2_PM_1_MASK 0xFFFF /* DSP2_PM_1 - [15:0] */ 4854#define WM5100_DSP2_PM_1_SHIFT 0 /* DSP2_PM_1 - [15:0] */ 4855#define WM5100_DSP2_PM_1_WIDTH 16 /* DSP2_PM_1 - [15:0] */ 4856 4857/* 4858 * R28154 (0x6DFA) - DSP2 PM 1530 4859 */ 4860#define WM5100_DSP2_PM_510_2_MASK 0x00FF /* DSP2_PM_510 - [7:0] */ 4861#define WM5100_DSP2_PM_510_2_SHIFT 0 /* DSP2_PM_510 - [7:0] */ 4862#define WM5100_DSP2_PM_510_2_WIDTH 8 /* DSP2_PM_510 - [7:0] */ 4863 4864/* 4865 * R28155 (0x6DFB) - DSP2 PM 1531 4866 */ 4867#define WM5100_DSP2_PM_510_1_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 4868#define WM5100_DSP2_PM_510_1_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 4869#define WM5100_DSP2_PM_510_1_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 4870 4871/* 4872 * R28156 (0x6DFC) - DSP2 PM 1532 4873 */ 4874#define WM5100_DSP2_PM_510_MASK 0xFFFF /* DSP2_PM_510 - [15:0] */ 4875#define WM5100_DSP2_PM_510_SHIFT 0 /* DSP2_PM_510 - [15:0] */ 4876#define WM5100_DSP2_PM_510_WIDTH 16 /* DSP2_PM_510 - [15:0] */ 4877 4878/* 4879 * R28157 (0x6DFD) - DSP2 PM 1533 4880 */ 4881#define WM5100_DSP2_PM_END_2_MASK 0x00FF /* DSP2_PM_END - [7:0] */ 4882#define WM5100_DSP2_PM_END_2_SHIFT 0 /* DSP2_PM_END - [7:0] */ 4883#define WM5100_DSP2_PM_END_2_WIDTH 8 /* DSP2_PM_END - [7:0] */ 4884 4885/* 4886 * R28158 (0x6DFE) - DSP2 PM 1534 4887 */ 4888#define WM5100_DSP2_PM_END_1_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 4889#define WM5100_DSP2_PM_END_1_SHIFT 0 /* DSP2_PM_END - [15:0] */ 4890#define WM5100_DSP2_PM_END_1_WIDTH 16 /* DSP2_PM_END - [15:0] */ 4891 4892/* 4893 * R28159 (0x6DFF) - DSP2 PM 1535 4894 */ 4895#define WM5100_DSP2_PM_END_MASK 0xFFFF /* DSP2_PM_END - [15:0] */ 4896#define WM5100_DSP2_PM_END_SHIFT 0 /* DSP2_PM_END - [15:0] */ 4897#define WM5100_DSP2_PM_END_WIDTH 16 /* DSP2_PM_END - [15:0] */ 4898 4899/* 4900 * R28672 (0x7000) - DSP2 ZM 0 4901 */ 4902#define WM5100_DSP2_ZM_START_1_MASK 0x00FF /* DSP2_ZM_START - [7:0] */ 4903#define WM5100_DSP2_ZM_START_1_SHIFT 0 /* DSP2_ZM_START - [7:0] */ 4904#define WM5100_DSP2_ZM_START_1_WIDTH 8 /* DSP2_ZM_START - [7:0] */ 4905 4906/* 4907 * R28673 (0x7001) - DSP2 ZM 1 4908 */ 4909#define WM5100_DSP2_ZM_START_MASK 0xFFFF /* DSP2_ZM_START - [15:0] */ 4910#define WM5100_DSP2_ZM_START_SHIFT 0 /* DSP2_ZM_START - [15:0] */ 4911#define WM5100_DSP2_ZM_START_WIDTH 16 /* DSP2_ZM_START - [15:0] */ 4912 4913/* 4914 * R28674 (0x7002) - DSP2 ZM 2 4915 */ 4916#define WM5100_DSP2_ZM_1_1_MASK 0x00FF /* DSP2_ZM_1 - [7:0] */ 4917#define WM5100_DSP2_ZM_1_1_SHIFT 0 /* DSP2_ZM_1 - [7:0] */ 4918#define WM5100_DSP2_ZM_1_1_WIDTH 8 /* DSP2_ZM_1 - [7:0] */ 4919 4920/* 4921 * R28675 (0x7003) - DSP2 ZM 3 4922 */ 4923#define WM5100_DSP2_ZM_1_MASK 0xFFFF /* DSP2_ZM_1 - [15:0] */ 4924#define WM5100_DSP2_ZM_1_SHIFT 0 /* DSP2_ZM_1 - [15:0] */ 4925#define WM5100_DSP2_ZM_1_WIDTH 16 /* DSP2_ZM_1 - [15:0] */ 4926 4927/* 4928 * R30716 (0x77FC) - DSP2 ZM 2044 4929 */ 4930#define WM5100_DSP2_ZM_1022_1_MASK 0x00FF /* DSP2_ZM_1022 - [7:0] */ 4931#define WM5100_DSP2_ZM_1022_1_SHIFT 0 /* DSP2_ZM_1022 - [7:0] */ 4932#define WM5100_DSP2_ZM_1022_1_WIDTH 8 /* DSP2_ZM_1022 - [7:0] */ 4933 4934/* 4935 * R30717 (0x77FD) - DSP2 ZM 2045 4936 */ 4937#define WM5100_DSP2_ZM_1022_MASK 0xFFFF /* DSP2_ZM_1022 - [15:0] */ 4938#define WM5100_DSP2_ZM_1022_SHIFT 0 /* DSP2_ZM_1022 - [15:0] */ 4939#define WM5100_DSP2_ZM_1022_WIDTH 16 /* DSP2_ZM_1022 - [15:0] */ 4940 4941/* 4942 * R30718 (0x77FE) - DSP2 ZM 2046 4943 */ 4944#define WM5100_DSP2_ZM_END_1_MASK 0x00FF /* DSP2_ZM_END - [7:0] */ 4945#define WM5100_DSP2_ZM_END_1_SHIFT 0 /* DSP2_ZM_END - [7:0] */ 4946#define WM5100_DSP2_ZM_END_1_WIDTH 8 /* DSP2_ZM_END - [7:0] */ 4947 4948/* 4949 * R30719 (0x77FF) - DSP2 ZM 2047 4950 */ 4951#define WM5100_DSP2_ZM_END_MASK 0xFFFF /* DSP2_ZM_END - [15:0] */ 4952#define WM5100_DSP2_ZM_END_SHIFT 0 /* DSP2_ZM_END - [15:0] */ 4953#define WM5100_DSP2_ZM_END_WIDTH 16 /* DSP2_ZM_END - [15:0] */ 4954 4955/* 4956 * R32768 (0x8000) - DSP3 DM 0 4957 */ 4958#define WM5100_DSP3_DM_START_1_MASK 0x00FF /* DSP3_DM_START - [7:0] */ 4959#define WM5100_DSP3_DM_START_1_SHIFT 0 /* DSP3_DM_START - [7:0] */ 4960#define WM5100_DSP3_DM_START_1_WIDTH 8 /* DSP3_DM_START - [7:0] */ 4961 4962/* 4963 * R32769 (0x8001) - DSP3 DM 1 4964 */ 4965#define WM5100_DSP3_DM_START_MASK 0xFFFF /* DSP3_DM_START - [15:0] */ 4966#define WM5100_DSP3_DM_START_SHIFT 0 /* DSP3_DM_START - [15:0] */ 4967#define WM5100_DSP3_DM_START_WIDTH 16 /* DSP3_DM_START - [15:0] */ 4968 4969/* 4970 * R32770 (0x8002) - DSP3 DM 2 4971 */ 4972#define WM5100_DSP3_DM_1_1_MASK 0x00FF /* DSP3_DM_1 - [7:0] */ 4973#define WM5100_DSP3_DM_1_1_SHIFT 0 /* DSP3_DM_1 - [7:0] */ 4974#define WM5100_DSP3_DM_1_1_WIDTH 8 /* DSP3_DM_1 - [7:0] */ 4975 4976/* 4977 * R32771 (0x8003) - DSP3 DM 3 4978 */ 4979#define WM5100_DSP3_DM_1_MASK 0xFFFF /* DSP3_DM_1 - [15:0] */ 4980#define WM5100_DSP3_DM_1_SHIFT 0 /* DSP3_DM_1 - [15:0] */ 4981#define WM5100_DSP3_DM_1_WIDTH 16 /* DSP3_DM_1 - [15:0] */ 4982 4983/* 4984 * R33276 (0x81FC) - DSP3 DM 508 4985 */ 4986#define WM5100_DSP3_DM_254_1_MASK 0x00FF /* DSP3_DM_254 - [7:0] */ 4987#define WM5100_DSP3_DM_254_1_SHIFT 0 /* DSP3_DM_254 - [7:0] */ 4988#define WM5100_DSP3_DM_254_1_WIDTH 8 /* DSP3_DM_254 - [7:0] */ 4989 4990/* 4991 * R33277 (0x81FD) - DSP3 DM 509 4992 */ 4993#define WM5100_DSP3_DM_254_MASK 0xFFFF /* DSP3_DM_254 - [15:0] */ 4994#define WM5100_DSP3_DM_254_SHIFT 0 /* DSP3_DM_254 - [15:0] */ 4995#define WM5100_DSP3_DM_254_WIDTH 16 /* DSP3_DM_254 - [15:0] */ 4996 4997/* 4998 * R33278 (0x81FE) - DSP3 DM 510 4999 */ 5000#define WM5100_DSP3_DM_END_1_MASK 0x00FF /* DSP3_DM_END - [7:0] */ 5001#define WM5100_DSP3_DM_END_1_SHIFT 0 /* DSP3_DM_END - [7:0] */ 5002#define WM5100_DSP3_DM_END_1_WIDTH 8 /* DSP3_DM_END - [7:0] */ 5003 5004/* 5005 * R33279 (0x81FF) - DSP3 DM 511 5006 */ 5007#define WM5100_DSP3_DM_END_MASK 0xFFFF /* DSP3_DM_END - [15:0] */ 5008#define WM5100_DSP3_DM_END_SHIFT 0 /* DSP3_DM_END - [15:0] */ 5009#define WM5100_DSP3_DM_END_WIDTH 16 /* DSP3_DM_END - [15:0] */ 5010 5011/* 5012 * R34816 (0x8800) - DSP3 PM 0 5013 */ 5014#define WM5100_DSP3_PM_START_2_MASK 0x00FF /* DSP3_PM_START - [7:0] */ 5015#define WM5100_DSP3_PM_START_2_SHIFT 0 /* DSP3_PM_START - [7:0] */ 5016#define WM5100_DSP3_PM_START_2_WIDTH 8 /* DSP3_PM_START - [7:0] */ 5017 5018/* 5019 * R34817 (0x8801) - DSP3 PM 1 5020 */ 5021#define WM5100_DSP3_PM_START_1_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5022#define WM5100_DSP3_PM_START_1_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5023#define WM5100_DSP3_PM_START_1_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5024 5025/* 5026 * R34818 (0x8802) - DSP3 PM 2 5027 */ 5028#define WM5100_DSP3_PM_START_MASK 0xFFFF /* DSP3_PM_START - [15:0] */ 5029#define WM5100_DSP3_PM_START_SHIFT 0 /* DSP3_PM_START - [15:0] */ 5030#define WM5100_DSP3_PM_START_WIDTH 16 /* DSP3_PM_START - [15:0] */ 5031 5032/* 5033 * R34819 (0x8803) - DSP3 PM 3 5034 */ 5035#define WM5100_DSP3_PM_1_2_MASK 0x00FF /* DSP3_PM_1 - [7:0] */ 5036#define WM5100_DSP3_PM_1_2_SHIFT 0 /* DSP3_PM_1 - [7:0] */ 5037#define WM5100_DSP3_PM_1_2_WIDTH 8 /* DSP3_PM_1 - [7:0] */ 5038 5039/* 5040 * R34820 (0x8804) - DSP3 PM 4 5041 */ 5042#define WM5100_DSP3_PM_1_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5043#define WM5100_DSP3_PM_1_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5044#define WM5100_DSP3_PM_1_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5045 5046/* 5047 * R34821 (0x8805) - DSP3 PM 5 5048 */ 5049#define WM5100_DSP3_PM_1_MASK 0xFFFF /* DSP3_PM_1 - [15:0] */ 5050#define WM5100_DSP3_PM_1_SHIFT 0 /* DSP3_PM_1 - [15:0] */ 5051#define WM5100_DSP3_PM_1_WIDTH 16 /* DSP3_PM_1 - [15:0] */ 5052 5053/* 5054 * R36346 (0x8DFA) - DSP3 PM 1530 5055 */ 5056#define WM5100_DSP3_PM_510_2_MASK 0x00FF /* DSP3_PM_510 - [7:0] */ 5057#define WM5100_DSP3_PM_510_2_SHIFT 0 /* DSP3_PM_510 - [7:0] */ 5058#define WM5100_DSP3_PM_510_2_WIDTH 8 /* DSP3_PM_510 - [7:0] */ 5059 5060/* 5061 * R36347 (0x8DFB) - DSP3 PM 1531 5062 */ 5063#define WM5100_DSP3_PM_510_1_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5064#define WM5100_DSP3_PM_510_1_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5065#define WM5100_DSP3_PM_510_1_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5066 5067/* 5068 * R36348 (0x8DFC) - DSP3 PM 1532 5069 */ 5070#define WM5100_DSP3_PM_510_MASK 0xFFFF /* DSP3_PM_510 - [15:0] */ 5071#define WM5100_DSP3_PM_510_SHIFT 0 /* DSP3_PM_510 - [15:0] */ 5072#define WM5100_DSP3_PM_510_WIDTH 16 /* DSP3_PM_510 - [15:0] */ 5073 5074/* 5075 * R36349 (0x8DFD) - DSP3 PM 1533 5076 */ 5077#define WM5100_DSP3_PM_END_2_MASK 0x00FF /* DSP3_PM_END - [7:0] */ 5078#define WM5100_DSP3_PM_END_2_SHIFT 0 /* DSP3_PM_END - [7:0] */ 5079#define WM5100_DSP3_PM_END_2_WIDTH 8 /* DSP3_PM_END - [7:0] */ 5080 5081/* 5082 * R36350 (0x8DFE) - DSP3 PM 1534 5083 */ 5084#define WM5100_DSP3_PM_END_1_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5085#define WM5100_DSP3_PM_END_1_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5086#define WM5100_DSP3_PM_END_1_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5087 5088/* 5089 * R36351 (0x8DFF) - DSP3 PM 1535 5090 */ 5091#define WM5100_DSP3_PM_END_MASK 0xFFFF /* DSP3_PM_END - [15:0] */ 5092#define WM5100_DSP3_PM_END_SHIFT 0 /* DSP3_PM_END - [15:0] */ 5093#define WM5100_DSP3_PM_END_WIDTH 16 /* DSP3_PM_END - [15:0] */ 5094 5095/* 5096 * R36864 (0x9000) - DSP3 ZM 0 5097 */ 5098#define WM5100_DSP3_ZM_START_1_MASK 0x00FF /* DSP3_ZM_START - [7:0] */ 5099#define WM5100_DSP3_ZM_START_1_SHIFT 0 /* DSP3_ZM_START - [7:0] */ 5100#define WM5100_DSP3_ZM_START_1_WIDTH 8 /* DSP3_ZM_START - [7:0] */ 5101 5102/* 5103 * R36865 (0x9001) - DSP3 ZM 1 5104 */ 5105#define WM5100_DSP3_ZM_START_MASK 0xFFFF /* DSP3_ZM_START - [15:0] */ 5106#define WM5100_DSP3_ZM_START_SHIFT 0 /* DSP3_ZM_START - [15:0] */ 5107#define WM5100_DSP3_ZM_START_WIDTH 16 /* DSP3_ZM_START - [15:0] */ 5108 5109/* 5110 * R36866 (0x9002) - DSP3 ZM 2 5111 */ 5112#define WM5100_DSP3_ZM_1_1_MASK 0x00FF /* DSP3_ZM_1 - [7:0] */ 5113#define WM5100_DSP3_ZM_1_1_SHIFT 0 /* DSP3_ZM_1 - [7:0] */ 5114#define WM5100_DSP3_ZM_1_1_WIDTH 8 /* DSP3_ZM_1 - [7:0] */ 5115 5116/* 5117 * R36867 (0x9003) - DSP3 ZM 3 5118 */ 5119#define WM5100_DSP3_ZM_1_MASK 0xFFFF /* DSP3_ZM_1 - [15:0] */ 5120#define WM5100_DSP3_ZM_1_SHIFT 0 /* DSP3_ZM_1 - [15:0] */ 5121#define WM5100_DSP3_ZM_1_WIDTH 16 /* DSP3_ZM_1 - [15:0] */ 5122 5123/* 5124 * R38908 (0x97FC) - DSP3 ZM 2044 5125 */ 5126#define WM5100_DSP3_ZM_1022_1_MASK 0x00FF /* DSP3_ZM_1022 - [7:0] */ 5127#define WM5100_DSP3_ZM_1022_1_SHIFT 0 /* DSP3_ZM_1022 - [7:0] */ 5128#define WM5100_DSP3_ZM_1022_1_WIDTH 8 /* DSP3_ZM_1022 - [7:0] */ 5129 5130/* 5131 * R38909 (0x97FD) - DSP3 ZM 2045 5132 */ 5133#define WM5100_DSP3_ZM_1022_MASK 0xFFFF /* DSP3_ZM_1022 - [15:0] */ 5134#define WM5100_DSP3_ZM_1022_SHIFT 0 /* DSP3_ZM_1022 - [15:0] */ 5135#define WM5100_DSP3_ZM_1022_WIDTH 16 /* DSP3_ZM_1022 - [15:0] */ 5136 5137/* 5138 * R38910 (0x97FE) - DSP3 ZM 2046 5139 */ 5140#define WM5100_DSP3_ZM_END_1_MASK 0x00FF /* DSP3_ZM_END - [7:0] */ 5141#define WM5100_DSP3_ZM_END_1_SHIFT 0 /* DSP3_ZM_END - [7:0] */ 5142#define WM5100_DSP3_ZM_END_1_WIDTH 8 /* DSP3_ZM_END - [7:0] */ 5143 5144/* 5145 * R38911 (0x97FF) - DSP3 ZM 2047 5146 */ 5147#define WM5100_DSP3_ZM_END_MASK 0xFFFF /* DSP3_ZM_END - [15:0] */ 5148#define WM5100_DSP3_ZM_END_SHIFT 0 /* DSP3_ZM_END - [15:0] */ 5149#define WM5100_DSP3_ZM_END_WIDTH 16 /* DSP3_ZM_END - [15:0] */ 5150 5151bool wm5100_readable_register(struct device *dev, unsigned int reg); 5152bool wm5100_volatile_register(struct device *dev, unsigned int reg); 5153 5154extern struct reg_default wm5100_reg_defaults[WM5100_REGISTER_COUNT]; 5155 5156#endif