tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
fork
Configure Feed
Select the types of activity you want to include in your feed.
1/*
2 * include/linux/amba/pl022.h
3 *
4 * Copyright (C) 2008-2009 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 *
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
25#ifndef _SSP_PL022_H
26#define _SSP_PL022_H
27
28/**
29 * whether SSP is in loopback mode or not
30 */
31enum ssp_loopback {
32 LOOPBACK_DISABLED,
33 LOOPBACK_ENABLED
34};
35
36/**
37 * enum ssp_interface - interfaces allowed for this SSP Controller
38 * @SSP_INTERFACE_MOTOROLA_SPI: Motorola Interface
39 * @SSP_INTERFACE_TI_SYNC_SERIAL: Texas Instrument Synchronous Serial
40 * interface
41 * @SSP_INTERFACE_NATIONAL_MICROWIRE: National Semiconductor Microwire
42 * interface
43 * @SSP_INTERFACE_UNIDIRECTIONAL: Unidirectional interface (STn8810
44 * &STn8815 only)
45 */
46enum ssp_interface {
47 SSP_INTERFACE_MOTOROLA_SPI,
48 SSP_INTERFACE_TI_SYNC_SERIAL,
49 SSP_INTERFACE_NATIONAL_MICROWIRE,
50 SSP_INTERFACE_UNIDIRECTIONAL
51};
52
53/**
54 * enum ssp_hierarchy - whether SSP is configured as Master or Slave
55 */
56enum ssp_hierarchy {
57 SSP_MASTER,
58 SSP_SLAVE
59};
60
61/**
62 * enum ssp_clock_params - clock parameters, to set SSP clock at a
63 * desired freq
64 */
65struct ssp_clock_params {
66 u8 cpsdvsr; /* value from 2 to 254 (even only!) */
67 u8 scr; /* value from 0 to 255 */
68};
69
70/**
71 * enum ssp_rx_endian - endianess of Rx FIFO Data
72 * this feature is only available in ST versionf of PL022
73 */
74enum ssp_rx_endian {
75 SSP_RX_MSB,
76 SSP_RX_LSB
77};
78
79/**
80 * enum ssp_tx_endian - endianess of Tx FIFO Data
81 */
82enum ssp_tx_endian {
83 SSP_TX_MSB,
84 SSP_TX_LSB
85};
86
87/**
88 * enum ssp_data_size - number of bits in one data element
89 */
90enum ssp_data_size {
91 SSP_DATA_BITS_4 = 0x03, SSP_DATA_BITS_5, SSP_DATA_BITS_6,
92 SSP_DATA_BITS_7, SSP_DATA_BITS_8, SSP_DATA_BITS_9,
93 SSP_DATA_BITS_10, SSP_DATA_BITS_11, SSP_DATA_BITS_12,
94 SSP_DATA_BITS_13, SSP_DATA_BITS_14, SSP_DATA_BITS_15,
95 SSP_DATA_BITS_16, SSP_DATA_BITS_17, SSP_DATA_BITS_18,
96 SSP_DATA_BITS_19, SSP_DATA_BITS_20, SSP_DATA_BITS_21,
97 SSP_DATA_BITS_22, SSP_DATA_BITS_23, SSP_DATA_BITS_24,
98 SSP_DATA_BITS_25, SSP_DATA_BITS_26, SSP_DATA_BITS_27,
99 SSP_DATA_BITS_28, SSP_DATA_BITS_29, SSP_DATA_BITS_30,
100 SSP_DATA_BITS_31, SSP_DATA_BITS_32
101};
102
103/**
104 * enum ssp_mode - SSP mode of operation (Communication modes)
105 */
106enum ssp_mode {
107 INTERRUPT_TRANSFER,
108 POLLING_TRANSFER,
109 DMA_TRANSFER
110};
111
112/**
113 * enum ssp_rx_level_trig - receive FIFO watermark level which triggers
114 * IT: Interrupt fires when _N_ or more elements in RX FIFO.
115 */
116enum ssp_rx_level_trig {
117 SSP_RX_1_OR_MORE_ELEM,
118 SSP_RX_4_OR_MORE_ELEM,
119 SSP_RX_8_OR_MORE_ELEM,
120 SSP_RX_16_OR_MORE_ELEM,
121 SSP_RX_32_OR_MORE_ELEM
122};
123
124/**
125 * Transmit FIFO watermark level which triggers (IT Interrupt fires
126 * when _N_ or more empty locations in TX FIFO)
127 */
128enum ssp_tx_level_trig {
129 SSP_TX_1_OR_MORE_EMPTY_LOC,
130 SSP_TX_4_OR_MORE_EMPTY_LOC,
131 SSP_TX_8_OR_MORE_EMPTY_LOC,
132 SSP_TX_16_OR_MORE_EMPTY_LOC,
133 SSP_TX_32_OR_MORE_EMPTY_LOC
134};
135
136/**
137 * enum SPI Clock Phase - clock phase (Motorola SPI interface only)
138 * @SSP_CLK_FIRST_EDGE: Receive data on first edge transition (actual direction depends on polarity)
139 * @SSP_CLK_SECOND_EDGE: Receive data on second edge transition (actual direction depends on polarity)
140 */
141enum ssp_spi_clk_phase {
142 SSP_CLK_FIRST_EDGE,
143 SSP_CLK_SECOND_EDGE
144};
145
146/**
147 * enum SPI Clock Polarity - clock polarity (Motorola SPI interface only)
148 * @SSP_CLK_POL_IDLE_LOW: Low inactive level
149 * @SSP_CLK_POL_IDLE_HIGH: High inactive level
150 */
151enum ssp_spi_clk_pol {
152 SSP_CLK_POL_IDLE_LOW,
153 SSP_CLK_POL_IDLE_HIGH
154};
155
156/**
157 * Microwire Conrol Lengths Command size in microwire format
158 */
159enum ssp_microwire_ctrl_len {
160 SSP_BITS_4 = 0x03, SSP_BITS_5, SSP_BITS_6,
161 SSP_BITS_7, SSP_BITS_8, SSP_BITS_9,
162 SSP_BITS_10, SSP_BITS_11, SSP_BITS_12,
163 SSP_BITS_13, SSP_BITS_14, SSP_BITS_15,
164 SSP_BITS_16, SSP_BITS_17, SSP_BITS_18,
165 SSP_BITS_19, SSP_BITS_20, SSP_BITS_21,
166 SSP_BITS_22, SSP_BITS_23, SSP_BITS_24,
167 SSP_BITS_25, SSP_BITS_26, SSP_BITS_27,
168 SSP_BITS_28, SSP_BITS_29, SSP_BITS_30,
169 SSP_BITS_31, SSP_BITS_32
170};
171
172/**
173 * enum Microwire Wait State
174 * @SSP_MWIRE_WAIT_ZERO: No wait state inserted after last command bit
175 * @SSP_MWIRE_WAIT_ONE: One wait state inserted after last command bit
176 */
177enum ssp_microwire_wait_state {
178 SSP_MWIRE_WAIT_ZERO,
179 SSP_MWIRE_WAIT_ONE
180};
181
182/**
183 * enum ssp_duplex - whether Full/Half Duplex on microwire, only
184 * available in the ST Micro variant.
185 * @SSP_MICROWIRE_CHANNEL_FULL_DUPLEX: SSPTXD becomes bi-directional,
186 * SSPRXD not used
187 * @SSP_MICROWIRE_CHANNEL_HALF_DUPLEX: SSPTXD is an output, SSPRXD is
188 * an input.
189 */
190enum ssp_duplex {
191 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
192 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
193};
194
195/**
196 * enum ssp_clkdelay - an optional clock delay on the feedback clock
197 * only available in the ST Micro PL023 variant.
198 * @SSP_FEEDBACK_CLK_DELAY_NONE: no delay, the data coming in from the
199 * slave is sampled directly
200 * @SSP_FEEDBACK_CLK_DELAY_1T: the incoming slave data is sampled with
201 * a delay of T-dt
202 * @SSP_FEEDBACK_CLK_DELAY_2T: dito with a delay if 2T-dt
203 * @SSP_FEEDBACK_CLK_DELAY_3T: dito with a delay if 3T-dt
204 * @SSP_FEEDBACK_CLK_DELAY_4T: dito with a delay if 4T-dt
205 * @SSP_FEEDBACK_CLK_DELAY_5T: dito with a delay if 5T-dt
206 * @SSP_FEEDBACK_CLK_DELAY_6T: dito with a delay if 6T-dt
207 * @SSP_FEEDBACK_CLK_DELAY_7T: dito with a delay if 7T-dt
208 */
209enum ssp_clkdelay {
210 SSP_FEEDBACK_CLK_DELAY_NONE,
211 SSP_FEEDBACK_CLK_DELAY_1T,
212 SSP_FEEDBACK_CLK_DELAY_2T,
213 SSP_FEEDBACK_CLK_DELAY_3T,
214 SSP_FEEDBACK_CLK_DELAY_4T,
215 SSP_FEEDBACK_CLK_DELAY_5T,
216 SSP_FEEDBACK_CLK_DELAY_6T,
217 SSP_FEEDBACK_CLK_DELAY_7T
218};
219
220/**
221 * CHIP select/deselect commands
222 */
223enum ssp_chip_select {
224 SSP_CHIP_SELECT,
225 SSP_CHIP_DESELECT
226};
227
228
229struct dma_chan;
230/**
231 * struct pl022_ssp_master - device.platform_data for SPI controller devices.
232 * @num_chipselect: chipselects are used to distinguish individual
233 * SPI slaves, and are numbered from zero to num_chipselects - 1.
234 * each slave has a chipselect signal, but it's common that not
235 * every chipselect is connected to a slave.
236 * @enable_dma: if true enables DMA driven transfers.
237 * @dma_rx_param: parameter to locate an RX DMA channel.
238 * @dma_tx_param: parameter to locate a TX DMA channel.
239 * @autosuspend_delay: delay in ms following transfer completion before the
240 * runtime power management system suspends the device. A setting of 0
241 * indicates no delay and the device will be suspended immediately.
242 * @rt: indicates the controller should run the message pump with realtime
243 * priority to minimise the transfer latency on the bus.
244 */
245struct pl022_ssp_controller {
246 u16 bus_id;
247 u8 num_chipselect;
248 u8 enable_dma:1;
249 bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
250 void *dma_rx_param;
251 void *dma_tx_param;
252 int autosuspend_delay;
253 bool rt;
254};
255
256/**
257 * struct ssp_config_chip - spi_board_info.controller_data for SPI
258 * slave devices, copied to spi_device.controller_data.
259 *
260 * @lbm: used for test purpose to internally connect RX and TX
261 * @iface: Interface type(Motorola, TI, Microwire, Universal)
262 * @hierarchy: sets whether interface is master or slave
263 * @slave_tx_disable: SSPTXD is disconnected (in slave mode only)
264 * @clk_freq: Tune freq parameters of SSP(when in master mode)
265 * @endian_rx: Endianess of Data in Rx FIFO
266 * @endian_tx: Endianess of Data in Tx FIFO
267 * @data_size: Width of data element(4 to 32 bits)
268 * @com_mode: communication mode: polling, Interrupt or DMA
269 * @rx_lev_trig: Rx FIFO watermark level (for IT & DMA mode)
270 * @tx_lev_trig: Tx FIFO watermark level (for IT & DMA mode)
271 * @clk_phase: Motorola SPI interface Clock phase
272 * @clk_pol: Motorola SPI interface Clock polarity
273 * @ctrl_len: Microwire interface: Control length
274 * @wait_state: Microwire interface: Wait state
275 * @duplex: Microwire interface: Full/Half duplex
276 * @clkdelay: on the PL023 variant, the delay in feeback clock cycles
277 * before sampling the incoming line
278 * @cs_control: function pointer to board-specific function to
279 * assert/deassert I/O port to control HW generation of devices chip-select.
280 * @dma_xfer_type: Type of DMA xfer (Mem-to-periph or Periph-to-Periph)
281 * @dma_config: DMA configuration for SSP controller and peripheral
282 */
283struct pl022_config_chip {
284 enum ssp_interface iface;
285 enum ssp_hierarchy hierarchy;
286 bool slave_tx_disable;
287 struct ssp_clock_params clk_freq;
288 enum ssp_mode com_mode;
289 enum ssp_rx_level_trig rx_lev_trig;
290 enum ssp_tx_level_trig tx_lev_trig;
291 enum ssp_microwire_ctrl_len ctrl_len;
292 enum ssp_microwire_wait_state wait_state;
293 enum ssp_duplex duplex;
294 enum ssp_clkdelay clkdelay;
295 void (*cs_control) (u32 control);
296};
297
298#endif /* _SSP_PL022_H */