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1/*
2 * linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
3 *
4 * Copyright (C) 2005 ARM Ltd
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * pl08x information required by platform code
12 *
13 * Please credit ARM.com
14 * Documentation: ARM DDI 0196D
15 */
16
17#ifndef AMBA_PL08X_H
18#define AMBA_PL08X_H
19
20/* We need sizes of structs from this header */
21#include <linux/dmaengine.h>
22#include <linux/interrupt.h>
23
24struct pl08x_lli;
25struct pl08x_driver_data;
26
27/* Bitmasks for selecting AHB ports for DMA transfers */
28enum {
29 PL08X_AHB1 = (1 << 0),
30 PL08X_AHB2 = (1 << 1)
31};
32
33/**
34 * struct pl08x_channel_data - data structure to pass info between
35 * platform and PL08x driver regarding channel configuration
36 * @bus_id: name of this device channel, not just a device name since
37 * devices may have more than one channel e.g. "foo_tx"
38 * @min_signal: the minimum DMA signal number to be muxed in for this
39 * channel (for platforms supporting muxed signals). If you have
40 * static assignments, make sure this is set to the assigned signal
41 * number, PL08x have 16 possible signals in number 0 thru 15 so
42 * when these are not enough they often get muxed (in hardware)
43 * disabling simultaneous use of the same channel for two devices.
44 * @max_signal: the maximum DMA signal number to be muxed in for
45 * the channel. Set to the same as min_signal for
46 * devices with static assignments
47 * @muxval: a number usually used to poke into some mux regiser to
48 * mux in the signal to this channel
49 * @cctl_opt: default options for the channel control register
50 * @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
51 * channels. Fill with 'true' if peripheral should be flow controller. Direction
52 * will be selected at Runtime.
53 * @addr: source/target address in physical memory for this DMA channel,
54 * can be the address of a FIFO register for burst requests for example.
55 * This can be left undefined if the PrimeCell API is used for configuring
56 * this.
57 * @circular_buffer: whether the buffer passed in is circular and
58 * shall simply be looped round round (like a record baby round
59 * round round round)
60 * @single: the device connected to this channel will request single DMA
61 * transfers, not bursts. (Bursts are default.)
62 * @periph_buses: the device connected to this channel is accessible via
63 * these buses (use PL08X_AHB1 | PL08X_AHB2).
64 */
65struct pl08x_channel_data {
66 char *bus_id;
67 int min_signal;
68 int max_signal;
69 u32 muxval;
70 u32 cctl;
71 bool device_fc;
72 dma_addr_t addr;
73 bool circular_buffer;
74 bool single;
75 u8 periph_buses;
76};
77
78/**
79 * Struct pl08x_bus_data - information of source or destination
80 * busses for a transfer
81 * @addr: current address
82 * @maxwidth: the maximum width of a transfer on this bus
83 * @buswidth: the width of this bus in bytes: 1, 2 or 4
84 */
85struct pl08x_bus_data {
86 dma_addr_t addr;
87 u8 maxwidth;
88 u8 buswidth;
89};
90
91/**
92 * struct pl08x_phy_chan - holder for the physical channels
93 * @id: physical index to this channel
94 * @lock: a lock to use when altering an instance of this struct
95 * @signal: the physical signal (aka channel) serving this physical channel
96 * right now
97 * @serving: the virtual channel currently being served by this physical
98 * channel
99 */
100struct pl08x_phy_chan {
101 unsigned int id;
102 void __iomem *base;
103 spinlock_t lock;
104 int signal;
105 struct pl08x_dma_chan *serving;
106};
107
108/**
109 * struct pl08x_sg - structure containing data per sg
110 * @src_addr: src address of sg
111 * @dst_addr: dst address of sg
112 * @len: transfer len in bytes
113 * @node: node for txd's dsg_list
114 */
115struct pl08x_sg {
116 dma_addr_t src_addr;
117 dma_addr_t dst_addr;
118 size_t len;
119 struct list_head node;
120};
121
122/**
123 * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
124 * @tx: async tx descriptor
125 * @node: node for txd list for channels
126 * @dsg_list: list of children sg's
127 * @direction: direction of transfer
128 * @llis_bus: DMA memory address (physical) start for the LLIs
129 * @llis_va: virtual memory address start for the LLIs
130 * @cctl: control reg values for current txd
131 * @ccfg: config reg values for current txd
132 */
133struct pl08x_txd {
134 struct dma_async_tx_descriptor tx;
135 struct list_head node;
136 struct list_head dsg_list;
137 enum dma_transfer_direction direction;
138 dma_addr_t llis_bus;
139 struct pl08x_lli *llis_va;
140 /* Default cctl value for LLIs */
141 u32 cctl;
142 /*
143 * Settings to be put into the physical channel when we
144 * trigger this txd. Other registers are in llis_va[0].
145 */
146 u32 ccfg;
147};
148
149/**
150 * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
151 * states
152 * @PL08X_CHAN_IDLE: the channel is idle
153 * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
154 * channel and is running a transfer on it
155 * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
156 * channel, but the transfer is currently paused
157 * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
158 * channel to become available (only pertains to memcpy channels)
159 */
160enum pl08x_dma_chan_state {
161 PL08X_CHAN_IDLE,
162 PL08X_CHAN_RUNNING,
163 PL08X_CHAN_PAUSED,
164 PL08X_CHAN_WAITING,
165};
166
167/**
168 * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
169 * @chan: wrappped abstract channel
170 * @phychan: the physical channel utilized by this channel, if there is one
171 * @phychan_hold: if non-zero, hold on to the physical channel even if we
172 * have no pending entries
173 * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
174 * @name: name of channel
175 * @cd: channel platform data
176 * @runtime_addr: address for RX/TX according to the runtime config
177 * @runtime_direction: current direction of this channel according to
178 * runtime config
179 * @lc: last completed transaction on this channel
180 * @pend_list: queued transactions pending on this channel
181 * @at: active transaction on this channel
182 * @lock: a lock for this channel data
183 * @host: a pointer to the host (internal use)
184 * @state: whether the channel is idle, paused, running etc
185 * @slave: whether this channel is a device (slave) or for memcpy
186 * @waiting: a TX descriptor on this channel which is waiting for a physical
187 * channel to become available
188 */
189struct pl08x_dma_chan {
190 struct dma_chan chan;
191 struct pl08x_phy_chan *phychan;
192 int phychan_hold;
193 struct tasklet_struct tasklet;
194 char *name;
195 const struct pl08x_channel_data *cd;
196 dma_addr_t src_addr;
197 dma_addr_t dst_addr;
198 u32 src_cctl;
199 u32 dst_cctl;
200 enum dma_transfer_direction runtime_direction;
201 dma_cookie_t lc;
202 struct list_head pend_list;
203 struct pl08x_txd *at;
204 spinlock_t lock;
205 struct pl08x_driver_data *host;
206 enum pl08x_dma_chan_state state;
207 bool slave;
208 struct pl08x_txd *waiting;
209};
210
211/**
212 * struct pl08x_platform_data - the platform configuration for the PL08x
213 * PrimeCells.
214 * @slave_channels: the channels defined for the different devices on the
215 * platform, all inclusive, including multiplexed channels. The available
216 * physical channels will be multiplexed around these signals as they are
217 * requested, just enumerate all possible channels.
218 * @get_signal: request a physical signal to be used for a DMA transfer
219 * immediately: if there is some multiplexing or similar blocking the use
220 * of the channel the transfer can be denied by returning less than zero,
221 * else it returns the allocated signal number
222 * @put_signal: indicate to the platform that this physical signal is not
223 * running any DMA transfer and multiplexing can be recycled
224 * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
225 * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
226 */
227struct pl08x_platform_data {
228 const struct pl08x_channel_data *slave_channels;
229 unsigned int num_slave_channels;
230 struct pl08x_channel_data memcpy_channel;
231 int (*get_signal)(struct pl08x_dma_chan *);
232 void (*put_signal)(struct pl08x_dma_chan *);
233 u8 lli_buses;
234 u8 mem_buses;
235};
236
237#ifdef CONFIG_AMBA_PL08X
238bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
239#else
240static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
241{
242 return false;
243}
244#endif
245
246#endif /* AMBA_PL08X_H */