tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * GPIOs on MPC512x/8349/8572/8610 and compatible
3 *
4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_gpio.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/irq.h>
20
21#define MPC8XXX_GPIO_PINS 32
22
23#define GPIO_DIR 0x00
24#define GPIO_ODR 0x04
25#define GPIO_DAT 0x08
26#define GPIO_IER 0x0c
27#define GPIO_IMR 0x10
28#define GPIO_ICR 0x14
29#define GPIO_ICR2 0x18
30
31struct mpc8xxx_gpio_chip {
32 struct of_mm_gpio_chip mm_gc;
33 spinlock_t lock;
34
35 /*
36 * shadowed data register to be able to clear/set output pins in
37 * open drain mode safely
38 */
39 u32 data;
40 struct irq_host *irq;
41 void *of_dev_id_data;
42};
43
44static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
45{
46 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
47}
48
49static inline struct mpc8xxx_gpio_chip *
50to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
51{
52 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
53}
54
55static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
56{
57 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
58
59 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
60}
61
62/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
63 * defined as output cannot be determined by reading GPDAT register,
64 * so we use shadow data register instead. The status of input pins
65 * is determined by reading GPDAT register.
66 */
67static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
68{
69 u32 val;
70 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
71 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
72
73 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR);
74
75 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio);
76}
77
78static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
79{
80 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
81
82 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
83}
84
85static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
86{
87 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
89 unsigned long flags;
90
91 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
92
93 if (val)
94 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
95 else
96 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
97
98 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
99
100 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
101}
102
103static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
104{
105 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
106 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
107 unsigned long flags;
108
109 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
110
111 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
112
113 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
114
115 return 0;
116}
117
118static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
119{
120 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
121 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
122 unsigned long flags;
123
124 mpc8xxx_gpio_set(gc, gpio, val);
125
126 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
127
128 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
129
130 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
131
132 return 0;
133}
134
135static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136{
137 /* GPIO 28..31 are input only on MPC5121 */
138 if (gpio >= 28)
139 return -EINVAL;
140
141 return mpc8xxx_gpio_dir_out(gc, gpio, val);
142}
143
144static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
145{
146 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
147 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
148
149 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
150 return irq_create_mapping(mpc8xxx_gc->irq, offset);
151 else
152 return -ENXIO;
153}
154
155static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
156{
157 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
158 struct irq_chip *chip = irq_desc_get_chip(desc);
159 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
160 unsigned int mask;
161
162 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
163 if (mask)
164 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
165 32 - ffs(mask)));
166 chip->irq_eoi(&desc->irq_data);
167}
168
169static void mpc8xxx_irq_unmask(struct irq_data *d)
170{
171 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
172 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
173 unsigned long flags;
174
175 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
176
177 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
178
179 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
180}
181
182static void mpc8xxx_irq_mask(struct irq_data *d)
183{
184 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
185 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
186 unsigned long flags;
187
188 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
189
190 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
191
192 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
193}
194
195static void mpc8xxx_irq_ack(struct irq_data *d)
196{
197 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
198 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
199
200 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
201}
202
203static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
204{
205 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
206 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
207 unsigned long flags;
208
209 switch (flow_type) {
210 case IRQ_TYPE_EDGE_FALLING:
211 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
212 setbits32(mm->regs + GPIO_ICR,
213 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
214 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
215 break;
216
217 case IRQ_TYPE_EDGE_BOTH:
218 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
219 clrbits32(mm->regs + GPIO_ICR,
220 mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
221 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
222 break;
223
224 default:
225 return -EINVAL;
226 }
227
228 return 0;
229}
230
231static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
232{
233 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
234 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
235 unsigned long gpio = irqd_to_hwirq(d);
236 void __iomem *reg;
237 unsigned int shift;
238 unsigned long flags;
239
240 if (gpio < 16) {
241 reg = mm->regs + GPIO_ICR;
242 shift = (15 - gpio) * 2;
243 } else {
244 reg = mm->regs + GPIO_ICR2;
245 shift = (15 - (gpio % 16)) * 2;
246 }
247
248 switch (flow_type) {
249 case IRQ_TYPE_EDGE_FALLING:
250 case IRQ_TYPE_LEVEL_LOW:
251 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
252 clrsetbits_be32(reg, 3 << shift, 2 << shift);
253 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
254 break;
255
256 case IRQ_TYPE_EDGE_RISING:
257 case IRQ_TYPE_LEVEL_HIGH:
258 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
259 clrsetbits_be32(reg, 3 << shift, 1 << shift);
260 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
261 break;
262
263 case IRQ_TYPE_EDGE_BOTH:
264 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
265 clrbits32(reg, 3 << shift);
266 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
267 break;
268
269 default:
270 return -EINVAL;
271 }
272
273 return 0;
274}
275
276static struct irq_chip mpc8xxx_irq_chip = {
277 .name = "mpc8xxx-gpio",
278 .irq_unmask = mpc8xxx_irq_unmask,
279 .irq_mask = mpc8xxx_irq_mask,
280 .irq_ack = mpc8xxx_irq_ack,
281 .irq_set_type = mpc8xxx_irq_set_type,
282};
283
284static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
285 irq_hw_number_t hw)
286{
287 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
288
289 if (mpc8xxx_gc->of_dev_id_data)
290 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
291
292 irq_set_chip_data(virq, h->host_data);
293 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
294 irq_set_irq_type(virq, IRQ_TYPE_NONE);
295
296 return 0;
297}
298
299static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
300 const u32 *intspec, unsigned int intsize,
301 irq_hw_number_t *out_hwirq,
302 unsigned int *out_flags)
303
304{
305 /* interrupt sense values coming from the device tree equal either
306 * EDGE_FALLING or EDGE_BOTH
307 */
308 *out_hwirq = intspec[0];
309 *out_flags = intspec[1];
310
311 return 0;
312}
313
314static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
315 .map = mpc8xxx_gpio_irq_map,
316 .xlate = mpc8xxx_gpio_irq_xlate,
317};
318
319static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
320 { .compatible = "fsl,mpc8349-gpio", },
321 { .compatible = "fsl,mpc8572-gpio", },
322 { .compatible = "fsl,mpc8610-gpio", },
323 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
324 { .compatible = "fsl,pq3-gpio", },
325 { .compatible = "fsl,qoriq-gpio", },
326 {}
327};
328
329static void __init mpc8xxx_add_controller(struct device_node *np)
330{
331 struct mpc8xxx_gpio_chip *mpc8xxx_gc;
332 struct of_mm_gpio_chip *mm_gc;
333 struct gpio_chip *gc;
334 const struct of_device_id *id;
335 unsigned hwirq;
336 int ret;
337
338 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
339 if (!mpc8xxx_gc) {
340 ret = -ENOMEM;
341 goto err;
342 }
343
344 spin_lock_init(&mpc8xxx_gc->lock);
345
346 mm_gc = &mpc8xxx_gc->mm_gc;
347 gc = &mm_gc->gc;
348
349 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
350 gc->ngpio = MPC8XXX_GPIO_PINS;
351 gc->direction_input = mpc8xxx_gpio_dir_in;
352 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
353 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
354 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
355 mpc8572_gpio_get : mpc8xxx_gpio_get;
356 gc->set = mpc8xxx_gpio_set;
357 gc->to_irq = mpc8xxx_gpio_to_irq;
358
359 ret = of_mm_gpiochip_add(np, mm_gc);
360 if (ret)
361 goto err;
362
363 hwirq = irq_of_parse_and_map(np, 0);
364 if (hwirq == NO_IRQ)
365 goto skip_irq;
366
367 mpc8xxx_gc->irq =
368 irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
369 &mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
370 if (!mpc8xxx_gc->irq)
371 goto skip_irq;
372
373 id = of_match_node(mpc8xxx_gpio_ids, np);
374 if (id)
375 mpc8xxx_gc->of_dev_id_data = id->data;
376
377 mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
378
379 /* ack and mask all irqs */
380 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
381 out_be32(mm_gc->regs + GPIO_IMR, 0);
382
383 irq_set_handler_data(hwirq, mpc8xxx_gc);
384 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
385
386skip_irq:
387 return;
388
389err:
390 pr_err("%s: registration failed with status %d\n",
391 np->full_name, ret);
392 kfree(mpc8xxx_gc);
393
394 return;
395}
396
397static int __init mpc8xxx_add_gpiochips(void)
398{
399 struct device_node *np;
400
401 for_each_matching_node(np, mpc8xxx_gpio_ids)
402 mpc8xxx_add_controller(np);
403
404 return 0;
405}
406arch_initcall(mpc8xxx_add_gpiochips);