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1/*
2 * arch/arm/include/asm/assembler.h
3 *
4 * Copyright (C) 1996-2000 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains arm architecture specific defines
11 * for the different processors.
12 *
13 * Do not include any C declarations in this file - it is included by
14 * assembler source.
15 */
16#ifndef __ASM_ASSEMBLER_H__
17#define __ASM_ASSEMBLER_H__
18
19#ifndef __ASSEMBLY__
20#error "Only include this from assembly code"
21#endif
22
23#include <asm/ptrace.h>
24#include <asm/domain.h>
25
26/*
27 * Endian independent macros for shifting bytes within registers.
28 */
29#ifndef __ARMEB__
30#define pull lsr
31#define push lsl
32#define get_byte_0 lsl #0
33#define get_byte_1 lsr #8
34#define get_byte_2 lsr #16
35#define get_byte_3 lsr #24
36#define put_byte_0 lsl #0
37#define put_byte_1 lsl #8
38#define put_byte_2 lsl #16
39#define put_byte_3 lsl #24
40#else
41#define pull lsl
42#define push lsr
43#define get_byte_0 lsr #24
44#define get_byte_1 lsr #16
45#define get_byte_2 lsr #8
46#define get_byte_3 lsl #0
47#define put_byte_0 lsl #24
48#define put_byte_1 lsl #16
49#define put_byte_2 lsl #8
50#define put_byte_3 lsl #0
51#endif
52
53/*
54 * Data preload for architectures that support it
55 */
56#if __LINUX_ARM_ARCH__ >= 5
57#define PLD(code...) code
58#else
59#define PLD(code...)
60#endif
61
62/*
63 * This can be used to enable code to cacheline align the destination
64 * pointer when bulk writing to memory. Experiments on StrongARM and
65 * XScale didn't show this a worthwhile thing to do when the cache is not
66 * set to write-allocate (this would need further testing on XScale when WA
67 * is used).
68 *
69 * On Feroceon there is much to gain however, regardless of cache mode.
70 */
71#ifdef CONFIG_CPU_FEROCEON
72#define CALGN(code...) code
73#else
74#define CALGN(code...)
75#endif
76
77/*
78 * Enable and disable interrupts
79 */
80#if __LINUX_ARM_ARCH__ >= 6
81 .macro disable_irq_notrace
82 cpsid i
83 .endm
84
85 .macro enable_irq_notrace
86 cpsie i
87 .endm
88#else
89 .macro disable_irq_notrace
90 msr cpsr_c, #PSR_I_BIT | SVC_MODE
91 .endm
92
93 .macro enable_irq_notrace
94 msr cpsr_c, #SVC_MODE
95 .endm
96#endif
97
98 .macro asm_trace_hardirqs_off
99#if defined(CONFIG_TRACE_IRQFLAGS)
100 stmdb sp!, {r0-r3, ip, lr}
101 bl trace_hardirqs_off
102 ldmia sp!, {r0-r3, ip, lr}
103#endif
104 .endm
105
106 .macro asm_trace_hardirqs_on_cond, cond
107#if defined(CONFIG_TRACE_IRQFLAGS)
108 /*
109 * actually the registers should be pushed and pop'd conditionally, but
110 * after bl the flags are certainly clobbered
111 */
112 stmdb sp!, {r0-r3, ip, lr}
113 bl\cond trace_hardirqs_on
114 ldmia sp!, {r0-r3, ip, lr}
115#endif
116 .endm
117
118 .macro asm_trace_hardirqs_on
119 asm_trace_hardirqs_on_cond al
120 .endm
121
122 .macro disable_irq
123 disable_irq_notrace
124 asm_trace_hardirqs_off
125 .endm
126
127 .macro enable_irq
128 asm_trace_hardirqs_on
129 enable_irq_notrace
130 .endm
131/*
132 * Save the current IRQ state and disable IRQs. Note that this macro
133 * assumes FIQs are enabled, and that the processor is in SVC mode.
134 */
135 .macro save_and_disable_irqs, oldcpsr
136 mrs \oldcpsr, cpsr
137 disable_irq
138 .endm
139
140/*
141 * Restore interrupt state previously stored in a register. We don't
142 * guarantee that this will preserve the flags.
143 */
144 .macro restore_irqs_notrace, oldcpsr
145 msr cpsr_c, \oldcpsr
146 .endm
147
148 .macro restore_irqs, oldcpsr
149 tst \oldcpsr, #PSR_I_BIT
150 asm_trace_hardirqs_on_cond eq
151 restore_irqs_notrace \oldcpsr
152 .endm
153
154#define USER(x...) \
1559999: x; \
156 .pushsection __ex_table,"a"; \
157 .align 3; \
158 .long 9999b,9001f; \
159 .popsection
160
161#ifdef CONFIG_SMP
162#define ALT_SMP(instr...) \
1639998: instr
164/*
165 * Note: if you get assembler errors from ALT_UP() when building with
166 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
167 * ALT_SMP( W(instr) ... )
168 */
169#define ALT_UP(instr...) \
170 .pushsection ".alt.smp.init", "a" ;\
171 .long 9998b ;\
1729997: instr ;\
173 .if . - 9997b != 4 ;\
174 .error "ALT_UP() content must assemble to exactly 4 bytes";\
175 .endif ;\
176 .popsection
177#define ALT_UP_B(label) \
178 .equ up_b_offset, label - 9998b ;\
179 .pushsection ".alt.smp.init", "a" ;\
180 .long 9998b ;\
181 W(b) . + up_b_offset ;\
182 .popsection
183#else
184#define ALT_SMP(instr...)
185#define ALT_UP(instr...) instr
186#define ALT_UP_B(label) b label
187#endif
188
189/*
190 * Instruction barrier
191 */
192 .macro instr_sync
193#if __LINUX_ARM_ARCH__ >= 7
194 isb
195#elif __LINUX_ARM_ARCH__ == 6
196 mcr p15, 0, r0, c7, c5, 4
197#endif
198 .endm
199
200/*
201 * SMP data memory barrier
202 */
203 .macro smp_dmb mode
204#ifdef CONFIG_SMP
205#if __LINUX_ARM_ARCH__ >= 7
206 .ifeqs "\mode","arm"
207 ALT_SMP(dmb)
208 .else
209 ALT_SMP(W(dmb))
210 .endif
211#elif __LINUX_ARM_ARCH__ == 6
212 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
213#else
214#error Incompatible SMP platform
215#endif
216 .ifeqs "\mode","arm"
217 ALT_UP(nop)
218 .else
219 ALT_UP(W(nop))
220 .endif
221#endif
222 .endm
223
224#ifdef CONFIG_THUMB2_KERNEL
225 .macro setmode, mode, reg
226 mov \reg, #\mode
227 msr cpsr_c, \reg
228 .endm
229#else
230 .macro setmode, mode, reg
231 msr cpsr_c, #\mode
232 .endm
233#endif
234
235/*
236 * STRT/LDRT access macros with ARM and Thumb-2 variants
237 */
238#ifdef CONFIG_THUMB2_KERNEL
239
240 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
2419999:
242 .if \inc == 1
243 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
244 .elseif \inc == 4
245 \instr\cond\()\t\().w \reg, [\ptr, #\off]
246 .else
247 .error "Unsupported inc macro argument"
248 .endif
249
250 .pushsection __ex_table,"a"
251 .align 3
252 .long 9999b, \abort
253 .popsection
254 .endm
255
256 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
257 @ explicit IT instruction needed because of the label
258 @ introduced by the USER macro
259 .ifnc \cond,al
260 .if \rept == 1
261 itt \cond
262 .elseif \rept == 2
263 ittt \cond
264 .else
265 .error "Unsupported rept macro argument"
266 .endif
267 .endif
268
269 @ Slightly optimised to avoid incrementing the pointer twice
270 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
271 .if \rept == 2
272 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
273 .endif
274
275 add\cond \ptr, #\rept * \inc
276 .endm
277
278#else /* !CONFIG_THUMB2_KERNEL */
279
280 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
281 .rept \rept
2829999:
283 .if \inc == 1
284 \instr\cond\()b\()\t \reg, [\ptr], #\inc
285 .elseif \inc == 4
286 \instr\cond\()\t \reg, [\ptr], #\inc
287 .else
288 .error "Unsupported inc macro argument"
289 .endif
290
291 .pushsection __ex_table,"a"
292 .align 3
293 .long 9999b, \abort
294 .popsection
295 .endr
296 .endm
297
298#endif /* CONFIG_THUMB2_KERNEL */
299
300 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
301 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
302 .endm
303
304 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
305 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
306 .endm
307
308/* Utility macro for declaring string literals */
309 .macro string name:req, string
310 .type \name , #object
311\name:
312 .asciz "\string"
313 .size \name , . - \name
314 .endm
315
316#endif /* __ASM_ASSEMBLER_H__ */