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1/*
2 * Header for the new SH dmaengine driver
3 *
4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef SH_DMA_H
11#define SH_DMA_H
12
13#include <linux/list.h>
14#include <linux/dmaengine.h>
15
16/* Used by slave DMA clients to request DMA to/from a specific peripheral */
17struct sh_dmae_slave {
18 unsigned int slave_id; /* Set by the platform */
19 struct device *dma_dev; /* Set by the platform */
20 const struct sh_dmae_slave_config *config; /* Set by the driver */
21};
22
23struct sh_dmae_regs {
24 u32 sar; /* SAR / source address */
25 u32 dar; /* DAR / destination address */
26 u32 tcr; /* TCR / transfer count */
27};
28
29struct sh_desc {
30 struct sh_dmae_regs hw;
31 struct list_head node;
32 struct dma_async_tx_descriptor async_tx;
33 enum dma_data_direction direction;
34 dma_cookie_t cookie;
35 size_t partial;
36 int chunks;
37 int mark;
38};
39
40struct sh_dmae_slave_config {
41 unsigned int slave_id;
42 dma_addr_t addr;
43 u32 chcr;
44 char mid_rid;
45};
46
47struct sh_dmae_channel {
48 unsigned int offset;
49 unsigned int dmars;
50 unsigned int dmars_bit;
51};
52
53struct sh_dmae_pdata {
54 const struct sh_dmae_slave_config *slave;
55 int slave_num;
56 const struct sh_dmae_channel *channel;
57 int channel_num;
58 unsigned int ts_low_shift;
59 unsigned int ts_low_mask;
60 unsigned int ts_high_shift;
61 unsigned int ts_high_mask;
62 const unsigned int *ts_shift;
63 int ts_shift_num;
64 u16 dmaor_init;
65 unsigned int chcr_offset;
66 u32 chcr_ie_bit;
67
68 unsigned int dmaor_is_32bit:1;
69 unsigned int needs_tend_set:1;
70 unsigned int no_dmars:1;
71};
72
73/* DMA register */
74#define SAR 0x00
75#define DAR 0x04
76#define TCR 0x08
77#define CHCR 0x0C
78#define DMAOR 0x40
79
80#define TEND 0x18 /* USB-DMAC */
81
82/* DMAOR definitions */
83#define DMAOR_AE 0x00000004
84#define DMAOR_NMIF 0x00000002
85#define DMAOR_DME 0x00000001
86
87/* Definitions for the SuperH DMAC */
88#define REQ_L 0x00000000
89#define REQ_E 0x00080000
90#define RACK_H 0x00000000
91#define RACK_L 0x00040000
92#define ACK_R 0x00000000
93#define ACK_W 0x00020000
94#define ACK_H 0x00000000
95#define ACK_L 0x00010000
96#define DM_INC 0x00004000
97#define DM_DEC 0x00008000
98#define DM_FIX 0x0000c000
99#define SM_INC 0x00001000
100#define SM_DEC 0x00002000
101#define SM_FIX 0x00003000
102#define RS_IN 0x00000200
103#define RS_OUT 0x00000300
104#define TS_BLK 0x00000040
105#define TM_BUR 0x00000020
106#define CHCR_DE 0x00000001
107#define CHCR_TE 0x00000002
108#define CHCR_IE 0x00000004
109
110#endif