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1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3#ifdef __KERNEL__
4
5#include <linux/irq.h>
6#include <asm/dcr.h>
7#include <asm/msi_bitmap.h>
8
9/*
10 * Global registers
11 */
12
13#define MPIC_GREG_BASE 0x01000
14
15#define MPIC_GREG_FEATURE_0 0x00000
16#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
17#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
18#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
19#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
20#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
21#define MPIC_GREG_FEATURE_1 0x00010
22#define MPIC_GREG_GLOBAL_CONF_0 0x00020
23#define MPIC_GREG_GCONF_RESET 0x80000000
24/* On the FSL mpic implementations the Mode field is expand to be
25 * 2 bits wide:
26 * 0b00 = pass through (interrupts routed to IRQ0)
27 * 0b01 = Mixed mode
28 * 0b10 = reserved
29 * 0b11 = External proxy / coreint
30 */
31#define MPIC_GREG_GCONF_COREINT 0x60000000
32#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
33#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
34#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
35#define MPIC_GREG_GCONF_MCK 0x08000000
36#define MPIC_GREG_GLOBAL_CONF_1 0x00030
37#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
38#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
39#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
40 (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
41#define MPIC_GREG_VENDOR_0 0x00040
42#define MPIC_GREG_VENDOR_1 0x00050
43#define MPIC_GREG_VENDOR_2 0x00060
44#define MPIC_GREG_VENDOR_3 0x00070
45#define MPIC_GREG_VENDOR_ID 0x00080
46#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
47#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
48#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
49#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
50#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
51#define MPIC_GREG_PROCESSOR_INIT 0x00090
52#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
53#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
54#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
55#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
56#define MPIC_GREG_IPI_STRIDE 0x10
57#define MPIC_GREG_SPURIOUS 0x000e0
58#define MPIC_GREG_TIMER_FREQ 0x000f0
59
60/*
61 *
62 * Timer registers
63 */
64#define MPIC_TIMER_BASE 0x01100
65#define MPIC_TIMER_STRIDE 0x40
66
67#define MPIC_TIMER_CURRENT_CNT 0x00000
68#define MPIC_TIMER_BASE_CNT 0x00010
69#define MPIC_TIMER_VECTOR_PRI 0x00020
70#define MPIC_TIMER_DESTINATION 0x00030
71
72/*
73 * Per-Processor registers
74 */
75
76#define MPIC_CPU_THISBASE 0x00000
77#define MPIC_CPU_BASE 0x20000
78#define MPIC_CPU_STRIDE 0x01000
79
80#define MPIC_CPU_IPI_DISPATCH_0 0x00040
81#define MPIC_CPU_IPI_DISPATCH_1 0x00050
82#define MPIC_CPU_IPI_DISPATCH_2 0x00060
83#define MPIC_CPU_IPI_DISPATCH_3 0x00070
84#define MPIC_CPU_IPI_DISPATCH_STRIDE 0x00010
85#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
86#define MPIC_CPU_TASKPRI_MASK 0x0000000f
87#define MPIC_CPU_WHOAMI 0x00090
88#define MPIC_CPU_WHOAMI_MASK 0x0000001f
89#define MPIC_CPU_INTACK 0x000a0
90#define MPIC_CPU_EOI 0x000b0
91#define MPIC_CPU_MCACK 0x000c0
92
93/*
94 * Per-source registers
95 */
96
97#define MPIC_IRQ_BASE 0x10000
98#define MPIC_IRQ_STRIDE 0x00020
99#define MPIC_IRQ_VECTOR_PRI 0x00000
100#define MPIC_VECPRI_MASK 0x80000000
101#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
102#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
103#define MPIC_VECPRI_PRIORITY_SHIFT 16
104#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
105#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
106#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
107#define MPIC_VECPRI_POLARITY_MASK 0x00800000
108#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
109#define MPIC_VECPRI_SENSE_EDGE 0x00000000
110#define MPIC_VECPRI_SENSE_MASK 0x00400000
111#define MPIC_IRQ_DESTINATION 0x00010
112
113#define MPIC_MAX_IRQ_SOURCES 2048
114#define MPIC_MAX_CPUS 32
115#define MPIC_MAX_ISU 32
116
117/*
118 * Tsi108 implementation of MPIC has many differences from the original one
119 */
120
121/*
122 * Global registers
123 */
124
125#define TSI108_GREG_BASE 0x00000
126#define TSI108_GREG_FEATURE_0 0x00000
127#define TSI108_GREG_GLOBAL_CONF_0 0x00004
128#define TSI108_GREG_VENDOR_ID 0x0000c
129#define TSI108_GREG_IPI_VECTOR_PRI_0 0x00204 /* Doorbell 0 */
130#define TSI108_GREG_IPI_STRIDE 0x0c
131#define TSI108_GREG_SPURIOUS 0x00010
132#define TSI108_GREG_TIMER_FREQ 0x00014
133
134/*
135 * Timer registers
136 */
137#define TSI108_TIMER_BASE 0x0030
138#define TSI108_TIMER_STRIDE 0x10
139#define TSI108_TIMER_CURRENT_CNT 0x00000
140#define TSI108_TIMER_BASE_CNT 0x00004
141#define TSI108_TIMER_VECTOR_PRI 0x00008
142#define TSI108_TIMER_DESTINATION 0x0000c
143
144/*
145 * Per-Processor registers
146 */
147#define TSI108_CPU_BASE 0x00300
148#define TSI108_CPU_STRIDE 0x00040
149#define TSI108_CPU_IPI_DISPATCH_0 0x00200
150#define TSI108_CPU_IPI_DISPATCH_STRIDE 0x00000
151#define TSI108_CPU_CURRENT_TASK_PRI 0x00000
152#define TSI108_CPU_WHOAMI 0xffffffff
153#define TSI108_CPU_INTACK 0x00004
154#define TSI108_CPU_EOI 0x00008
155#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
156
157/*
158 * Per-source registers
159 */
160#define TSI108_IRQ_BASE 0x00100
161#define TSI108_IRQ_STRIDE 0x00008
162#define TSI108_IRQ_VECTOR_PRI 0x00000
163#define TSI108_VECPRI_VECTOR_MASK 0x000000ff
164#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
165#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
166#define TSI108_VECPRI_SENSE_LEVEL 0x02000000
167#define TSI108_VECPRI_SENSE_EDGE 0x00000000
168#define TSI108_VECPRI_POLARITY_MASK 0x01000000
169#define TSI108_VECPRI_SENSE_MASK 0x02000000
170#define TSI108_IRQ_DESTINATION 0x00004
171
172/* weird mpic register indices and mask bits in the HW info array */
173enum {
174 MPIC_IDX_GREG_BASE = 0,
175 MPIC_IDX_GREG_FEATURE_0,
176 MPIC_IDX_GREG_GLOBAL_CONF_0,
177 MPIC_IDX_GREG_VENDOR_ID,
178 MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
179 MPIC_IDX_GREG_IPI_STRIDE,
180 MPIC_IDX_GREG_SPURIOUS,
181 MPIC_IDX_GREG_TIMER_FREQ,
182
183 MPIC_IDX_TIMER_BASE,
184 MPIC_IDX_TIMER_STRIDE,
185 MPIC_IDX_TIMER_CURRENT_CNT,
186 MPIC_IDX_TIMER_BASE_CNT,
187 MPIC_IDX_TIMER_VECTOR_PRI,
188 MPIC_IDX_TIMER_DESTINATION,
189
190 MPIC_IDX_CPU_BASE,
191 MPIC_IDX_CPU_STRIDE,
192 MPIC_IDX_CPU_IPI_DISPATCH_0,
193 MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
194 MPIC_IDX_CPU_CURRENT_TASK_PRI,
195 MPIC_IDX_CPU_WHOAMI,
196 MPIC_IDX_CPU_INTACK,
197 MPIC_IDX_CPU_EOI,
198 MPIC_IDX_CPU_MCACK,
199
200 MPIC_IDX_IRQ_BASE,
201 MPIC_IDX_IRQ_STRIDE,
202 MPIC_IDX_IRQ_VECTOR_PRI,
203
204 MPIC_IDX_VECPRI_VECTOR_MASK,
205 MPIC_IDX_VECPRI_POLARITY_POSITIVE,
206 MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
207 MPIC_IDX_VECPRI_SENSE_LEVEL,
208 MPIC_IDX_VECPRI_SENSE_EDGE,
209 MPIC_IDX_VECPRI_POLARITY_MASK,
210 MPIC_IDX_VECPRI_SENSE_MASK,
211 MPIC_IDX_IRQ_DESTINATION,
212 MPIC_IDX_END
213};
214
215
216#ifdef CONFIG_MPIC_U3_HT_IRQS
217/* Fixup table entry */
218struct mpic_irq_fixup
219{
220 u8 __iomem *base;
221 u8 __iomem *applebase;
222 u32 data;
223 unsigned int index;
224};
225#endif /* CONFIG_MPIC_U3_HT_IRQS */
226
227
228enum mpic_reg_type {
229 mpic_access_mmio_le,
230 mpic_access_mmio_be,
231#ifdef CONFIG_PPC_DCR
232 mpic_access_dcr
233#endif
234};
235
236struct mpic_reg_bank {
237 u32 __iomem *base;
238#ifdef CONFIG_PPC_DCR
239 dcr_host_t dhost;
240#endif /* CONFIG_PPC_DCR */
241};
242
243struct mpic_irq_save {
244 u32 vecprio,
245 dest;
246#ifdef CONFIG_MPIC_U3_HT_IRQS
247 u32 fixup_data;
248#endif
249};
250
251/* The instance data of a given MPIC */
252struct mpic
253{
254 /* The remapper for this MPIC */
255 struct irq_host *irqhost;
256
257 /* The "linux" controller struct */
258 struct irq_chip hc_irq;
259#ifdef CONFIG_MPIC_U3_HT_IRQS
260 struct irq_chip hc_ht_irq;
261#endif
262#ifdef CONFIG_SMP
263 struct irq_chip hc_ipi;
264#endif
265 struct irq_chip hc_tm;
266 const char *name;
267 /* Flags */
268 unsigned int flags;
269 /* How many irq sources in a given ISU */
270 unsigned int isu_size;
271 unsigned int isu_shift;
272 unsigned int isu_mask;
273 unsigned int irq_count;
274 /* Number of sources */
275 unsigned int num_sources;
276 /* default senses array */
277 unsigned char *senses;
278 unsigned int senses_count;
279
280 /* vector numbers used for internal sources (ipi/timers) */
281 unsigned int ipi_vecs[4];
282 unsigned int timer_vecs[8];
283
284 /* Spurious vector to program into unused sources */
285 unsigned int spurious_vec;
286
287#ifdef CONFIG_MPIC_U3_HT_IRQS
288 /* The fixup table */
289 struct mpic_irq_fixup *fixups;
290 raw_spinlock_t fixup_lock;
291#endif
292
293 /* Register access method */
294 enum mpic_reg_type reg_type;
295
296 /* The various ioremap'ed bases */
297 struct mpic_reg_bank gregs;
298 struct mpic_reg_bank tmregs;
299 struct mpic_reg_bank cpuregs[MPIC_MAX_CPUS];
300 struct mpic_reg_bank isus[MPIC_MAX_ISU];
301
302 /* Protected sources */
303 unsigned long *protected;
304
305#ifdef CONFIG_MPIC_WEIRD
306 /* Pointer to HW info array */
307 u32 *hw_set;
308#endif
309
310#ifdef CONFIG_PCI_MSI
311 struct msi_bitmap msi_bitmap;
312#endif
313
314#ifdef CONFIG_MPIC_BROKEN_REGREAD
315 u32 isu_reg0_shadow[MPIC_MAX_IRQ_SOURCES];
316#endif
317
318 /* link */
319 struct mpic *next;
320
321#ifdef CONFIG_PM
322 struct mpic_irq_save *save_data;
323#endif
324};
325
326/*
327 * MPIC flags (passed to mpic_alloc)
328 *
329 * The top 4 bits contain an MPIC bhw id that is used to index the
330 * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
331 * Note setting any ID (leaving those bits to 0) means standard MPIC
332 */
333
334/* This is the primary controller, only that one has IPIs and
335 * has afinity control. A non-primary MPIC always uses CPU0
336 * registers only
337 */
338#define MPIC_PRIMARY 0x00000001
339
340/* Set this for a big-endian MPIC */
341#define MPIC_BIG_ENDIAN 0x00000002
342/* Broken U3 MPIC */
343#define MPIC_U3_HT_IRQS 0x00000004
344/* Broken IPI registers (autodetected) */
345#define MPIC_BROKEN_IPI 0x00000008
346/* MPIC wants a reset */
347#define MPIC_WANTS_RESET 0x00000010
348/* Spurious vector requires EOI */
349#define MPIC_SPV_EOI 0x00000020
350/* No passthrough disable */
351#define MPIC_NO_PTHROU_DIS 0x00000040
352/* DCR based MPIC */
353#define MPIC_USES_DCR 0x00000080
354/* MPIC has 11-bit vector fields (or larger) */
355#define MPIC_LARGE_VECTORS 0x00000100
356/* Enable delivery of prio 15 interrupts as MCK instead of EE */
357#define MPIC_ENABLE_MCK 0x00000200
358/* Disable bias among target selection, spread interrupts evenly */
359#define MPIC_NO_BIAS 0x00000400
360/* Ignore NIRQS as reported by FRR */
361#define MPIC_BROKEN_FRR_NIRQS 0x00000800
362/* Destination only supports a single CPU at a time */
363#define MPIC_SINGLE_DEST_CPU 0x00001000
364/* Enable CoreInt delivery of interrupts */
365#define MPIC_ENABLE_COREINT 0x00002000
366/* Disable resetting of the MPIC.
367 * NOTE: This flag trumps MPIC_WANTS_RESET.
368 */
369#define MPIC_NO_RESET 0x00004000
370/* Freescale MPIC (compatible includes "fsl,mpic") */
371#define MPIC_FSL 0x00008000
372
373/* MPIC HW modification ID */
374#define MPIC_REGSET_MASK 0xf0000000
375#define MPIC_REGSET(val) (((val) & 0xf ) << 28)
376#define MPIC_GET_REGSET(flags) (((flags) >> 28) & 0xf)
377
378#define MPIC_REGSET_STANDARD MPIC_REGSET(0) /* Original MPIC */
379#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
380
381/* Allocate the controller structure and setup the linux irq descs
382 * for the range if interrupts passed in. No HW initialization is
383 * actually performed.
384 *
385 * @phys_addr: physial base address of the MPIC
386 * @flags: flags, see constants above
387 * @isu_size: number of interrupts in an ISU. Use 0 to use a
388 * standard ISU-less setup (aka powermac)
389 * @irq_offset: first irq number to assign to this mpic
390 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
391 * to match the number of sources
392 * @ipi_offset: first irq number to assign to this mpic IPI sources,
393 * used only on primary mpic
394 * @senses: array of sense values
395 * @senses_num: number of entries in the array
396 *
397 * Note about the sense array. If none is passed, all interrupts are
398 * setup to be level negative unless MPIC_U3_HT_IRQS is set in which
399 * case they are edge positive (and the array is ignored anyway).
400 * The values in the array start at the first source of the MPIC,
401 * that is senses[0] correspond to linux irq "irq_offset".
402 */
403extern struct mpic *mpic_alloc(struct device_node *node,
404 phys_addr_t phys_addr,
405 unsigned int flags,
406 unsigned int isu_size,
407 unsigned int irq_count,
408 const char *name);
409
410/* Assign ISUs, to call before mpic_init()
411 *
412 * @mpic: controller structure as returned by mpic_alloc()
413 * @isu_num: ISU number
414 * @phys_addr: physical address of the ISU
415 */
416extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
417 phys_addr_t phys_addr);
418
419/* Set default sense codes
420 *
421 * @mpic: controller
422 * @senses: array of sense codes
423 * @count: size of above array
424 *
425 * Optionally provide an array (indexed on hardware interrupt numbers
426 * for this MPIC) of default sense codes for the chip. Those are linux
427 * sense codes IRQ_TYPE_*
428 *
429 * The driver gets ownership of the pointer, don't dispose of it or
430 * anything like that. __init only.
431 */
432extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
433
434
435/* Initialize the controller. After this has been called, none of the above
436 * should be called again for this mpic
437 */
438extern void mpic_init(struct mpic *mpic);
439
440/*
441 * All of the following functions must only be used after the
442 * ISUs have been assigned and the controller fully initialized
443 * with mpic_init()
444 */
445
446
447/* Change the priority of an interrupt. Default is 8 for irqs and
448 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
449 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
450 */
451extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
452
453/* Setup a non-boot CPU */
454extern void mpic_setup_this_cpu(void);
455
456/* Clean up for kexec (or cpu offline or ...) */
457extern void mpic_teardown_this_cpu(int secondary);
458
459/* Get the current cpu priority for this cpu (0..15) */
460extern int mpic_cpu_get_priority(void);
461
462/* Set the current cpu priority for this cpu */
463extern void mpic_cpu_set_priority(int prio);
464
465/* Request IPIs on primary mpic */
466extern void mpic_request_ipis(void);
467
468/* Send a message (IPI) to a given target (cpu number or MSG_*) */
469void smp_mpic_message_pass(int target, int msg);
470
471/* Unmask a specific virq */
472extern void mpic_unmask_irq(struct irq_data *d);
473/* Mask a specific virq */
474extern void mpic_mask_irq(struct irq_data *d);
475/* EOI a specific virq */
476extern void mpic_end_irq(struct irq_data *d);
477
478/* Fetch interrupt from a given mpic */
479extern unsigned int mpic_get_one_irq(struct mpic *mpic);
480/* This one gets from the primary mpic */
481extern unsigned int mpic_get_irq(void);
482/* This one gets from the primary mpic via CoreInt*/
483extern unsigned int mpic_get_coreint_irq(void);
484/* Fetch Machine Check interrupt from primary mpic */
485extern unsigned int mpic_get_mcirq(void);
486
487/* Set the EPIC clock ratio */
488void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
489
490/* Enable/Disable EPIC serial interrupt mode */
491void mpic_set_serial_int(struct mpic *mpic, int enable);
492
493#endif /* __KERNEL__ */
494#endif /* _ASM_POWERPC_MPIC_H */