tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * linux/drivers/video/omap2/dss/dispc.h
3 *
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef __OMAP2_DISPC_REG_H
22#define __OMAP2_DISPC_REG_H
23
24/* DISPC common registers */
25#define DISPC_REVISION 0x0000
26#define DISPC_SYSCONFIG 0x0010
27#define DISPC_SYSSTATUS 0x0014
28#define DISPC_IRQSTATUS 0x0018
29#define DISPC_IRQENABLE 0x001C
30#define DISPC_CONTROL 0x0040
31#define DISPC_CONFIG 0x0044
32#define DISPC_CAPABLE 0x0048
33#define DISPC_LINE_STATUS 0x005C
34#define DISPC_LINE_NUMBER 0x0060
35#define DISPC_GLOBAL_ALPHA 0x0074
36#define DISPC_CONTROL2 0x0238
37#define DISPC_CONFIG2 0x0620
38#define DISPC_DIVISOR 0x0804
39
40/* DISPC overlay registers */
41#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
42 DISPC_BA0_OFFSET(n))
43#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
44 DISPC_BA1_OFFSET(n))
45#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
46 DISPC_BA0_UV_OFFSET(n))
47#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
48 DISPC_BA1_UV_OFFSET(n))
49#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
50 DISPC_POS_OFFSET(n))
51#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
52 DISPC_SIZE_OFFSET(n))
53#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
54 DISPC_ATTR_OFFSET(n))
55#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
56 DISPC_ATTR2_OFFSET(n))
57#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
58 DISPC_FIFO_THRESH_OFFSET(n))
59#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
60 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
61#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
62 DISPC_ROW_INC_OFFSET(n))
63#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
64 DISPC_PIX_INC_OFFSET(n))
65#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
66 DISPC_WINDOW_SKIP_OFFSET(n))
67#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
68 DISPC_TABLE_BA_OFFSET(n))
69#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
70 DISPC_FIR_OFFSET(n))
71#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
72 DISPC_FIR2_OFFSET(n))
73#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
74 DISPC_PIC_SIZE_OFFSET(n))
75#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
76 DISPC_ACCU0_OFFSET(n))
77#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
78 DISPC_ACCU1_OFFSET(n))
79#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
80 DISPC_ACCU2_0_OFFSET(n))
81#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
82 DISPC_ACCU2_1_OFFSET(n))
83#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
84 DISPC_FIR_COEF_H_OFFSET(n, i))
85#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
86 DISPC_FIR_COEF_HV_OFFSET(n, i))
87#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
88 DISPC_FIR_COEF_H2_OFFSET(n, i))
89#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
90 DISPC_FIR_COEF_HV2_OFFSET(n, i))
91#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
92 DISPC_CONV_COEF_OFFSET(n, i))
93#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
94 DISPC_FIR_COEF_V_OFFSET(n, i))
95#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
96 DISPC_FIR_COEF_V2_OFFSET(n, i))
97#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
98 DISPC_PRELOAD_OFFSET(n))
99
100/* DISPC manager/channel specific registers */
101static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
102{
103 switch (channel) {
104 case OMAP_DSS_CHANNEL_LCD:
105 return 0x004C;
106 case OMAP_DSS_CHANNEL_DIGIT:
107 return 0x0050;
108 case OMAP_DSS_CHANNEL_LCD2:
109 return 0x03AC;
110 default:
111 BUG();
112 }
113}
114
115static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
116{
117 switch (channel) {
118 case OMAP_DSS_CHANNEL_LCD:
119 return 0x0054;
120 case OMAP_DSS_CHANNEL_DIGIT:
121 return 0x0058;
122 case OMAP_DSS_CHANNEL_LCD2:
123 return 0x03B0;
124 default:
125 BUG();
126 }
127}
128
129static inline u16 DISPC_TIMING_H(enum omap_channel channel)
130{
131 switch (channel) {
132 case OMAP_DSS_CHANNEL_LCD:
133 return 0x0064;
134 case OMAP_DSS_CHANNEL_DIGIT:
135 BUG();
136 case OMAP_DSS_CHANNEL_LCD2:
137 return 0x0400;
138 default:
139 BUG();
140 }
141}
142
143static inline u16 DISPC_TIMING_V(enum omap_channel channel)
144{
145 switch (channel) {
146 case OMAP_DSS_CHANNEL_LCD:
147 return 0x0068;
148 case OMAP_DSS_CHANNEL_DIGIT:
149 BUG();
150 case OMAP_DSS_CHANNEL_LCD2:
151 return 0x0404;
152 default:
153 BUG();
154 }
155}
156
157static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
158{
159 switch (channel) {
160 case OMAP_DSS_CHANNEL_LCD:
161 return 0x006C;
162 case OMAP_DSS_CHANNEL_DIGIT:
163 BUG();
164 case OMAP_DSS_CHANNEL_LCD2:
165 return 0x0408;
166 default:
167 BUG();
168 }
169}
170
171static inline u16 DISPC_DIVISORo(enum omap_channel channel)
172{
173 switch (channel) {
174 case OMAP_DSS_CHANNEL_LCD:
175 return 0x0070;
176 case OMAP_DSS_CHANNEL_DIGIT:
177 BUG();
178 case OMAP_DSS_CHANNEL_LCD2:
179 return 0x040C;
180 default:
181 BUG();
182 }
183}
184
185/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
186static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
187{
188 switch (channel) {
189 case OMAP_DSS_CHANNEL_LCD:
190 return 0x007C;
191 case OMAP_DSS_CHANNEL_DIGIT:
192 return 0x0078;
193 case OMAP_DSS_CHANNEL_LCD2:
194 return 0x03CC;
195 default:
196 BUG();
197 }
198}
199
200static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
201{
202 switch (channel) {
203 case OMAP_DSS_CHANNEL_LCD:
204 return 0x01D4;
205 case OMAP_DSS_CHANNEL_DIGIT:
206 BUG();
207 case OMAP_DSS_CHANNEL_LCD2:
208 return 0x03C0;
209 default:
210 BUG();
211 }
212}
213
214static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
215{
216 switch (channel) {
217 case OMAP_DSS_CHANNEL_LCD:
218 return 0x01D8;
219 case OMAP_DSS_CHANNEL_DIGIT:
220 BUG();
221 case OMAP_DSS_CHANNEL_LCD2:
222 return 0x03C4;
223 default:
224 BUG();
225 }
226}
227
228static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
229{
230 switch (channel) {
231 case OMAP_DSS_CHANNEL_LCD:
232 return 0x01DC;
233 case OMAP_DSS_CHANNEL_DIGIT:
234 BUG();
235 case OMAP_DSS_CHANNEL_LCD2:
236 return 0x03C8;
237 default:
238 BUG();
239 }
240}
241
242static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
243{
244 switch (channel) {
245 case OMAP_DSS_CHANNEL_LCD:
246 return 0x0220;
247 case OMAP_DSS_CHANNEL_DIGIT:
248 BUG();
249 case OMAP_DSS_CHANNEL_LCD2:
250 return 0x03BC;
251 default:
252 BUG();
253 }
254}
255
256static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
257{
258 switch (channel) {
259 case OMAP_DSS_CHANNEL_LCD:
260 return 0x0224;
261 case OMAP_DSS_CHANNEL_DIGIT:
262 BUG();
263 case OMAP_DSS_CHANNEL_LCD2:
264 return 0x03B8;
265 default:
266 BUG();
267 }
268}
269
270static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
271{
272 switch (channel) {
273 case OMAP_DSS_CHANNEL_LCD:
274 return 0x0228;
275 case OMAP_DSS_CHANNEL_DIGIT:
276 BUG();
277 case OMAP_DSS_CHANNEL_LCD2:
278 return 0x03B4;
279 default:
280 BUG();
281 }
282}
283
284/* DISPC overlay register base addresses */
285static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
286{
287 switch (plane) {
288 case OMAP_DSS_GFX:
289 return 0x0080;
290 case OMAP_DSS_VIDEO1:
291 return 0x00BC;
292 case OMAP_DSS_VIDEO2:
293 return 0x014C;
294 case OMAP_DSS_VIDEO3:
295 return 0x0300;
296 default:
297 BUG();
298 }
299}
300
301/* DISPC overlay register offsets */
302static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
303{
304 switch (plane) {
305 case OMAP_DSS_GFX:
306 case OMAP_DSS_VIDEO1:
307 case OMAP_DSS_VIDEO2:
308 return 0x0000;
309 case OMAP_DSS_VIDEO3:
310 return 0x0008;
311 default:
312 BUG();
313 }
314}
315
316static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
317{
318 switch (plane) {
319 case OMAP_DSS_GFX:
320 case OMAP_DSS_VIDEO1:
321 case OMAP_DSS_VIDEO2:
322 return 0x0004;
323 case OMAP_DSS_VIDEO3:
324 return 0x000C;
325 default:
326 BUG();
327 }
328}
329
330static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
331{
332 switch (plane) {
333 case OMAP_DSS_GFX:
334 BUG();
335 case OMAP_DSS_VIDEO1:
336 return 0x0544;
337 case OMAP_DSS_VIDEO2:
338 return 0x04BC;
339 case OMAP_DSS_VIDEO3:
340 return 0x0310;
341 default:
342 BUG();
343 }
344}
345
346static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
347{
348 switch (plane) {
349 case OMAP_DSS_GFX:
350 BUG();
351 case OMAP_DSS_VIDEO1:
352 return 0x0548;
353 case OMAP_DSS_VIDEO2:
354 return 0x04C0;
355 case OMAP_DSS_VIDEO3:
356 return 0x0314;
357 default:
358 BUG();
359 }
360}
361
362static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
363{
364 switch (plane) {
365 case OMAP_DSS_GFX:
366 case OMAP_DSS_VIDEO1:
367 case OMAP_DSS_VIDEO2:
368 return 0x0008;
369 case OMAP_DSS_VIDEO3:
370 return 0x009C;
371 default:
372 BUG();
373 }
374}
375
376static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
377{
378 switch (plane) {
379 case OMAP_DSS_GFX:
380 case OMAP_DSS_VIDEO1:
381 case OMAP_DSS_VIDEO2:
382 return 0x000C;
383 case OMAP_DSS_VIDEO3:
384 return 0x00A8;
385 default:
386 BUG();
387 }
388}
389
390static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
391{
392 switch (plane) {
393 case OMAP_DSS_GFX:
394 return 0x0020;
395 case OMAP_DSS_VIDEO1:
396 case OMAP_DSS_VIDEO2:
397 return 0x0010;
398 case OMAP_DSS_VIDEO3:
399 return 0x0070;
400 default:
401 BUG();
402 }
403}
404
405static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
406{
407 switch (plane) {
408 case OMAP_DSS_GFX:
409 BUG();
410 case OMAP_DSS_VIDEO1:
411 return 0x0568;
412 case OMAP_DSS_VIDEO2:
413 return 0x04DC;
414 case OMAP_DSS_VIDEO3:
415 return 0x032C;
416 default:
417 BUG();
418 }
419}
420
421static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
422{
423 switch (plane) {
424 case OMAP_DSS_GFX:
425 return 0x0024;
426 case OMAP_DSS_VIDEO1:
427 case OMAP_DSS_VIDEO2:
428 return 0x0014;
429 case OMAP_DSS_VIDEO3:
430 return 0x008C;
431 default:
432 BUG();
433 }
434}
435
436static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
437{
438 switch (plane) {
439 case OMAP_DSS_GFX:
440 return 0x0028;
441 case OMAP_DSS_VIDEO1:
442 case OMAP_DSS_VIDEO2:
443 return 0x0018;
444 case OMAP_DSS_VIDEO3:
445 return 0x0088;
446 default:
447 BUG();
448 }
449}
450
451static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
452{
453 switch (plane) {
454 case OMAP_DSS_GFX:
455 return 0x002C;
456 case OMAP_DSS_VIDEO1:
457 case OMAP_DSS_VIDEO2:
458 return 0x001C;
459 case OMAP_DSS_VIDEO3:
460 return 0x00A4;
461 default:
462 BUG();
463 }
464}
465
466static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
467{
468 switch (plane) {
469 case OMAP_DSS_GFX:
470 return 0x0030;
471 case OMAP_DSS_VIDEO1:
472 case OMAP_DSS_VIDEO2:
473 return 0x0020;
474 case OMAP_DSS_VIDEO3:
475 return 0x0098;
476 default:
477 BUG();
478 }
479}
480
481static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
482{
483 switch (plane) {
484 case OMAP_DSS_GFX:
485 return 0x0034;
486 case OMAP_DSS_VIDEO1:
487 case OMAP_DSS_VIDEO2:
488 case OMAP_DSS_VIDEO3:
489 BUG();
490 default:
491 BUG();
492 }
493}
494
495static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
496{
497 switch (plane) {
498 case OMAP_DSS_GFX:
499 return 0x0038;
500 case OMAP_DSS_VIDEO1:
501 case OMAP_DSS_VIDEO2:
502 case OMAP_DSS_VIDEO3:
503 BUG();
504 default:
505 BUG();
506 }
507}
508
509static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
510{
511 switch (plane) {
512 case OMAP_DSS_GFX:
513 BUG();
514 case OMAP_DSS_VIDEO1:
515 case OMAP_DSS_VIDEO2:
516 return 0x0024;
517 case OMAP_DSS_VIDEO3:
518 return 0x0090;
519 default:
520 BUG();
521 }
522}
523
524static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
525{
526 switch (plane) {
527 case OMAP_DSS_GFX:
528 BUG();
529 case OMAP_DSS_VIDEO1:
530 return 0x0580;
531 case OMAP_DSS_VIDEO2:
532 return 0x055C;
533 case OMAP_DSS_VIDEO3:
534 return 0x0424;
535 default:
536 BUG();
537 }
538}
539
540static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
541{
542 switch (plane) {
543 case OMAP_DSS_GFX:
544 BUG();
545 case OMAP_DSS_VIDEO1:
546 case OMAP_DSS_VIDEO2:
547 return 0x0028;
548 case OMAP_DSS_VIDEO3:
549 return 0x0094;
550 default:
551 BUG();
552 }
553}
554
555
556static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
557{
558 switch (plane) {
559 case OMAP_DSS_GFX:
560 BUG();
561 case OMAP_DSS_VIDEO1:
562 case OMAP_DSS_VIDEO2:
563 return 0x002C;
564 case OMAP_DSS_VIDEO3:
565 return 0x0000;
566 default:
567 BUG();
568 }
569}
570
571static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
572{
573 switch (plane) {
574 case OMAP_DSS_GFX:
575 BUG();
576 case OMAP_DSS_VIDEO1:
577 return 0x0584;
578 case OMAP_DSS_VIDEO2:
579 return 0x0560;
580 case OMAP_DSS_VIDEO3:
581 return 0x0428;
582 default:
583 BUG();
584 }
585}
586
587static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
588{
589 switch (plane) {
590 case OMAP_DSS_GFX:
591 BUG();
592 case OMAP_DSS_VIDEO1:
593 case OMAP_DSS_VIDEO2:
594 return 0x0030;
595 case OMAP_DSS_VIDEO3:
596 return 0x0004;
597 default:
598 BUG();
599 }
600}
601
602static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
603{
604 switch (plane) {
605 case OMAP_DSS_GFX:
606 BUG();
607 case OMAP_DSS_VIDEO1:
608 return 0x0588;
609 case OMAP_DSS_VIDEO2:
610 return 0x0564;
611 case OMAP_DSS_VIDEO3:
612 return 0x042C;
613 default:
614 BUG();
615 }
616}
617
618/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
619static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
620{
621 switch (plane) {
622 case OMAP_DSS_GFX:
623 BUG();
624 case OMAP_DSS_VIDEO1:
625 case OMAP_DSS_VIDEO2:
626 return 0x0034 + i * 0x8;
627 case OMAP_DSS_VIDEO3:
628 return 0x0010 + i * 0x8;
629 default:
630 BUG();
631 }
632}
633
634/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
635static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
636{
637 switch (plane) {
638 case OMAP_DSS_GFX:
639 BUG();
640 case OMAP_DSS_VIDEO1:
641 return 0x058C + i * 0x8;
642 case OMAP_DSS_VIDEO2:
643 return 0x0568 + i * 0x8;
644 case OMAP_DSS_VIDEO3:
645 return 0x0430 + i * 0x8;
646 default:
647 BUG();
648 }
649}
650
651/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
652static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
653{
654 switch (plane) {
655 case OMAP_DSS_GFX:
656 BUG();
657 case OMAP_DSS_VIDEO1:
658 case OMAP_DSS_VIDEO2:
659 return 0x0038 + i * 0x8;
660 case OMAP_DSS_VIDEO3:
661 return 0x0014 + i * 0x8;
662 default:
663 BUG();
664 }
665}
666
667/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
668static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
669{
670 switch (plane) {
671 case OMAP_DSS_GFX:
672 BUG();
673 case OMAP_DSS_VIDEO1:
674 return 0x0590 + i * 8;
675 case OMAP_DSS_VIDEO2:
676 return 0x056C + i * 0x8;
677 case OMAP_DSS_VIDEO3:
678 return 0x0434 + i * 0x8;
679 default:
680 BUG();
681 }
682}
683
684/* coef index i = {0, 1, 2, 3, 4,} */
685static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
686{
687 switch (plane) {
688 case OMAP_DSS_GFX:
689 BUG();
690 case OMAP_DSS_VIDEO1:
691 case OMAP_DSS_VIDEO2:
692 case OMAP_DSS_VIDEO3:
693 return 0x0074 + i * 0x4;
694 default:
695 BUG();
696 }
697}
698
699/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
700static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
701{
702 switch (plane) {
703 case OMAP_DSS_GFX:
704 BUG();
705 case OMAP_DSS_VIDEO1:
706 return 0x0124 + i * 0x4;
707 case OMAP_DSS_VIDEO2:
708 return 0x00B4 + i * 0x4;
709 case OMAP_DSS_VIDEO3:
710 return 0x0050 + i * 0x4;
711 default:
712 BUG();
713 }
714}
715
716/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
717static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
718{
719 switch (plane) {
720 case OMAP_DSS_GFX:
721 BUG();
722 case OMAP_DSS_VIDEO1:
723 return 0x05CC + i * 0x4;
724 case OMAP_DSS_VIDEO2:
725 return 0x05A8 + i * 0x4;
726 case OMAP_DSS_VIDEO3:
727 return 0x0470 + i * 0x4;
728 default:
729 BUG();
730 }
731}
732
733static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
734{
735 switch (plane) {
736 case OMAP_DSS_GFX:
737 return 0x01AC;
738 case OMAP_DSS_VIDEO1:
739 return 0x0174;
740 case OMAP_DSS_VIDEO2:
741 return 0x00E8;
742 case OMAP_DSS_VIDEO3:
743 return 0x00A0;
744 default:
745 BUG();
746 }
747}
748#endif