Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15#include <asm/page.h>
16#include <asm/cacheflush.h>
17#include <arch/icache.h>
18#include <arch/spr_def.h>
19
20
21void __flush_icache_range(unsigned long start, unsigned long end)
22{
23 invalidate_icache((const void *)start, end - start, PAGE_SIZE);
24}
25
26
27/* Force a load instruction to issue. */
28static inline void force_load(char *p)
29{
30 *(volatile char *)p;
31}
32
33/*
34 * Flush and invalidate a VA range that is homed remotely on a single
35 * core (if "!hfh") or homed via hash-for-home (if "hfh"), waiting
36 * until the memory controller holds the flushed values.
37 */
38void finv_buffer_remote(void *buffer, size_t size, int hfh)
39{
40 char *p, *base;
41 size_t step_size, load_count;
42 const unsigned long STRIPE_WIDTH = 8192;
43#ifdef __tilegx__
44 /*
45 * On TILE-Gx, we must disable the dstream prefetcher before doing
46 * a cache flush; otherwise, we could end up with data in the cache
47 * that we don't want there. Note that normally we'd do an mf
48 * after the SPR write to disabling the prefetcher, but we do one
49 * below, before any further loads, so there's no need to do it
50 * here.
51 */
52 uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
53 __insn_mtspr(SPR_DSTREAM_PF, 0);
54#endif
55
56 /*
57 * Flush and invalidate the buffer out of the local L1/L2
58 * and request the home cache to flush and invalidate as well.
59 */
60 __finv_buffer(buffer, size);
61
62 /*
63 * Wait for the home cache to acknowledge that it has processed
64 * all the flush-and-invalidate requests. This does not mean
65 * that the flushed data has reached the memory controller yet,
66 * but it does mean the home cache is processing the flushes.
67 */
68 __insn_mf();
69
70 /*
71 * Issue a load to the last cache line, which can't complete
72 * until all the previously-issued flushes to the same memory
73 * controller have also completed. If we weren't striping
74 * memory, that one load would be sufficient, but since we may
75 * be, we also need to back up to the last load issued to
76 * another memory controller, which would be the point where
77 * we crossed an 8KB boundary (the granularity of striping
78 * across memory controllers). Keep backing up and doing this
79 * until we are before the beginning of the buffer, or have
80 * hit all the controllers.
81 *
82 * If we are flushing a hash-for-home buffer, it's even worse.
83 * Each line may be homed on a different tile, and each tile
84 * may have up to four lines that are on different
85 * controllers. So as we walk backwards, we have to touch
86 * enough cache lines to satisfy these constraints. In
87 * practice this ends up being close enough to "load from
88 * every cache line on a full memory stripe on each
89 * controller" that we simply do that, to simplify the logic.
90 *
91 * FIXME: See bug 9535 for some issues with this code.
92 */
93 if (hfh) {
94 step_size = L2_CACHE_BYTES;
95 load_count = (STRIPE_WIDTH / L2_CACHE_BYTES) *
96 (1 << CHIP_LOG_NUM_MSHIMS());
97 } else {
98 step_size = STRIPE_WIDTH;
99 load_count = (1 << CHIP_LOG_NUM_MSHIMS());
100 }
101
102 /* Load the last byte of the buffer. */
103 p = (char *)buffer + size - 1;
104 force_load(p);
105
106 /* Bump down to the end of the previous stripe or cache line. */
107 p -= step_size;
108 p = (char *)((unsigned long)p | (step_size - 1));
109
110 /* Figure out how far back we need to go. */
111 base = p - (step_size * (load_count - 2));
112 if ((long)base < (long)buffer)
113 base = buffer;
114
115 /*
116 * Fire all the loads we need. The MAF only has eight entries
117 * so we can have at most eight outstanding loads, so we
118 * unroll by that amount.
119 */
120#pragma unroll 8
121 for (; p >= base; p -= step_size)
122 force_load(p);
123
124 /*
125 * Repeat, but with inv's instead of loads, to get rid of the
126 * data we just loaded into our own cache and the old home L3.
127 * No need to unroll since inv's don't target a register.
128 */
129 p = (char *)buffer + size - 1;
130 __insn_inv(p);
131 p -= step_size;
132 p = (char *)((unsigned long)p | (step_size - 1));
133 for (; p >= base; p -= step_size)
134 __insn_inv(p);
135
136 /* Wait for the load+inv's (and thus finvs) to have completed. */
137 __insn_mf();
138
139#ifdef __tilegx__
140 /* Reenable the prefetcher. */
141 __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
142#endif
143}