Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/spinlock_types.h>
40#include <linux/semaphore.h>
41#include <linux/slab.h>
42#include <linux/vmalloc.h>
43#include <linux/radix-tree.h>
44
45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h>
47#include <linux/mlx5/mlx5_ifc.h>
48
49enum {
50 MLX5_BOARD_ID_LEN = 64,
51 MLX5_MAX_NAME_LEN = 16,
52};
53
54enum {
55 /* one minute for the sake of bringup. Generally, commands must always
56 * complete and we may need to increase this timeout value
57 */
58 MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000,
59 MLX5_CMD_WQ_MAX_NAME = 32,
60};
61
62enum {
63 CMD_OWNER_SW = 0x0,
64 CMD_OWNER_HW = 0x1,
65 CMD_STATUS_SUCCESS = 0,
66};
67
68enum mlx5_sqp_t {
69 MLX5_SQP_SMI = 0,
70 MLX5_SQP_GSI = 1,
71 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SNIFFER = 3,
73 MLX5_SQP_SYNC_UMR = 4,
74};
75
76enum {
77 MLX5_MAX_PORTS = 2,
78};
79
80enum {
81 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_CMD = 1,
83 MLX5_EQ_VEC_ASYNC = 2,
84 MLX5_EQ_VEC_COMP_BASE,
85};
86
87enum {
88 MLX5_MAX_EQ_NAME = 32
89};
90
91enum {
92 MLX5_ATOMIC_MODE_IB_COMP = 1 << 16,
93 MLX5_ATOMIC_MODE_CX = 2 << 16,
94 MLX5_ATOMIC_MODE_8B = 3 << 16,
95 MLX5_ATOMIC_MODE_16B = 4 << 16,
96 MLX5_ATOMIC_MODE_32B = 5 << 16,
97 MLX5_ATOMIC_MODE_64B = 6 << 16,
98 MLX5_ATOMIC_MODE_128B = 7 << 16,
99 MLX5_ATOMIC_MODE_256B = 8 << 16,
100};
101
102enum {
103 MLX5_REG_PCAP = 0x5001,
104 MLX5_REG_PMTU = 0x5003,
105 MLX5_REG_PTYS = 0x5004,
106 MLX5_REG_PAOS = 0x5006,
107 MLX5_REG_PMAOS = 0x5012,
108 MLX5_REG_PUDE = 0x5009,
109 MLX5_REG_PMPE = 0x5010,
110 MLX5_REG_PELC = 0x500e,
111 MLX5_REG_PMLP = 0, /* TBD */
112 MLX5_REG_NODE_DESC = 0x6001,
113 MLX5_REG_HOST_ENDIANNESS = 0x7004,
114};
115
116enum mlx5_page_fault_resume_flags {
117 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
118 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
119 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
120 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
121};
122
123enum dbg_rsc_type {
124 MLX5_DBG_RSC_QP,
125 MLX5_DBG_RSC_EQ,
126 MLX5_DBG_RSC_CQ,
127};
128
129struct mlx5_field_desc {
130 struct dentry *dent;
131 int i;
132};
133
134struct mlx5_rsc_debug {
135 struct mlx5_core_dev *dev;
136 void *object;
137 enum dbg_rsc_type type;
138 struct dentry *root;
139 struct mlx5_field_desc fields[0];
140};
141
142enum mlx5_dev_event {
143 MLX5_DEV_EVENT_SYS_ERROR,
144 MLX5_DEV_EVENT_PORT_UP,
145 MLX5_DEV_EVENT_PORT_DOWN,
146 MLX5_DEV_EVENT_PORT_INITIALIZED,
147 MLX5_DEV_EVENT_LID_CHANGE,
148 MLX5_DEV_EVENT_PKEY_CHANGE,
149 MLX5_DEV_EVENT_GUID_CHANGE,
150 MLX5_DEV_EVENT_CLIENT_REREG,
151};
152
153struct mlx5_uuar_info {
154 struct mlx5_uar *uars;
155 int num_uars;
156 int num_low_latency_uuars;
157 unsigned long *bitmap;
158 unsigned int *count;
159 struct mlx5_bf *bfs;
160
161 /*
162 * protect uuar allocation data structs
163 */
164 struct mutex lock;
165 u32 ver;
166};
167
168struct mlx5_bf {
169 void __iomem *reg;
170 void __iomem *regreg;
171 int buf_size;
172 struct mlx5_uar *uar;
173 unsigned long offset;
174 int need_lock;
175 /* protect blue flame buffer selection when needed
176 */
177 spinlock_t lock;
178
179 /* serialize 64 bit writes when done as two 32 bit accesses
180 */
181 spinlock_t lock32;
182 int uuarn;
183};
184
185struct mlx5_cmd_first {
186 __be32 data[4];
187};
188
189struct mlx5_cmd_msg {
190 struct list_head list;
191 struct cache_ent *cache;
192 u32 len;
193 struct mlx5_cmd_first first;
194 struct mlx5_cmd_mailbox *next;
195};
196
197struct mlx5_cmd_debug {
198 struct dentry *dbg_root;
199 struct dentry *dbg_in;
200 struct dentry *dbg_out;
201 struct dentry *dbg_outlen;
202 struct dentry *dbg_status;
203 struct dentry *dbg_run;
204 void *in_msg;
205 void *out_msg;
206 u8 status;
207 u16 inlen;
208 u16 outlen;
209};
210
211struct cache_ent {
212 /* protect block chain allocations
213 */
214 spinlock_t lock;
215 struct list_head head;
216};
217
218struct cmd_msg_cache {
219 struct cache_ent large;
220 struct cache_ent med;
221
222};
223
224struct mlx5_cmd_stats {
225 u64 sum;
226 u64 n;
227 struct dentry *root;
228 struct dentry *avg;
229 struct dentry *count;
230 /* protect command average calculations */
231 spinlock_t lock;
232};
233
234struct mlx5_cmd {
235 void *cmd_buf;
236 dma_addr_t dma;
237 u16 cmdif_rev;
238 u8 log_sz;
239 u8 log_stride;
240 int max_reg_cmds;
241 int events;
242 u32 __iomem *vector;
243
244 /* protect command queue allocations
245 */
246 spinlock_t alloc_lock;
247
248 /* protect token allocations
249 */
250 spinlock_t token_lock;
251 u8 token;
252 unsigned long bitmask;
253 char wq_name[MLX5_CMD_WQ_MAX_NAME];
254 struct workqueue_struct *wq;
255 struct semaphore sem;
256 struct semaphore pages_sem;
257 int mode;
258 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
259 struct pci_pool *pool;
260 struct mlx5_cmd_debug dbg;
261 struct cmd_msg_cache cache;
262 int checksum_disabled;
263 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
264};
265
266struct mlx5_port_caps {
267 int gid_table_len;
268 int pkey_table_len;
269};
270
271struct mlx5_general_caps {
272 u8 log_max_eq;
273 u8 log_max_cq;
274 u8 log_max_qp;
275 u8 log_max_mkey;
276 u8 log_max_pd;
277 u8 log_max_srq;
278 u8 log_max_strq;
279 u8 log_max_mrw_sz;
280 u8 log_max_bsf_list_size;
281 u8 log_max_klm_list_size;
282 u32 max_cqes;
283 int max_wqes;
284 u32 max_eqes;
285 u32 max_indirection;
286 int max_sq_desc_sz;
287 int max_rq_desc_sz;
288 int max_dc_sq_desc_sz;
289 u64 flags;
290 u16 stat_rate_support;
291 int log_max_msg;
292 int num_ports;
293 u8 log_max_ra_res_qp;
294 u8 log_max_ra_req_qp;
295 int max_srq_wqes;
296 int bf_reg_size;
297 int bf_regs_per_page;
298 struct mlx5_port_caps port[MLX5_MAX_PORTS];
299 u8 ext_port_cap[MLX5_MAX_PORTS];
300 int max_vf;
301 u32 reserved_lkey;
302 u8 local_ca_ack_delay;
303 u8 log_max_mcg;
304 u32 max_qp_mcg;
305 int min_page_sz;
306 int pd_cap;
307 u32 max_qp_counters;
308 u32 pkey_table_size;
309 u8 log_max_ra_req_dc;
310 u8 log_max_ra_res_dc;
311 u32 uar_sz;
312 u8 min_log_pg_sz;
313 u8 log_max_xrcd;
314 u16 log_uar_page_sz;
315};
316
317struct mlx5_caps {
318 struct mlx5_general_caps gen;
319};
320
321struct mlx5_cmd_mailbox {
322 void *buf;
323 dma_addr_t dma;
324 struct mlx5_cmd_mailbox *next;
325};
326
327struct mlx5_buf_list {
328 void *buf;
329 dma_addr_t map;
330};
331
332struct mlx5_buf {
333 struct mlx5_buf_list direct;
334 struct mlx5_buf_list *page_list;
335 int nbufs;
336 int npages;
337 int size;
338 u8 page_shift;
339};
340
341struct mlx5_eq {
342 struct mlx5_core_dev *dev;
343 __be32 __iomem *doorbell;
344 u32 cons_index;
345 struct mlx5_buf buf;
346 int size;
347 u8 irqn;
348 u8 eqn;
349 int nent;
350 u64 mask;
351 char name[MLX5_MAX_EQ_NAME];
352 struct list_head list;
353 int index;
354 struct mlx5_rsc_debug *dbg;
355};
356
357struct mlx5_core_psv {
358 u32 psv_idx;
359 struct psv_layout {
360 u32 pd;
361 u16 syndrome;
362 u16 reserved;
363 u16 bg;
364 u16 app_tag;
365 u32 ref_tag;
366 } psv;
367};
368
369struct mlx5_core_sig_ctx {
370 struct mlx5_core_psv psv_memory;
371 struct mlx5_core_psv psv_wire;
372 struct ib_sig_err err_item;
373 bool sig_status_checked;
374 bool sig_err_exists;
375 u32 sigerr_count;
376};
377
378struct mlx5_core_mr {
379 u64 iova;
380 u64 size;
381 u32 key;
382 u32 pd;
383};
384
385enum mlx5_res_type {
386 MLX5_RES_QP,
387};
388
389struct mlx5_core_rsc_common {
390 enum mlx5_res_type res;
391 atomic_t refcount;
392 struct completion free;
393};
394
395struct mlx5_core_srq {
396 u32 srqn;
397 int max;
398 int max_gs;
399 int max_avail_gather;
400 int wqe_shift;
401 void (*event) (struct mlx5_core_srq *, enum mlx5_event);
402
403 atomic_t refcount;
404 struct completion free;
405};
406
407struct mlx5_eq_table {
408 void __iomem *update_ci;
409 void __iomem *update_arm_ci;
410 struct list_head *comp_eq_head;
411 struct mlx5_eq pages_eq;
412 struct mlx5_eq async_eq;
413 struct mlx5_eq cmd_eq;
414 struct msix_entry *msix_arr;
415 int num_comp_vectors;
416 /* protect EQs list
417 */
418 spinlock_t lock;
419};
420
421struct mlx5_uar {
422 u32 index;
423 struct list_head bf_list;
424 unsigned free_bf_bmap;
425 void __iomem *wc_map;
426 void __iomem *map;
427};
428
429
430struct mlx5_core_health {
431 struct health_buffer __iomem *health;
432 __be32 __iomem *health_counter;
433 struct timer_list timer;
434 struct list_head list;
435 u32 prev;
436 int miss_counter;
437};
438
439struct mlx5_cq_table {
440 /* protect radix tree
441 */
442 spinlock_t lock;
443 struct radix_tree_root tree;
444};
445
446struct mlx5_qp_table {
447 /* protect radix tree
448 */
449 spinlock_t lock;
450 struct radix_tree_root tree;
451};
452
453struct mlx5_srq_table {
454 /* protect radix tree
455 */
456 spinlock_t lock;
457 struct radix_tree_root tree;
458};
459
460struct mlx5_mr_table {
461 /* protect radix tree
462 */
463 rwlock_t lock;
464 struct radix_tree_root tree;
465};
466
467struct mlx5_priv {
468 char name[MLX5_MAX_NAME_LEN];
469 struct mlx5_eq_table eq_table;
470 struct mlx5_uuar_info uuari;
471 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
472
473 /* pages stuff */
474 struct workqueue_struct *pg_wq;
475 struct rb_root page_root;
476 int fw_pages;
477 atomic_t reg_pages;
478 struct list_head free_list;
479
480 struct mlx5_core_health health;
481
482 struct mlx5_srq_table srq_table;
483
484 /* start: qp staff */
485 struct mlx5_qp_table qp_table;
486 struct dentry *qp_debugfs;
487 struct dentry *eq_debugfs;
488 struct dentry *cq_debugfs;
489 struct dentry *cmdif_debugfs;
490 /* end: qp staff */
491
492 /* start: cq staff */
493 struct mlx5_cq_table cq_table;
494 /* end: cq staff */
495
496 /* start: mr staff */
497 struct mlx5_mr_table mr_table;
498 /* end: mr staff */
499
500 /* start: alloc staff */
501 struct mutex pgdir_mutex;
502 struct list_head pgdir_list;
503 /* end: alloc staff */
504 struct dentry *dbg_root;
505
506 /* protect mkey key part */
507 spinlock_t mkey_lock;
508 u8 mkey_key;
509
510 struct list_head dev_list;
511 struct list_head ctx_list;
512 spinlock_t ctx_lock;
513};
514
515struct mlx5_core_dev {
516 struct pci_dev *pdev;
517 u8 rev_id;
518 char board_id[MLX5_BOARD_ID_LEN];
519 struct mlx5_cmd cmd;
520 struct mlx5_caps caps;
521 phys_addr_t iseg_base;
522 struct mlx5_init_seg __iomem *iseg;
523 void (*event) (struct mlx5_core_dev *dev,
524 enum mlx5_dev_event event,
525 unsigned long param);
526 struct mlx5_priv priv;
527 struct mlx5_profile *profile;
528 atomic_t num_qps;
529};
530
531struct mlx5_db {
532 __be32 *db;
533 union {
534 struct mlx5_db_pgdir *pgdir;
535 struct mlx5_ib_user_db_page *user_page;
536 } u;
537 dma_addr_t dma;
538 int index;
539};
540
541enum {
542 MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES,
543};
544
545enum {
546 MLX5_COMP_EQ_SIZE = 1024,
547};
548
549struct mlx5_db_pgdir {
550 struct list_head list;
551 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
552 __be32 *db_page;
553 dma_addr_t db_dma;
554};
555
556typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
557
558struct mlx5_cmd_work_ent {
559 struct mlx5_cmd_msg *in;
560 struct mlx5_cmd_msg *out;
561 void *uout;
562 int uout_size;
563 mlx5_cmd_cbk_t callback;
564 void *context;
565 int idx;
566 struct completion done;
567 struct mlx5_cmd *cmd;
568 struct work_struct work;
569 struct mlx5_cmd_layout *lay;
570 int ret;
571 int page_queue;
572 u8 status;
573 u8 token;
574 u64 ts1;
575 u64 ts2;
576 u16 op;
577};
578
579struct mlx5_pas {
580 u64 pa;
581 u8 log_sz;
582};
583
584static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
585{
586 if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
587 return buf->direct.buf + offset;
588 else
589 return buf->page_list[offset >> PAGE_SHIFT].buf +
590 (offset & (PAGE_SIZE - 1));
591}
592
593extern struct workqueue_struct *mlx5_core_wq;
594
595#define STRUCT_FIELD(header, field) \
596 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
597 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
598
599struct ib_field {
600 size_t struct_offset_bytes;
601 size_t struct_size_bytes;
602 int offset_bits;
603 int size_bits;
604};
605
606static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
607{
608 return pci_get_drvdata(pdev);
609}
610
611extern struct dentry *mlx5_debugfs_root;
612
613static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
614{
615 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
616}
617
618static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
619{
620 return ioread32be(&dev->iseg->fw_rev) >> 16;
621}
622
623static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
624{
625 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
626}
627
628static inline u16 cmdif_rev(struct mlx5_core_dev *dev)
629{
630 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
631}
632
633static inline void *mlx5_vzalloc(unsigned long size)
634{
635 void *rtn;
636
637 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
638 if (!rtn)
639 rtn = vzalloc(size);
640 return rtn;
641}
642
643static inline u32 mlx5_base_mkey(const u32 key)
644{
645 return key & 0xffffff00u;
646}
647
648int mlx5_cmd_init(struct mlx5_core_dev *dev);
649void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
650void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
651void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
652int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
653int mlx5_cmd_status_to_err_v2(void *ptr);
654int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
655 u16 opmod);
656int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
657 int out_size);
658int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
659 void *out, int out_size, mlx5_cmd_cbk_t callback,
660 void *context);
661int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
662int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
663int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
664int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
665void mlx5_health_cleanup(void);
666void __init mlx5_health_init(void);
667void mlx5_start_health_poll(struct mlx5_core_dev *dev);
668void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
669int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
670 struct mlx5_buf *buf);
671void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
672struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
673 gfp_t flags, int npages);
674void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
675 struct mlx5_cmd_mailbox *head);
676int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
677 struct mlx5_create_srq_mbox_in *in, int inlen);
678int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
679int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
680 struct mlx5_query_srq_mbox_out *out);
681int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
682 u16 lwm, int is_srq);
683void mlx5_init_mr_table(struct mlx5_core_dev *dev);
684void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
685int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
686 struct mlx5_create_mkey_mbox_in *in, int inlen,
687 mlx5_cmd_cbk_t callback, void *context,
688 struct mlx5_create_mkey_mbox_out *out);
689int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
690int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
691 struct mlx5_query_mkey_mbox_out *out, int outlen);
692int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
693 u32 *mkey);
694int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
695int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
696int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
697 u16 opmod, u8 port);
698void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
699void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
700int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
701void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
702void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
703 s32 npages);
704int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
705int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
706void mlx5_register_debugfs(void);
707void mlx5_unregister_debugfs(void);
708int mlx5_eq_init(struct mlx5_core_dev *dev);
709void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
710void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
711void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
712void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
713#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
714void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe);
715#endif
716void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
717struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
718void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector);
719void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
720int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
721 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
722int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
723int mlx5_start_eqs(struct mlx5_core_dev *dev);
724int mlx5_stop_eqs(struct mlx5_core_dev *dev);
725int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
726int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
727
728int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
729void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
730int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
731 int size_in, void *data_out, int size_out,
732 u16 reg_num, int arg, int write);
733int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
734
735int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
736void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
737int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
738 struct mlx5_query_eq_mbox_out *out, int outlen);
739int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
740void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
741int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
742void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
743int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
744void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
745
746const char *mlx5_command_str(int command);
747int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
748void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
749int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
750 int npsvs, u32 *sig_index);
751int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
752void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
753int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
754 struct mlx5_odp_caps *odp_caps);
755
756static inline u32 mlx5_mkey_to_idx(u32 mkey)
757{
758 return mkey >> 8;
759}
760
761static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
762{
763 return mkey_idx << 8;
764}
765
766static inline u8 mlx5_mkey_variant(u32 mkey)
767{
768 return mkey & 0xff;
769}
770
771enum {
772 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
773 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
774};
775
776enum {
777 MAX_MR_CACHE_ENTRIES = 16,
778};
779
780struct mlx5_interface {
781 void * (*add)(struct mlx5_core_dev *dev);
782 void (*remove)(struct mlx5_core_dev *dev, void *context);
783 void (*event)(struct mlx5_core_dev *dev, void *context,
784 enum mlx5_dev_event event, unsigned long param);
785 struct list_head list;
786};
787
788int mlx5_register_interface(struct mlx5_interface *intf);
789void mlx5_unregister_interface(struct mlx5_interface *intf);
790
791struct mlx5_profile {
792 u64 mask;
793 u8 log_max_qp;
794 struct {
795 int size;
796 int limit;
797 } mr_cache[MAX_MR_CACHE_ENTRIES];
798};
799
800#endif /* MLX5_DRIVER_H */