tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Broadcom Starfighter2 private context
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __BCM_SF2_H
13#define __BCM_SF2_H
14
15#include <linux/platform_device.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/mutex.h>
20#include <linux/mii.h>
21#include <linux/ethtool.h>
22
23#include <net/dsa.h>
24
25#include "bcm_sf2_regs.h"
26
27struct bcm_sf2_hw_params {
28 u16 top_rev;
29 u16 core_rev;
30 u16 gphy_rev;
31 u32 num_gphy;
32 u8 num_acb_queue;
33 u8 num_rgmii;
34 u8 num_ports;
35 u8 fcb_pause_override:1;
36 u8 acb_packets_inflight:1;
37};
38
39#define BCM_SF2_REGS_NAME {\
40 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
41}
42
43#define BCM_SF2_REGS_NUM 6
44
45struct bcm_sf2_port_status {
46 unsigned int link;
47
48 struct ethtool_eee eee;
49};
50
51struct bcm_sf2_priv {
52 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
53 void __iomem *core;
54 void __iomem *reg;
55 void __iomem *intrl2_0;
56 void __iomem *intrl2_1;
57 void __iomem *fcb;
58 void __iomem *acb;
59
60 /* spinlock protecting access to the indirect registers */
61 spinlock_t indir_lock;
62
63 int irq0;
64 int irq1;
65 u32 irq0_stat;
66 u32 irq0_mask;
67 u32 irq1_stat;
68 u32 irq1_mask;
69
70 /* Mutex protecting access to the MIB counters */
71 struct mutex stats_mutex;
72
73 struct bcm_sf2_hw_params hw_params;
74
75 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
76
77 /* Mask of ports enabled for Wake-on-LAN */
78 u32 wol_ports_mask;
79};
80
81struct bcm_sf2_hw_stats {
82 const char *string;
83 u16 reg;
84 u8 sizeof_stat;
85};
86
87#define SF2_IO_MACRO(name) \
88static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
89{ \
90 return __raw_readl(priv->name + off); \
91} \
92static inline void name##_writel(struct bcm_sf2_priv *priv, \
93 u32 val, u32 off) \
94{ \
95 __raw_writel(val, priv->name + off); \
96} \
97
98/* Accesses to 64-bits register requires us to latch the hi/lo pairs
99 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
100 * spinlock is automatically grabbed and released to provide relative
101 * atomiticy with latched reads/writes.
102 */
103#define SF2_IO64_MACRO(name) \
104static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
105{ \
106 u32 indir, dir; \
107 spin_lock(&priv->indir_lock); \
108 indir = reg_readl(priv, REG_DIR_DATA_READ); \
109 dir = __raw_readl(priv->name + off); \
110 spin_unlock(&priv->indir_lock); \
111 return (u64)indir << 32 | dir; \
112} \
113static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off, \
114 u64 val) \
115{ \
116 spin_lock(&priv->indir_lock); \
117 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
118 __raw_writel(lower_32_bits(val), priv->name + off); \
119 spin_unlock(&priv->indir_lock); \
120}
121
122#define SWITCH_INTR_L2(which) \
123static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
124 u32 mask) \
125{ \
126 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
127 priv->irq##which##_mask &= ~(mask); \
128} \
129static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
130 u32 mask) \
131{ \
132 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
133 priv->irq##which##_mask |= (mask); \
134} \
135
136SF2_IO_MACRO(core);
137SF2_IO_MACRO(reg);
138SF2_IO64_MACRO(core);
139SF2_IO_MACRO(intrl2_0);
140SF2_IO_MACRO(intrl2_1);
141SF2_IO_MACRO(fcb);
142SF2_IO_MACRO(acb);
143
144SWITCH_INTR_L2(0);
145SWITCH_INTR_L2(1);
146
147#endif /* __BCM_SF2_H */