tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Allwinner sunxi AHCI SATA platform driver
3 * Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
4 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
5 *
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7 * Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
8 * Daniel Wang <danielwang@allwinnertech.com>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms and conditions of the GNU General Public License,
12 * version 2, as published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 */
19
20#include <linux/ahci_platform.h>
21#include <linux/clk.h>
22#include <linux/errno.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include "ahci.h"
29
30/* Insmod parameters */
31static bool enable_pmp;
32module_param(enable_pmp, bool, 0);
33MODULE_PARM_DESC(enable_pmp,
34 "Enable support for sata port multipliers, only use if you use a pmp!");
35
36#define AHCI_BISTAFR 0x00a0
37#define AHCI_BISTCR 0x00a4
38#define AHCI_BISTFCTR 0x00a8
39#define AHCI_BISTSR 0x00ac
40#define AHCI_BISTDECR 0x00b0
41#define AHCI_DIAGNR0 0x00b4
42#define AHCI_DIAGNR1 0x00b8
43#define AHCI_OOBR 0x00bc
44#define AHCI_PHYCS0R 0x00c0
45#define AHCI_PHYCS1R 0x00c4
46#define AHCI_PHYCS2R 0x00c8
47#define AHCI_TIMER1MS 0x00e0
48#define AHCI_GPARAM1R 0x00e8
49#define AHCI_GPARAM2R 0x00ec
50#define AHCI_PPARAMR 0x00f0
51#define AHCI_TESTR 0x00f4
52#define AHCI_VERSIONR 0x00f8
53#define AHCI_IDR 0x00fc
54#define AHCI_RWCR 0x00fc
55#define AHCI_P0DMACR 0x0170
56#define AHCI_P0PHYCR 0x0178
57#define AHCI_P0PHYSR 0x017c
58
59static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
60{
61 u32 reg_val;
62
63 reg_val = readl(reg);
64 reg_val &= ~(clr_val);
65 writel(reg_val, reg);
66}
67
68static void sunxi_setbits(void __iomem *reg, u32 set_val)
69{
70 u32 reg_val;
71
72 reg_val = readl(reg);
73 reg_val |= set_val;
74 writel(reg_val, reg);
75}
76
77static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
78{
79 u32 reg_val;
80
81 reg_val = readl(reg);
82 reg_val &= ~(clr_val);
83 reg_val |= set_val;
84 writel(reg_val, reg);
85}
86
87static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
88{
89 return (readl(reg) >> shift) & mask;
90}
91
92static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
93{
94 u32 reg_val;
95 int timeout;
96
97 /* This magic is from the original code */
98 writel(0, reg_base + AHCI_RWCR);
99 msleep(5);
100
101 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
102 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
103 (0x7 << 24),
104 (0x5 << 24) | BIT(23) | BIT(18));
105 sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
106 (0x3 << 16) | (0x1f << 8) | (0x3 << 6),
107 (0x2 << 16) | (0x6 << 8) | (0x2 << 6));
108 sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
109 sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
110 sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
111 (0x7 << 20), (0x3 << 20));
112 sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
113 (0x1f << 5), (0x19 << 5));
114 msleep(5);
115
116 sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
117
118 timeout = 250; /* Power up takes aprox 50 us */
119 do {
120 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
121 if (reg_val == 0x02)
122 break;
123
124 if (--timeout == 0) {
125 dev_err(dev, "PHY power up failed.\n");
126 return -EIO;
127 }
128 udelay(1);
129 } while (1);
130
131 sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
132
133 timeout = 100; /* Calibration takes aprox 10 us */
134 do {
135 reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
136 if (reg_val == 0x00)
137 break;
138
139 if (--timeout == 0) {
140 dev_err(dev, "PHY calibration failed.\n");
141 return -EIO;
142 }
143 udelay(1);
144 } while (1);
145
146 msleep(15);
147
148 writel(0x7, reg_base + AHCI_RWCR);
149
150 return 0;
151}
152
153static void ahci_sunxi_start_engine(struct ata_port *ap)
154{
155 void __iomem *port_mmio = ahci_port_base(ap);
156 struct ahci_host_priv *hpriv = ap->host->private_data;
157
158 /* Setup DMA before DMA start */
159 sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
160
161 /* Start DMA */
162 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
163}
164
165static const struct ata_port_info ahci_sunxi_port_info = {
166 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
167 .pio_mask = ATA_PIO4,
168 .udma_mask = ATA_UDMA6,
169 .port_ops = &ahci_platform_ops,
170};
171
172static int ahci_sunxi_probe(struct platform_device *pdev)
173{
174 struct device *dev = &pdev->dev;
175 struct ahci_host_priv *hpriv;
176 int rc;
177
178 hpriv = ahci_platform_get_resources(pdev);
179 if (IS_ERR(hpriv))
180 return PTR_ERR(hpriv);
181
182 hpriv->start_engine = ahci_sunxi_start_engine;
183
184 rc = ahci_platform_enable_resources(hpriv);
185 if (rc)
186 return rc;
187
188 rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
189 if (rc)
190 goto disable_resources;
191
192 hpriv->flags = AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
193 AHCI_HFLAG_YES_NCQ;
194
195 /*
196 * The sunxi sata controller seems to be unable to successfully do a
197 * soft reset if no pmp is attached, so disable pmp use unless
198 * requested, otherwise directly attached disks do not work.
199 */
200 if (!enable_pmp)
201 hpriv->flags |= AHCI_HFLAG_NO_PMP;
202
203 rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info);
204 if (rc)
205 goto disable_resources;
206
207 return 0;
208
209disable_resources:
210 ahci_platform_disable_resources(hpriv);
211 return rc;
212}
213
214#ifdef CONFIG_PM_SLEEP
215static int ahci_sunxi_resume(struct device *dev)
216{
217 struct ata_host *host = dev_get_drvdata(dev);
218 struct ahci_host_priv *hpriv = host->private_data;
219 int rc;
220
221 rc = ahci_platform_enable_resources(hpriv);
222 if (rc)
223 return rc;
224
225 rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
226 if (rc)
227 goto disable_resources;
228
229 rc = ahci_platform_resume_host(dev);
230 if (rc)
231 goto disable_resources;
232
233 return 0;
234
235disable_resources:
236 ahci_platform_disable_resources(hpriv);
237 return rc;
238}
239#endif
240
241static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
242 ahci_sunxi_resume);
243
244static const struct of_device_id ahci_sunxi_of_match[] = {
245 { .compatible = "allwinner,sun4i-a10-ahci", },
246 { },
247};
248MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
249
250static struct platform_driver ahci_sunxi_driver = {
251 .probe = ahci_sunxi_probe,
252 .remove = ata_platform_remove_one,
253 .driver = {
254 .name = "ahci-sunxi",
255 .of_match_table = ahci_sunxi_of_match,
256 .pm = &ahci_sunxi_pm_ops,
257 },
258};
259module_platform_driver(ahci_sunxi_driver);
260
261MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
262MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
263MODULE_LICENSE("GPL");