Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1#include "headers.h"
2
3
4
5#define DDR_DUMP_INTERNAL_DEVICE_MEMORY 0xBFC02B00
6#define MIPS_CLOCK_REG 0x0f000820
7
8/* DDR INIT-133Mhz */
9#define T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 12 /* index for 0x0F007000 */
10static struct bcm_ddr_setting asT3_DDRSetting133MHz[] = {
11 /* DPLL Clock Setting */
12 {0x0F000800, 0x00007212},
13 {0x0f000820, 0x07F13FFF},
14 {0x0f000810, 0x00000F95},
15 {0x0f000860, 0x00000000},
16 {0x0f000880, 0x000003DD},
17 /* Changed source for X-bar and MIPS clock to APLL */
18 {0x0f000840, 0x0FFF1B00},
19 {0x0f000870, 0x00000002},
20 {0x0F00a044, 0x1fffffff},
21 {0x0F00a040, 0x1f000000},
22 {0x0F00a084, 0x1Cffffff},
23 {0x0F00a080, 0x1C000000},
24 {0x0F00a04C, 0x0000000C},
25 /* Memcontroller Default values */
26 {0x0F007000, 0x00010001},
27 {0x0F007004, 0x01010100},
28 {0x0F007008, 0x01000001},
29 {0x0F00700c, 0x00000000},
30 {0x0F007010, 0x01000000},
31 {0x0F007014, 0x01000100},
32 {0x0F007018, 0x01000000},
33 {0x0F00701c, 0x01020001},
34 {0x0F007020, 0x04030107},
35 {0x0F007024, 0x02000007},
36 {0x0F007028, 0x02020202},
37 {0x0F00702c, 0x0206060a},
38 {0x0F007030, 0x05000000},
39 {0x0F007034, 0x00000003},
40 {0x0F007038, 0x110a0200},
41 {0x0F00703C, 0x02101010},
42 {0x0F007040, 0x45751200},
43 {0x0F007044, 0x110a0d00},
44 {0x0F007048, 0x081b0306},
45 {0x0F00704c, 0x00000000},
46 {0x0F007050, 0x0000001c},
47 {0x0F007054, 0x00000000},
48 {0x0F007058, 0x00000000},
49 {0x0F00705c, 0x00000000},
50 {0x0F007060, 0x0010246c},
51 {0x0F007064, 0x00000010},
52 {0x0F007068, 0x00000000},
53 {0x0F00706c, 0x00000001},
54 {0x0F007070, 0x00007000},
55 {0x0F007074, 0x00000000},
56 {0x0F007078, 0x00000000},
57 {0x0F00707C, 0x00000000},
58 {0x0F007080, 0x00000000},
59 {0x0F007084, 0x00000000},
60 /* Enable BW improvement within memory controller */
61 {0x0F007094, 0x00000104},
62 /* Enable 2 ports within X-bar */
63 {0x0F00A000, 0x00000016},
64 /* Enable start bit within memory controller */
65 {0x0F007018, 0x01010000}
66};
67/* 80Mhz */
68#define T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 10 /* index for 0x0F007000 */
69static struct bcm_ddr_setting asT3_DDRSetting80MHz[] = {
70 /* DPLL Clock Setting */
71 {0x0f000810, 0x00000F95},
72 {0x0f000820, 0x07f1ffff},
73 {0x0f000860, 0x00000000},
74 {0x0f000880, 0x000003DD},
75 {0x0F00a044, 0x1fffffff},
76 {0x0F00a040, 0x1f000000},
77 {0x0F00a084, 0x1Cffffff},
78 {0x0F00a080, 0x1C000000},
79 {0x0F00a000, 0x00000016},
80 {0x0F00a04C, 0x0000000C},
81 /* Memcontroller Default values */
82 {0x0F007000, 0x00010001},
83 {0x0F007004, 0x01000000},
84 {0x0F007008, 0x01000001},
85 {0x0F00700c, 0x00000000},
86 {0x0F007010, 0x01000000},
87 {0x0F007014, 0x01000100},
88 {0x0F007018, 0x01000000},
89 {0x0F00701c, 0x01020000},
90 {0x0F007020, 0x04020107},
91 {0x0F007024, 0x00000007},
92 {0x0F007028, 0x02020201},
93 {0x0F00702c, 0x0204040a},
94 {0x0F007030, 0x04000000},
95 {0x0F007034, 0x00000002},
96 {0x0F007038, 0x1F060200},
97 {0x0F00703C, 0x1C22221F},
98 {0x0F007040, 0x8A006600},
99 {0x0F007044, 0x221a0800},
100 {0x0F007048, 0x02690204},
101 {0x0F00704c, 0x00000000},
102 {0x0F007050, 0x0000001c},
103 {0x0F007054, 0x00000000},
104 {0x0F007058, 0x00000000},
105 {0x0F00705c, 0x00000000},
106 {0x0F007060, 0x000A15D6},
107 {0x0F007064, 0x0000000A},
108 {0x0F007068, 0x00000000},
109 {0x0F00706c, 0x00000001},
110 {0x0F007070, 0x00004000},
111 {0x0F007074, 0x00000000},
112 {0x0F007078, 0x00000000},
113 {0x0F00707C, 0x00000000},
114 {0x0F007080, 0x00000000},
115 {0x0F007084, 0x00000000},
116 {0x0F007094, 0x00000104},
117 /* Enable start bit within memory controller */
118 {0x0F007018, 0x01010000}
119};
120/* 100Mhz */
121#define T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 13 /* index for 0x0F007000 */
122static struct bcm_ddr_setting asT3_DDRSetting100MHz[] = {
123 /* DPLL Clock Setting */
124 {0x0F000800, 0x00007008},
125 {0x0f000810, 0x00000F95},
126 {0x0f000820, 0x07F13E3F},
127 {0x0f000860, 0x00000000},
128 {0x0f000880, 0x000003DD},
129 /* Changed source for X-bar and MIPS clock to APLL */
130 {0x0f000840, 0x0FFF1B00},
131 {0x0f000870, 0x00000002},
132 {0x0F00a044, 0x1fffffff},
133 {0x0F00a040, 0x1f000000},
134 {0x0F00a084, 0x1Cffffff},
135 {0x0F00a080, 0x1C000000},
136 {0x0F00a04C, 0x0000000C},
137 /* Enable 2 ports within X-bar */
138 {0x0F00A000, 0x00000016},
139 /* Memcontroller Default values */
140 {0x0F007000, 0x00010001},
141 {0x0F007004, 0x01010100},
142 {0x0F007008, 0x01000001},
143 {0x0F00700c, 0x00000000},
144 {0x0F007010, 0x01000000},
145 {0x0F007014, 0x01000100},
146 {0x0F007018, 0x01000000},
147 {0x0F00701c, 0x01020001},
148 {0x0F007020, 0x04020107},
149 {0x0F007024, 0x00000007},
150 {0x0F007028, 0x01020201},
151 {0x0F00702c, 0x0204040A},
152 {0x0F007030, 0x06000000},
153 {0x0F007034, 0x00000004},
154 {0x0F007038, 0x20080200},
155 {0x0F00703C, 0x02030320},
156 {0x0F007040, 0x6E7F1200},
157 {0x0F007044, 0x01190A00},
158 {0x0F007048, 0x06120305},
159 {0x0F00704c, 0x00000000},
160 {0x0F007050, 0x0000001C},
161 {0x0F007054, 0x00000000},
162 {0x0F007058, 0x00000000},
163 {0x0F00705c, 0x00000000},
164 {0x0F007060, 0x00082ED6},
165 {0x0F007064, 0x0000000A},
166 {0x0F007068, 0x00000000},
167 {0x0F00706c, 0x00000001},
168 {0x0F007070, 0x00005000},
169 {0x0F007074, 0x00000000},
170 {0x0F007078, 0x00000000},
171 {0x0F00707C, 0x00000000},
172 {0x0F007080, 0x00000000},
173 {0x0F007084, 0x00000000},
174 /* Enable BW improvement within memory controller */
175 {0x0F007094, 0x00000104},
176 /* Enable start bit within memory controller */
177 {0x0F007018, 0x01010000}
178};
179
180/* Net T3B DDR Settings
181 * DDR INIT-133Mhz
182 */
183static struct bcm_ddr_setting asDPLL_266MHZ[] = {
184 {0x0F000800, 0x00007212},
185 {0x0f000820, 0x07F13FFF},
186 {0x0f000810, 0x00000F95},
187 {0x0f000860, 0x00000000},
188 {0x0f000880, 0x000003DD},
189 /* Changed source for X-bar and MIPS clock to APLL */
190 {0x0f000840, 0x0FFF1B00},
191 {0x0f000870, 0x00000002}
192};
193
194#define T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 11 /* index for 0x0F007000 */
195static struct bcm_ddr_setting asT3B_DDRSetting133MHz[] = {
196 /* DPLL Clock Setting */
197 {0x0f000810, 0x00000F95},
198 {0x0f000810, 0x00000F95},
199 {0x0f000810, 0x00000F95},
200 {0x0f000820, 0x07F13652},
201 {0x0f000840, 0x0FFF0800},
202 /* Changed source for X-bar and MIPS clock to APLL */
203 {0x0f000880, 0x000003DD},
204 {0x0f000860, 0x00000000},
205 /* Changed source for X-bar and MIPS clock to APLL */
206 {0x0F00a044, 0x1fffffff},
207 {0x0F00a040, 0x1f000000},
208 {0x0F00a084, 0x1Cffffff},
209 {0x0F00a080, 0x1C000000},
210 /* Enable 2 ports within X-bar */
211 {0x0F00A000, 0x00000016},
212 /* Memcontroller Default values */
213 {0x0F007000, 0x00010001},
214 {0x0F007004, 0x01010100},
215 {0x0F007008, 0x01000001},
216 {0x0F00700c, 0x00000000},
217 {0x0F007010, 0x01000000},
218 {0x0F007014, 0x01000100},
219 {0x0F007018, 0x01000000},
220 {0x0F00701c, 0x01020001},
221 {0x0F007020, 0x04030107},
222 {0x0F007024, 0x02000007},
223 {0x0F007028, 0x02020202},
224 {0x0F00702c, 0x0206060a},
225 {0x0F007030, 0x05000000},
226 {0x0F007034, 0x00000003},
227 {0x0F007038, 0x130a0200},
228 {0x0F00703C, 0x02101012},
229 {0x0F007040, 0x457D1200},
230 {0x0F007044, 0x11130d00},
231 {0x0F007048, 0x040D0306},
232 {0x0F00704c, 0x00000000},
233 {0x0F007050, 0x0000001c},
234 {0x0F007054, 0x00000000},
235 {0x0F007058, 0x00000000},
236 {0x0F00705c, 0x00000000},
237 {0x0F007060, 0x0010246c},
238 {0x0F007064, 0x00000012},
239 {0x0F007068, 0x00000000},
240 {0x0F00706c, 0x00000001},
241 {0x0F007070, 0x00007000},
242 {0x0F007074, 0x00000000},
243 {0x0F007078, 0x00000000},
244 {0x0F00707C, 0x00000000},
245 {0x0F007080, 0x00000000},
246 {0x0F007084, 0x00000000},
247 /* Enable BW improvement within memory controller */
248 {0x0F007094, 0x00000104},
249 /* Enable start bit within memory controller */
250 {0x0F007018, 0x01010000},
251 };
252
253#define T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
254static struct bcm_ddr_setting asT3B_DDRSetting80MHz[] = {
255 /* DPLL Clock Setting */
256 {0x0f000810, 0x00000F95},
257 {0x0f000820, 0x07F13FFF},
258 {0x0f000840, 0x0FFF1F00},
259 {0x0f000880, 0x000003DD},
260 {0x0f000860, 0x00000000},
261
262 {0x0F00a044, 0x1fffffff},
263 {0x0F00a040, 0x1f000000},
264 {0x0F00a084, 0x1Cffffff},
265 {0x0F00a080, 0x1C000000},
266 {0x0F00a000, 0x00000016},
267 /* Memcontroller Default values */
268 {0x0F007000, 0x00010001},
269 {0x0F007004, 0x01000000},
270 {0x0F007008, 0x01000001},
271 {0x0F00700c, 0x00000000},
272 {0x0F007010, 0x01000000},
273 {0x0F007014, 0x01000100},
274 {0x0F007018, 0x01000000},
275 {0x0F00701c, 0x01020000},
276 {0x0F007020, 0x04020107},
277 {0x0F007024, 0x00000007},
278 {0x0F007028, 0x02020201},
279 {0x0F00702c, 0x0204040a},
280 {0x0F007030, 0x04000000},
281 {0x0F007034, 0x02000002},
282 {0x0F007038, 0x1F060202},
283 {0x0F00703C, 0x1C22221F},
284 {0x0F007040, 0x8A006600},
285 {0x0F007044, 0x221a0800},
286 {0x0F007048, 0x02690204},
287 {0x0F00704c, 0x00000000},
288 {0x0F007050, 0x0100001c},
289 {0x0F007054, 0x00000000},
290 {0x0F007058, 0x00000000},
291 {0x0F00705c, 0x00000000},
292 {0x0F007060, 0x000A15D6},
293 {0x0F007064, 0x0000000A},
294 {0x0F007068, 0x00000000},
295 {0x0F00706c, 0x00000001},
296 {0x0F007070, 0x00004000},
297 {0x0F007074, 0x00000000},
298 {0x0F007078, 0x00000000},
299 {0x0F00707C, 0x00000000},
300 {0x0F007080, 0x00000000},
301 {0x0F007084, 0x00000000},
302 {0x0F007094, 0x00000104},
303 /* Enable start bit within memory controller */
304 {0x0F007018, 0x01010000}
305};
306
307/* 100Mhz */
308#define T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 9 /* index for 0x0F007000 */
309static struct bcm_ddr_setting asT3B_DDRSetting100MHz[] = {
310 /* DPLL Clock Setting */
311 {0x0f000810, 0x00000F95},
312 {0x0f000820, 0x07F1369B},
313 {0x0f000840, 0x0FFF0800},
314 {0x0f000880, 0x000003DD},
315 {0x0f000860, 0x00000000},
316 {0x0F00a044, 0x1fffffff},
317 {0x0F00a040, 0x1f000000},
318 {0x0F00a084, 0x1Cffffff},
319 {0x0F00a080, 0x1C000000},
320 /* Enable 2 ports within X-bar */
321 {0x0F00A000, 0x00000016},
322 /* Memcontroller Default values */
323 {0x0F007000, 0x00010001},
324 {0x0F007004, 0x01010100},
325 {0x0F007008, 0x01000001},
326 {0x0F00700c, 0x00000000},
327 {0x0F007010, 0x01000000},
328 {0x0F007014, 0x01000100},
329 {0x0F007018, 0x01000000},
330 {0x0F00701c, 0x01020000},
331 {0x0F007020, 0x04020107},
332 {0x0F007024, 0x00000007},
333 {0x0F007028, 0x01020201},
334 {0x0F00702c, 0x0204040A},
335 {0x0F007030, 0x06000000},
336 {0x0F007034, 0x02000004},
337 {0x0F007038, 0x20080200},
338 {0x0F00703C, 0x02030320},
339 {0x0F007040, 0x6E7F1200},
340 {0x0F007044, 0x01190A00},
341 {0x0F007048, 0x06120305},
342 {0x0F00704c, 0x00000000},
343 {0x0F007050, 0x0100001C},
344 {0x0F007054, 0x00000000},
345 {0x0F007058, 0x00000000},
346 {0x0F00705c, 0x00000000},
347 {0x0F007060, 0x00082ED6},
348 {0x0F007064, 0x0000000A},
349 {0x0F007068, 0x00000000},
350 {0x0F00706c, 0x00000001},
351 {0x0F007070, 0x00005000},
352 {0x0F007074, 0x00000000},
353 {0x0F007078, 0x00000000},
354 {0x0F00707C, 0x00000000},
355 {0x0F007080, 0x00000000},
356 {0x0F007084, 0x00000000},
357 /* Enable BW improvement within memory controller */
358 {0x0F007094, 0x00000104},
359 /* Enable start bit within memory controller */
360 {0x0F007018, 0x01010000}
361};
362
363
364#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 9 /* index for 0x0F007000 */
365static struct bcm_ddr_setting asT3LP_DDRSetting133MHz[] = {
366 /* DPLL Clock Setting */
367 {0x0f000820, 0x03F1365B},
368 {0x0f000810, 0x00002F95},
369 {0x0f000880, 0x000003DD},
370 /* Changed source for X-bar and MIPS clock to APLL */
371 {0x0f000840, 0x0FFF0000},
372 {0x0f000860, 0x00000000},
373 {0x0F00a044, 0x1fffffff},
374 {0x0F00a040, 0x1f000000},
375 {0x0F00a084, 0x1Cffffff},
376 {0x0F00a080, 0x1C000000},
377 {0x0F00A000, 0x00000016},
378 /* Memcontroller Default values */
379 {0x0F007000, 0x00010001},
380 {0x0F007004, 0x01010100},
381 {0x0F007008, 0x01000001},
382 {0x0F00700c, 0x00000000},
383 {0x0F007010, 0x01000000},
384 {0x0F007014, 0x01000100},
385 {0x0F007018, 0x01000000},
386 {0x0F00701c, 0x01020001},
387 {0x0F007020, 0x04030107},
388 {0x0F007024, 0x02000007},
389 {0x0F007028, 0x02020200},
390 {0x0F00702c, 0x0206060a},
391 {0x0F007030, 0x05000000},
392 {0x0F007034, 0x00000003},
393 {0x0F007038, 0x200a0200},
394 {0x0F00703C, 0x02101020},
395 {0x0F007040, 0x45711200},
396 {0x0F007044, 0x110D0D00},
397 {0x0F007048, 0x04080306},
398 {0x0F00704c, 0x00000000},
399 {0x0F007050, 0x0100001c},
400 {0x0F007054, 0x00000000},
401 {0x0F007058, 0x00000000},
402 {0x0F00705c, 0x00000000},
403 {0x0F007060, 0x0010245F},
404 {0x0F007064, 0x00000010},
405 {0x0F007068, 0x00000000},
406 {0x0F00706c, 0x00000001},
407 {0x0F007070, 0x00007000},
408 {0x0F007074, 0x00000000},
409 {0x0F007078, 0x00000000},
410 {0x0F00707C, 0x00000000},
411 {0x0F007080, 0x00000000},
412 {0x0F007084, 0x00000000},
413 {0x0F007088, 0x01000001},
414 {0x0F00708c, 0x00000101},
415 {0x0F007090, 0x00000000},
416 /* Enable BW improvement within memory controller */
417 {0x0F007094, 0x00040000},
418 {0x0F007098, 0x00000000},
419 {0x0F0070c8, 0x00000104},
420 /* Enable 2 ports within X-bar */
421 /* Enable start bit within memory controller */
422 {0x0F007018, 0x01010000}
423};
424
425#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 11 /* index for 0x0F007000 */
426static struct bcm_ddr_setting asT3LP_DDRSetting100MHz[] = {
427 /* DPLL Clock Setting */
428 {0x0f000810, 0x00002F95},
429 {0x0f000820, 0x03F1369B},
430 {0x0f000840, 0x0fff0000},
431 {0x0f000860, 0x00000000},
432 {0x0f000880, 0x000003DD},
433 /* Changed source for X-bar and MIPS clock to APLL */
434 {0x0f000840, 0x0FFF0000},
435 {0x0F00a044, 0x1fffffff},
436 {0x0F00a040, 0x1f000000},
437 {0x0F00a084, 0x1Cffffff},
438 {0x0F00a080, 0x1C000000},
439 /* Memcontroller Default values */
440 {0x0F007000, 0x00010001},
441 {0x0F007004, 0x01010100},
442 {0x0F007008, 0x01000001},
443 {0x0F00700c, 0x00000000},
444 {0x0F007010, 0x01000000},
445 {0x0F007014, 0x01000100},
446 {0x0F007018, 0x01000000},
447 {0x0F00701c, 0x01020000},
448 {0x0F007020, 0x04020107},
449 {0x0F007024, 0x00000007},
450 {0x0F007028, 0x01020200},
451 {0x0F00702c, 0x0204040a},
452 {0x0F007030, 0x06000000},
453 {0x0F007034, 0x00000004},
454 {0x0F007038, 0x1F080200},
455 {0x0F00703C, 0x0203031F},
456 {0x0F007040, 0x6e001200},
457 {0x0F007044, 0x011a0a00},
458 {0x0F007048, 0x03000305},
459 {0x0F00704c, 0x00000000},
460 {0x0F007050, 0x0100001c},
461 {0x0F007054, 0x00000000},
462 {0x0F007058, 0x00000000},
463 {0x0F00705c, 0x00000000},
464 {0x0F007060, 0x00082ED6},
465 {0x0F007064, 0x0000000A},
466 {0x0F007068, 0x00000000},
467 {0x0F00706c, 0x00000001},
468 {0x0F007070, 0x00005000},
469 {0x0F007074, 0x00000000},
470 {0x0F007078, 0x00000000},
471 {0x0F00707C, 0x00000000},
472 {0x0F007080, 0x00000000},
473 {0x0F007084, 0x00000000},
474 {0x0F007088, 0x01000001},
475 {0x0F00708c, 0x00000101},
476 {0x0F007090, 0x00000000},
477 {0x0F007094, 0x00010000},
478 {0x0F007098, 0x00000000},
479 {0x0F0070C8, 0x00000104},
480 /* Enable 2 ports within X-bar */
481 {0x0F00A000, 0x00000016},
482 /* Enable start bit within memory controller */
483 {0x0F007018, 0x01010000}
484};
485
486#define T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 9 /* index for 0x0F007000 */
487static struct bcm_ddr_setting asT3LP_DDRSetting80MHz[] = {
488 /* DPLL Clock Setting */
489 {0x0f000820, 0x07F13FFF},
490 {0x0f000810, 0x00002F95},
491 {0x0f000860, 0x00000000},
492 {0x0f000880, 0x000003DD},
493 {0x0f000840, 0x0FFF1F00},
494 {0x0F00a044, 0x1fffffff},
495 {0x0F00a040, 0x1f000000},
496 {0x0F00a084, 0x1Cffffff},
497 {0x0F00a080, 0x1C000000},
498 {0x0F00A000, 0x00000016},
499 {0x0f007000, 0x00010001},
500 {0x0f007004, 0x01000000},
501 {0x0f007008, 0x01000001},
502 {0x0f00700c, 0x00000000},
503 {0x0f007010, 0x01000000},
504 {0x0f007014, 0x01000100},
505 {0x0f007018, 0x01000000},
506 {0x0f00701c, 0x01020000},
507 {0x0f007020, 0x04020107},
508 {0x0f007024, 0x00000007},
509 {0x0f007028, 0x02020200},
510 {0x0f00702c, 0x0204040a},
511 {0x0f007030, 0x04000000},
512 {0x0f007034, 0x00000002},
513 {0x0f007038, 0x1d060200},
514 {0x0f00703c, 0x1c22221d},
515 {0x0f007040, 0x8A116600},
516 {0x0f007044, 0x222d0800},
517 {0x0f007048, 0x02690204},
518 {0x0f00704c, 0x00000000},
519 {0x0f007050, 0x0100001c},
520 {0x0f007054, 0x00000000},
521 {0x0f007058, 0x00000000},
522 {0x0f00705c, 0x00000000},
523 {0x0f007060, 0x000A15D6},
524 {0x0f007064, 0x0000000A},
525 {0x0f007068, 0x00000000},
526 {0x0f00706c, 0x00000001},
527 {0x0f007070, 0x00004000},
528 {0x0f007074, 0x00000000},
529 {0x0f007078, 0x00000000},
530 {0x0f00707c, 0x00000000},
531 {0x0f007080, 0x00000000},
532 {0x0f007084, 0x00000000},
533 {0x0f007088, 0x01000001},
534 {0x0f00708c, 0x00000101},
535 {0x0f007090, 0x00000000},
536 {0x0f007094, 0x00010000},
537 {0x0f007098, 0x00000000},
538 {0x0F0070C8, 0x00000104},
539 {0x0F007018, 0x01010000}
540};
541
542
543
544
545/* T3 LP-B (UMA-B) */
546
547#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ 7 /* index for 0x0F007000 */
548static struct bcm_ddr_setting asT3LPB_DDRSetting160MHz[] = {
549 /* DPLL Clock Setting */
550 {0x0f000820, 0x03F137DB},
551 {0x0f000810, 0x01842795},
552 {0x0f000860, 0x00000000},
553 {0x0f000880, 0x000003DD},
554 {0x0f000840, 0x0FFF0400},
555 {0x0F00a044, 0x1fffffff},
556 {0x0F00a040, 0x1f000000},
557 {0x0f003050, 0x00000021}, /* this is flash/eeprom clock divisor which
558 * set the flash clock to 20 MHz */
559 {0x0F00a084, 0x1Cffffff}, /* Now dump from her in internal memory */
560 {0x0F00a080, 0x1C000000},
561 {0x0F00A000, 0x00000016},
562 {0x0f007000, 0x00010001},
563 {0x0f007004, 0x01000001},
564 {0x0f007008, 0x01000101},
565 {0x0f00700c, 0x00000000},
566 {0x0f007010, 0x01000100},
567 {0x0f007014, 0x01000100},
568 {0x0f007018, 0x01000000},
569 {0x0f00701c, 0x01020000},
570 {0x0f007020, 0x04030107},
571 {0x0f007024, 0x02000007},
572 {0x0f007028, 0x02020200},
573 {0x0f00702c, 0x0206060a},
574 {0x0f007030, 0x050d0d00},
575 {0x0f007034, 0x00000003},
576 {0x0f007038, 0x170a0200},
577 {0x0f00703c, 0x02101012},
578 {0x0f007040, 0x45161200},
579 {0x0f007044, 0x11250c00},
580 {0x0f007048, 0x04da0307},
581 {0x0f00704c, 0x00000000},
582 {0x0f007050, 0x0000001c},
583 {0x0f007054, 0x00000000},
584 {0x0f007058, 0x00000000},
585 {0x0f00705c, 0x00000000},
586 {0x0f007060, 0x00142bb6},
587 {0x0f007064, 0x20430014},
588 {0x0f007068, 0x00000000},
589 {0x0f00706c, 0x00000001},
590 {0x0f007070, 0x00009000},
591 {0x0f007074, 0x00000000},
592 {0x0f007078, 0x00000000},
593 {0x0f00707c, 0x00000000},
594 {0x0f007080, 0x00000000},
595 {0x0f007084, 0x00000000},
596 {0x0f007088, 0x01000001},
597 {0x0f00708c, 0x00000101},
598 {0x0f007090, 0x00000000},
599 {0x0f007094, 0x00040000},
600 {0x0f007098, 0x00000000},
601 {0x0F0070C8, 0x00000104},
602 {0x0F007018, 0x01010000}
603};
604
605
606#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ 7 /* index for 0x0F007000 */
607static struct bcm_ddr_setting asT3LPB_DDRSetting133MHz[] = {
608 /* DPLL Clock Setting */
609 {0x0f000820, 0x03F1365B},
610 {0x0f000810, 0x00002F95},
611 {0x0f000880, 0x000003DD},
612 /* Changed source for X-bar and MIPS clock to APLL */
613 {0x0f000840, 0x0FFF0000},
614 {0x0f000860, 0x00000000},
615 {0x0F00a044, 0x1fffffff},
616 {0x0F00a040, 0x1f000000},
617 {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor which
618 * set the flash clock to 20 MHz */
619 {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
620 {0x0F00a080, 0x1C000000},
621 {0x0F00A000, 0x00000016},
622 /* Memcontroller Default values */
623 {0x0F007000, 0x00010001},
624 {0x0F007004, 0x01010100},
625 {0x0F007008, 0x01000001},
626 {0x0F00700c, 0x00000000},
627 {0x0F007010, 0x01000000},
628 {0x0F007014, 0x01000100},
629 {0x0F007018, 0x01000000},
630 {0x0F00701c, 0x01020001},
631 {0x0F007020, 0x04030107},
632 {0x0F007024, 0x02000007},
633 {0x0F007028, 0x02020200},
634 {0x0F00702c, 0x0206060a},
635 {0x0F007030, 0x05000000},
636 {0x0F007034, 0x00000003},
637 {0x0F007038, 0x190a0200},
638 {0x0F00703C, 0x02101017},
639 {0x0F007040, 0x45171200},
640 {0x0F007044, 0x11290D00},
641 {0x0F007048, 0x04080306},
642 {0x0F00704c, 0x00000000},
643 {0x0F007050, 0x0100001c},
644 {0x0F007054, 0x00000000},
645 {0x0F007058, 0x00000000},
646 {0x0F00705c, 0x00000000},
647 {0x0F007060, 0x0010245F},
648 {0x0F007064, 0x00000010},
649 {0x0F007068, 0x00000000},
650 {0x0F00706c, 0x00000001},
651 {0x0F007070, 0x00007000},
652 {0x0F007074, 0x00000000},
653 {0x0F007078, 0x00000000},
654 {0x0F00707C, 0x00000000},
655 {0x0F007080, 0x00000000},
656 {0x0F007084, 0x00000000},
657 {0x0F007088, 0x01000001},
658 {0x0F00708c, 0x00000101},
659 {0x0F007090, 0x00000000},
660 /* Enable BW improvement within memory controller */
661 {0x0F007094, 0x00040000},
662 {0x0F007098, 0x00000000},
663 {0x0F0070c8, 0x00000104},
664 /* Enable 2 ports within X-bar */
665 /* Enable start bit within memory controller */
666 {0x0F007018, 0x01010000}
667};
668
669#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ 8 /* index for 0x0F007000 */
670static struct bcm_ddr_setting asT3LPB_DDRSetting100MHz[] = {
671 /* DPLL Clock Setting */
672 {0x0f000810, 0x00002F95},
673 {0x0f000820, 0x03F1369B},
674 {0x0f000840, 0x0fff0000},
675 {0x0f000860, 0x00000000},
676 {0x0f000880, 0x000003DD},
677 /* Changed source for X-bar and MIPS clock to APLL */
678 {0x0f000840, 0x0FFF0000},
679 {0x0F00a044, 0x1fffffff},
680 {0x0F00a040, 0x1f000000},
681 {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor which
682 * set the flash clock to 20 MHz */
683 {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
684 {0x0F00a080, 0x1C000000},
685 /* Memcontroller Default values */
686 {0x0F007000, 0x00010001},
687 {0x0F007004, 0x01010100},
688 {0x0F007008, 0x01000001},
689 {0x0F00700c, 0x00000000},
690 {0x0F007010, 0x01000000},
691 {0x0F007014, 0x01000100},
692 {0x0F007018, 0x01000000},
693 {0x0F00701c, 0x01020000},
694 {0x0F007020, 0x04020107},
695 {0x0F007024, 0x00000007},
696 {0x0F007028, 0x01020200},
697 {0x0F00702c, 0x0204040a},
698 {0x0F007030, 0x06000000},
699 {0x0F007034, 0x00000004},
700 {0x0F007038, 0x1F080200},
701 {0x0F00703C, 0x0203031F},
702 {0x0F007040, 0x6e001200},
703 {0x0F007044, 0x011a0a00},
704 {0x0F007048, 0x03000305},
705 {0x0F00704c, 0x00000000},
706 {0x0F007050, 0x0100001c},
707 {0x0F007054, 0x00000000},
708 {0x0F007058, 0x00000000},
709 {0x0F00705c, 0x00000000},
710 {0x0F007060, 0x00082ED6},
711 {0x0F007064, 0x0000000A},
712 {0x0F007068, 0x00000000},
713 {0x0F00706c, 0x00000001},
714 {0x0F007070, 0x00005000},
715 {0x0F007074, 0x00000000},
716 {0x0F007078, 0x00000000},
717 {0x0F00707C, 0x00000000},
718 {0x0F007080, 0x00000000},
719 {0x0F007084, 0x00000000},
720 {0x0F007088, 0x01000001},
721 {0x0F00708c, 0x00000101},
722 {0x0F007090, 0x00000000},
723 {0x0F007094, 0x00010000},
724 {0x0F007098, 0x00000000},
725 {0x0F0070C8, 0x00000104},
726 /* Enable 2 ports within X-bar */
727 {0x0F00A000, 0x00000016},
728 /* Enable start bit within memory controller */
729 {0x0F007018, 0x01010000}
730};
731
732#define T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ 7 /* index for 0x0F007000 */
733static struct bcm_ddr_setting asT3LPB_DDRSetting80MHz[] = {
734 /* DPLL Clock Setting */
735 {0x0f000820, 0x07F13FFF},
736 {0x0f000810, 0x00002F95},
737 {0x0f000860, 0x00000000},
738 {0x0f000880, 0x000003DD},
739 {0x0f000840, 0x0FFF1F00},
740 {0x0F00a044, 0x1fffffff},
741 {0x0F00a040, 0x1f000000},
742 {0x0f003050, 0x00000021}, /* flash/eeprom clock divisor
743 * which set the flash clock to 20 MHz */
744 {0x0F00a084, 0x1Cffffff}, /* dump from here in internal memory */
745 {0x0F00a080, 0x1C000000},
746 {0x0F00A000, 0x00000016},
747 {0x0f007000, 0x00010001},
748 {0x0f007004, 0x01000000},
749 {0x0f007008, 0x01000001},
750 {0x0f00700c, 0x00000000},
751 {0x0f007010, 0x01000000},
752 {0x0f007014, 0x01000100},
753 {0x0f007018, 0x01000000},
754 {0x0f00701c, 0x01020000},
755 {0x0f007020, 0x04020107},
756 {0x0f007024, 0x00000007},
757 {0x0f007028, 0x02020200},
758 {0x0f00702c, 0x0204040a},
759 {0x0f007030, 0x04000000},
760 {0x0f007034, 0x00000002},
761 {0x0f007038, 0x1d060200},
762 {0x0f00703c, 0x1c22221d},
763 {0x0f007040, 0x8A116600},
764 {0x0f007044, 0x222d0800},
765 {0x0f007048, 0x02690204},
766 {0x0f00704c, 0x00000000},
767 {0x0f007050, 0x0100001c},
768 {0x0f007054, 0x00000000},
769 {0x0f007058, 0x00000000},
770 {0x0f00705c, 0x00000000},
771 {0x0f007060, 0x000A15D6},
772 {0x0f007064, 0x0000000A},
773 {0x0f007068, 0x00000000},
774 {0x0f00706c, 0x00000001},
775 {0x0f007070, 0x00004000},
776 {0x0f007074, 0x00000000},
777 {0x0f007078, 0x00000000},
778 {0x0f00707c, 0x00000000},
779 {0x0f007080, 0x00000000},
780 {0x0f007084, 0x00000000},
781 {0x0f007088, 0x01000001},
782 {0x0f00708c, 0x00000101},
783 {0x0f007090, 0x00000000},
784 {0x0f007094, 0x00010000},
785 {0x0f007098, 0x00000000},
786 {0x0F0070C8, 0x00000104},
787 {0x0F007018, 0x01010000}
788};
789
790
791int ddr_init(struct bcm_mini_adapter *Adapter)
792{
793 struct bcm_ddr_setting *psDDRSetting = NULL;
794 ULONG RegCount = 0;
795 UINT value = 0;
796 UINT uiResetValue = 0;
797 UINT uiClockSetting = 0;
798 int retval = STATUS_SUCCESS;
799
800 switch (Adapter->chip_id) {
801 case 0xbece3200:
802 switch (Adapter->DDRSetting) {
803 case DDR_80_MHZ:
804 psDDRSetting = asT3LP_DDRSetting80MHz;
805 RegCount = (sizeof(asT3LP_DDRSetting80MHz) /
806 sizeof(struct bcm_ddr_setting));
807 break;
808 case DDR_100_MHZ:
809 psDDRSetting = asT3LP_DDRSetting100MHz;
810 RegCount = (sizeof(asT3LP_DDRSetting100MHz) /
811 sizeof(struct bcm_ddr_setting));
812 break;
813 case DDR_133_MHZ:
814 psDDRSetting = asT3LP_DDRSetting133MHz;
815 RegCount = (sizeof(asT3LP_DDRSetting133MHz) /
816 sizeof(struct bcm_ddr_setting));
817 if (Adapter->bMipsConfig == MIPS_200_MHZ)
818 uiClockSetting = 0x03F13652;
819 else
820 uiClockSetting = 0x03F1365B;
821 break;
822 default:
823 return -EINVAL;
824 }
825
826 break;
827 case T3LPB:
828 case BCS220_2:
829 case BCS220_2BC:
830 case BCS250_BC:
831 case BCS220_3:
832 /* Set bit 2 and bit 6 to 1 for BBIC 2mA drive
833 * (please check current value and additionally set these bits)
834 */
835 if ((Adapter->chip_id != BCS220_2) &&
836 (Adapter->chip_id != BCS220_2BC) &&
837 (Adapter->chip_id != BCS220_3)) {
838 retval = rdmalt(Adapter, (UINT)0x0f000830, &uiResetValue,
839 sizeof(uiResetValue));
840 if (retval < 0) {
841 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL,
842 "%s:%d RDM failed\n",
843 __func__, __LINE__);
844 return retval;
845 }
846 uiResetValue |= 0x44;
847 retval = wrmalt(Adapter, (UINT)0x0f000830, &uiResetValue,
848 sizeof(uiResetValue));
849 if (retval < 0) {
850 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM, DBG_LVL_ALL,
851 "%s:%d RDM failed\n",
852 __func__, __LINE__);
853 return retval;
854 }
855 }
856 switch (Adapter->DDRSetting) {
857
858
859
860 case DDR_80_MHZ:
861 psDDRSetting = asT3LPB_DDRSetting80MHz;
862 RegCount = (sizeof(asT3B_DDRSetting80MHz) /
863 sizeof(struct bcm_ddr_setting));
864 break;
865 case DDR_100_MHZ:
866 psDDRSetting = asT3LPB_DDRSetting100MHz;
867 RegCount = (sizeof(asT3B_DDRSetting100MHz) /
868 sizeof(struct bcm_ddr_setting));
869 break;
870 case DDR_133_MHZ:
871 psDDRSetting = asT3LPB_DDRSetting133MHz;
872 RegCount = (sizeof(asT3B_DDRSetting133MHz) /
873 sizeof(struct bcm_ddr_setting));
874
875 if (Adapter->bMipsConfig == MIPS_200_MHZ)
876 uiClockSetting = 0x03F13652;
877 else
878 uiClockSetting = 0x03F1365B;
879 break;
880
881 case DDR_160_MHZ:
882 psDDRSetting = asT3LPB_DDRSetting160MHz;
883 RegCount = sizeof(asT3LPB_DDRSetting160MHz) /
884 sizeof(struct bcm_ddr_setting);
885
886 if (Adapter->bMipsConfig == MIPS_200_MHZ)
887 uiClockSetting = 0x03F137D2;
888 else
889 uiClockSetting = 0x03F137DB;
890 }
891 break;
892
893 case 0xbece0110:
894 case 0xbece0120:
895 case 0xbece0121:
896 case 0xbece0130:
897 case 0xbece0300:
898 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL,
899 "DDR Setting: %x\n", Adapter->DDRSetting);
900 switch (Adapter->DDRSetting) {
901 case DDR_80_MHZ:
902 psDDRSetting = asT3_DDRSetting80MHz;
903 RegCount = (sizeof(asT3_DDRSetting80MHz) /
904 sizeof(struct bcm_ddr_setting));
905 break;
906 case DDR_100_MHZ:
907 psDDRSetting = asT3_DDRSetting100MHz;
908 RegCount = (sizeof(asT3_DDRSetting100MHz) /
909 sizeof(struct bcm_ddr_setting));
910 break;
911 case DDR_133_MHZ:
912 psDDRSetting = asT3_DDRSetting133MHz;
913 RegCount = (sizeof(asT3_DDRSetting133MHz) /
914 sizeof(struct bcm_ddr_setting));
915 break;
916 default:
917 return -EINVAL;
918 }
919 case 0xbece0310:
920 {
921 switch (Adapter->DDRSetting) {
922 case DDR_80_MHZ:
923 psDDRSetting = asT3B_DDRSetting80MHz;
924 RegCount = (sizeof(asT3B_DDRSetting80MHz) /
925 sizeof(struct bcm_ddr_setting));
926 break;
927 case DDR_100_MHZ:
928 psDDRSetting = asT3B_DDRSetting100MHz;
929 RegCount = (sizeof(asT3B_DDRSetting100MHz) /
930 sizeof(struct bcm_ddr_setting));
931 break;
932 case DDR_133_MHZ:
933
934 /* 266Mhz PLL selected. */
935 if (Adapter->bDPLLConfig == PLL_266_MHZ) {
936 memcpy(asT3B_DDRSetting133MHz, asDPLL_266MHZ,
937 sizeof(asDPLL_266MHZ));
938 psDDRSetting = asT3B_DDRSetting133MHz;
939 RegCount = (sizeof(asT3B_DDRSetting133MHz) /
940 sizeof(struct bcm_ddr_setting));
941 } else {
942 psDDRSetting = asT3B_DDRSetting133MHz;
943 RegCount = (sizeof(asT3B_DDRSetting133MHz) /
944 sizeof(struct bcm_ddr_setting));
945 if (Adapter->bMipsConfig == MIPS_200_MHZ)
946 uiClockSetting = 0x07F13652;
947 else
948 uiClockSetting = 0x07F1365B;
949 }
950 break;
951 default:
952 return -EINVAL;
953 }
954 break;
955
956 }
957 default:
958 return -EINVAL;
959 }
960
961 value = 0;
962 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_INITEXIT, DRV_ENTRY, DBG_LVL_ALL,
963 "Register Count is =%lu\n", RegCount);
964 while (RegCount && !retval) {
965 if (uiClockSetting
966 && psDDRSetting->ulRegAddress == MIPS_CLOCK_REG)
967 value = uiClockSetting;
968 else
969 value = psDDRSetting->ulRegValue;
970 retval = wrmalt(Adapter, psDDRSetting->ulRegAddress, &value,
971 sizeof(value));
972 if (STATUS_SUCCESS != retval) {
973 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0,
974 "%s:%d\n", __func__, __LINE__);
975 break;
976 }
977
978 RegCount--;
979 psDDRSetting++;
980 }
981
982 if (Adapter->chip_id >= 0xbece3300) {
983
984 mdelay(3);
985 if ((Adapter->chip_id != BCS220_2) &&
986 (Adapter->chip_id != BCS220_2BC) &&
987 (Adapter->chip_id != BCS220_3)) {
988 /* drive MDDR to half in case of UMA-B: */
989 uiResetValue = 0x01010001;
990 retval = wrmalt(Adapter, (UINT)0x0F007018,
991 &uiResetValue, sizeof(uiResetValue));
992 if (retval < 0) {
993 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
994 DBG_LVL_ALL,
995 "%s:%d RDM failed\n",
996 __func__,
997 __LINE__);
998 return retval;
999 }
1000 uiResetValue = 0x00040020;
1001 retval = wrmalt(Adapter, (UINT)0x0F007094,
1002 &uiResetValue, sizeof(uiResetValue));
1003 if (retval < 0) {
1004 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1005 DBG_LVL_ALL,
1006 "%s:%d RDM failed\n",
1007 __func__,
1008 __LINE__);
1009 return retval;
1010 }
1011 uiResetValue = 0x01020101;
1012 retval = wrmalt(Adapter, (UINT)0x0F00701c,
1013 &uiResetValue, sizeof(uiResetValue));
1014 if (retval < 0) {
1015 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1016 DBG_LVL_ALL,
1017 "%s:%d RDM failed\n",
1018 __func__,
1019 __LINE__);
1020 return retval;
1021 }
1022 uiResetValue = 0x01010000;
1023 retval = wrmalt(Adapter, (UINT)0x0F007018,
1024 &uiResetValue, sizeof(uiResetValue));
1025 if (retval < 0) {
1026 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1027 DBG_LVL_ALL,
1028 "%s:%d RDM failed\n",
1029 __func__,
1030 __LINE__);
1031 return retval;
1032 }
1033 }
1034 mdelay(3);
1035
1036 /* DC/DC standby change...
1037 * This is to be done only for Hybrid PMU mode.
1038 * with the current h/w there is no way to detect this.
1039 * and since we dont have internal PMU lets do it under
1040 * UMA-B chip id. we will change this when we will have
1041 * internal PMU.
1042 */
1043 if (Adapter->PmuMode == HYBRID_MODE_7C) {
1044 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1045 &uiResetValue, sizeof(uiResetValue));
1046 if (retval < 0) {
1047 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1048 DBG_LVL_ALL,
1049 "%s:%d RDM failed\n",
1050 __func__,
1051 __LINE__);
1052 return retval;
1053 }
1054 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1055 &uiResetValue, sizeof(uiResetValue));
1056 if (retval < 0) {
1057 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1058 DBG_LVL_ALL,
1059 "%s:%d RDM failed\n",
1060 __func__,
1061 __LINE__);
1062 return retval;
1063 }
1064 uiResetValue = 0x1322a8;
1065 retval = wrmalt(Adapter, (UINT)0x0f000d1c,
1066 &uiResetValue, sizeof(uiResetValue));
1067 if (retval < 0) {
1068 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1069 DBG_LVL_ALL,
1070 "%s:%d RDM failed\n",
1071 __func__,
1072 __LINE__);
1073 return retval;
1074 }
1075 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1076 &uiResetValue, sizeof(uiResetValue));
1077 if (retval < 0) {
1078 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, RDM,
1079 DBG_LVL_ALL,
1080 "%s:%d RDM failed\n",
1081 __func__,
1082 __LINE__);
1083 return retval;
1084 }
1085 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1086 &uiResetValue, sizeof(uiResetValue));
1087 if (retval < 0) {
1088 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1089 DBG_LVL_ALL,
1090 "%s:%d RDM failed\n",
1091 __func__,
1092 __LINE__);
1093 return retval;
1094 }
1095 uiResetValue = 0x132296;
1096 retval = wrmalt(Adapter, (UINT)0x0f000d14,
1097 &uiResetValue, sizeof(uiResetValue));
1098 if (retval < 0) {
1099 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1100 DBG_LVL_ALL,
1101 "%s:%d RDM failed\n",
1102 __func__,
1103 __LINE__);
1104 return retval;
1105 }
1106 } else if (Adapter->PmuMode == HYBRID_MODE_6) {
1107
1108 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1109 &uiResetValue, sizeof(uiResetValue));
1110 if (retval < 0) {
1111 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1112 DBG_LVL_ALL,
1113 "%s:%d RDM failed\n",
1114 __func__,
1115 __LINE__);
1116 return retval;
1117 }
1118 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1119 &uiResetValue, sizeof(uiResetValue));
1120 if (retval < 0) {
1121 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1122 DBG_LVL_ALL,
1123 "%s:%d RDM failed\n",
1124 __func__,
1125 __LINE__);
1126 return retval;
1127 }
1128 uiResetValue = 0x6003229a;
1129 retval = wrmalt(Adapter, (UINT)0x0f000d14,
1130 &uiResetValue, sizeof(uiResetValue));
1131 if (retval < 0) {
1132 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1133 DBG_LVL_ALL,
1134 "%s:%d RDM failed\n",
1135 __func__,
1136 __LINE__);
1137 return retval;
1138 }
1139 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1140 &uiResetValue, sizeof(uiResetValue));
1141 if (retval < 0) {
1142 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1143 DBG_LVL_ALL,
1144 "%s:%d RDM failed\n",
1145 __func__,
1146 __LINE__);
1147 return retval;
1148 }
1149 retval = rdmalt(Adapter, (UINT)0x0f000c00,
1150 &uiResetValue, sizeof(uiResetValue));
1151 if (retval < 0) {
1152 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1153 DBG_LVL_ALL,
1154 "%s:%d RDM failed\n",
1155 __func__,
1156 __LINE__);
1157 return retval;
1158 }
1159 uiResetValue = 0x1322a8;
1160 retval = wrmalt(Adapter, (UINT)0x0f000d1c,
1161 &uiResetValue, sizeof(uiResetValue));
1162 if (retval < 0) {
1163 BCM_DEBUG_PRINT(Adapter, CMHOST, RDM,
1164 DBG_LVL_ALL,
1165 "%s:%d RDM failed\n",
1166 __func__,
1167 __LINE__);
1168 return retval;
1169 }
1170 }
1171
1172 }
1173 Adapter->bDDRInitDone = TRUE;
1174 return retval;
1175}
1176
1177int download_ddr_settings(struct bcm_mini_adapter *Adapter)
1178{
1179 struct bcm_ddr_setting *psDDRSetting = NULL;
1180 ULONG RegCount = 0;
1181 unsigned long ul_ddr_setting_load_addr =
1182 DDR_DUMP_INTERNAL_DEVICE_MEMORY;
1183 UINT value = 0;
1184 int retval = STATUS_SUCCESS;
1185 bool bOverrideSelfRefresh = false;
1186
1187 switch (Adapter->chip_id) {
1188 case 0xbece3200:
1189 switch (Adapter->DDRSetting) {
1190 case DDR_80_MHZ:
1191 psDDRSetting = asT3LP_DDRSetting80MHz;
1192 RegCount = ARRAY_SIZE(asT3LP_DDRSetting80MHz);
1193 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1194 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1195 break;
1196 case DDR_100_MHZ:
1197 psDDRSetting = asT3LP_DDRSetting100MHz;
1198 RegCount = ARRAY_SIZE(asT3LP_DDRSetting100MHz);
1199 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1200 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1201 break;
1202 case DDR_133_MHZ:
1203 bOverrideSelfRefresh = TRUE;
1204 psDDRSetting = asT3LP_DDRSetting133MHz;
1205 RegCount = ARRAY_SIZE(asT3LP_DDRSetting133MHz);
1206 RegCount -= T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1207 psDDRSetting += T3LP_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1208 break;
1209 default:
1210 return -EINVAL;
1211 }
1212 break;
1213
1214 case T3LPB:
1215 case BCS220_2:
1216 case BCS220_2BC:
1217 case BCS250_BC:
1218 case BCS220_3:
1219 switch (Adapter->DDRSetting) {
1220 case DDR_80_MHZ:
1221 psDDRSetting = asT3LPB_DDRSetting80MHz;
1222 RegCount = ARRAY_SIZE(asT3LPB_DDRSetting80MHz);
1223 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1224 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1225 break;
1226 case DDR_100_MHZ:
1227 psDDRSetting = asT3LPB_DDRSetting100MHz;
1228 RegCount = ARRAY_SIZE(asT3LPB_DDRSetting100MHz);
1229 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1230 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1231 break;
1232 case DDR_133_MHZ:
1233 bOverrideSelfRefresh = TRUE;
1234 psDDRSetting = asT3LPB_DDRSetting133MHz;
1235 RegCount = ARRAY_SIZE(asT3LPB_DDRSetting133MHz);
1236 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1237 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1238 break;
1239
1240 case DDR_160_MHZ:
1241 bOverrideSelfRefresh = TRUE;
1242 psDDRSetting = asT3LPB_DDRSetting160MHz;
1243 RegCount = ARRAY_SIZE(asT3LPB_DDRSetting160MHz);
1244 RegCount -= T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1245 psDDRSetting += T3LPB_SKIP_CLOCK_PROGRAM_DUMP_160MHZ;
1246
1247 break;
1248 default:
1249 return -EINVAL;
1250 }
1251 break;
1252 case 0xbece0300:
1253 switch (Adapter->DDRSetting) {
1254 case DDR_80_MHZ:
1255 psDDRSetting = asT3_DDRSetting80MHz;
1256 RegCount = ARRAY_SIZE(asT3_DDRSetting80MHz);
1257 RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1258 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1259 break;
1260 case DDR_100_MHZ:
1261 psDDRSetting = asT3_DDRSetting100MHz;
1262 RegCount = ARRAY_SIZE(asT3_DDRSetting100MHz);
1263 RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1264 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1265 break;
1266 case DDR_133_MHZ:
1267 psDDRSetting = asT3_DDRSetting133MHz;
1268 RegCount = ARRAY_SIZE(asT3_DDRSetting133MHz);
1269 RegCount -= T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1270 psDDRSetting += T3_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1271 break;
1272 default:
1273 return -EINVAL;
1274 }
1275 break;
1276 case 0xbece0310:
1277 {
1278 switch (Adapter->DDRSetting) {
1279 case DDR_80_MHZ:
1280 psDDRSetting = asT3B_DDRSetting80MHz;
1281 RegCount = ARRAY_SIZE(asT3B_DDRSetting80MHz);
1282 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1283 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_80MHZ;
1284 break;
1285 case DDR_100_MHZ:
1286 psDDRSetting = asT3B_DDRSetting100MHz;
1287 RegCount = ARRAY_SIZE(asT3B_DDRSetting100MHz);
1288 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1289 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_100MHZ;
1290 break;
1291 case DDR_133_MHZ:
1292 bOverrideSelfRefresh = TRUE;
1293 psDDRSetting = asT3B_DDRSetting133MHz;
1294 RegCount = ARRAY_SIZE(asT3B_DDRSetting133MHz);
1295 RegCount -= T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1296 psDDRSetting += T3B_SKIP_CLOCK_PROGRAM_DUMP_133MHZ;
1297 break;
1298 }
1299 break;
1300 }
1301 default:
1302 return -EINVAL;
1303 }
1304 /* total number of Register that has to be dumped */
1305 value = RegCount;
1306 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value,
1307 sizeof(value));
1308 if (retval) {
1309 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0,
1310 "%s:%d\n", __func__, __LINE__);
1311
1312 return retval;
1313 }
1314 ul_ddr_setting_load_addr += sizeof(ULONG);
1315 /* signature */
1316 value = (0x1d1e0dd0);
1317 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value,
1318 sizeof(value));
1319 if (retval) {
1320 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0,
1321 "%s:%d\n", __func__, __LINE__);
1322 return retval;
1323 }
1324
1325 ul_ddr_setting_load_addr += sizeof(ULONG);
1326 RegCount *= (sizeof(struct bcm_ddr_setting)/sizeof(ULONG));
1327
1328 while (RegCount && !retval) {
1329 value = psDDRSetting->ulRegAddress;
1330 retval = wrmalt(Adapter, ul_ddr_setting_load_addr, &value,
1331 sizeof(value));
1332 ul_ddr_setting_load_addr += sizeof(ULONG);
1333 if (!retval) {
1334 if (bOverrideSelfRefresh
1335 && (psDDRSetting->ulRegAddress
1336 == 0x0F007018))
1337 value = (psDDRSetting->ulRegValue | (1<<8));
1338 else
1339 value = psDDRSetting->ulRegValue;
1340
1341 if (STATUS_SUCCESS != wrmalt(Adapter,
1342 ul_ddr_setting_load_addr,
1343 &value,
1344 sizeof(value))) {
1345 BCM_DEBUG_PRINT(Adapter, DBG_TYPE_PRINTK, 0, 0,
1346 "%s:%d\n", __func__, __LINE__);
1347 break;
1348 }
1349 }
1350 ul_ddr_setting_load_addr += sizeof(ULONG);
1351 RegCount--;
1352 psDDRSetting++;
1353 }
1354 return retval;
1355}