tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <linux/dma-mapping.h>
20#include <linux/clkdev.h>
21#include <mach/irqs.h>
22#include <mach/msm_iomap.h>
23#include <mach/dma.h>
24
25#include "devices.h"
26#include "smd_private.h"
27#include "common.h"
28
29#include <asm/mach/flash.h>
30
31#include "clock.h"
32#include "clock-pcom.h"
33
34#include <linux/platform_data/mmc-msm_sdcc.h>
35
36static struct resource msm_gpio_resources[] = {
37 {
38 .start = 32 + 18,
39 .end = 32 + 18,
40 .flags = IORESOURCE_IRQ,
41 },
42 {
43 .start = 32 + 19,
44 .end = 32 + 19,
45 .flags = IORESOURCE_IRQ,
46 },
47 {
48 .start = 0xac001000,
49 .end = 0xac001000 + SZ_4K - 1,
50 .flags = IORESOURCE_MEM,
51 .name = "gpio1"
52 },
53 {
54 .start = 0xac101400,
55 .end = 0xac101400 + SZ_4K - 1,
56 .flags = IORESOURCE_MEM,
57 .name = "gpio2"
58 },
59};
60
61struct platform_device msm_device_gpio_7x30 = {
62 .name = "gpio-msm-7x30",
63 .num_resources = ARRAY_SIZE(msm_gpio_resources),
64 .resource = msm_gpio_resources,
65};
66
67static struct resource resources_uart2[] = {
68 {
69 .start = INT_UART2,
70 .end = INT_UART2,
71 .flags = IORESOURCE_IRQ,
72 },
73 {
74 .start = MSM_UART2_PHYS,
75 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
76 .flags = IORESOURCE_MEM,
77 .name = "uart_resource"
78 },
79};
80
81struct platform_device msm_device_uart2 = {
82 .name = "msm_serial",
83 .id = 1,
84 .num_resources = ARRAY_SIZE(resources_uart2),
85 .resource = resources_uart2,
86};
87
88struct platform_device msm_device_smd = {
89 .name = "msm_smd",
90 .id = -1,
91};
92
93static struct resource resources_otg[] = {
94 {
95 .start = MSM_HSUSB_PHYS,
96 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
97 .flags = IORESOURCE_MEM,
98 },
99 {
100 .start = INT_USB_HS,
101 .end = INT_USB_HS,
102 .flags = IORESOURCE_IRQ,
103 },
104};
105
106struct platform_device msm_device_otg = {
107 .name = "msm_otg",
108 .id = -1,
109 .num_resources = ARRAY_SIZE(resources_otg),
110 .resource = resources_otg,
111 .dev = {
112 .coherent_dma_mask = 0xffffffff,
113 },
114};
115
116static struct resource resources_hsusb[] = {
117 {
118 .start = MSM_HSUSB_PHYS,
119 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
120 .flags = IORESOURCE_MEM,
121 },
122 {
123 .start = INT_USB_HS,
124 .end = INT_USB_HS,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129struct platform_device msm_device_hsusb = {
130 .name = "msm_hsusb",
131 .id = -1,
132 .num_resources = ARRAY_SIZE(resources_hsusb),
133 .resource = resources_hsusb,
134 .dev = {
135 .coherent_dma_mask = 0xffffffff,
136 },
137};
138
139static u64 dma_mask = 0xffffffffULL;
140static struct resource resources_hsusb_host[] = {
141 {
142 .start = MSM_HSUSB_PHYS,
143 .end = MSM_HSUSB_PHYS + MSM_HSUSB_SIZE,
144 .flags = IORESOURCE_MEM,
145 },
146 {
147 .start = INT_USB_HS,
148 .end = INT_USB_HS,
149 .flags = IORESOURCE_IRQ,
150 },
151};
152
153struct platform_device msm_device_hsusb_host = {
154 .name = "msm_hsusb_host",
155 .id = -1,
156 .num_resources = ARRAY_SIZE(resources_hsusb_host),
157 .resource = resources_hsusb_host,
158 .dev = {
159 .dma_mask = &dma_mask,
160 .coherent_dma_mask = 0xffffffffULL,
161 },
162};
163
164static struct clk_pcom_desc msm_clocks_7x30[] = {
165 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
166 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
167 CLK_PCOM("cam_m_clk", CAM_M_CLK, NULL, 0),
168 CLK_PCOM("camif_pad_pclk", CAMIF_PAD_P_CLK, NULL, OFF),
169 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
170 CLK_PCOM("codec_ssbi_clk", CODEC_SSBI_CLK, NULL, 0),
171 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
172 CLK_PCOM("ecodec_clk", ECODEC_CLK, NULL, 0),
173 CLK_PCOM("emdh_clk", EMDH_CLK, NULL, OFF | CLK_MINMAX),
174 CLK_PCOM("emdh_pclk", EMDH_P_CLK, NULL, OFF),
175 CLK_PCOM("gp_clk", GP_CLK, NULL, 0),
176 CLK_PCOM("grp_2d_clk", GRP_2D_CLK, NULL, 0),
177 CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK, NULL, 0),
178 CLK_PCOM("grp_clk", GRP_3D_CLK, NULL, 0),
179 CLK_PCOM("grp_pclk", GRP_3D_P_CLK, NULL, 0),
180 CLK_PCOM("hdmi_clk", HDMI_CLK, NULL, 0),
181 CLK_PCOM("imem_clk", IMEM_CLK, NULL, OFF),
182 CLK_PCOM("jpeg_clk", JPEG_CLK, NULL, OFF),
183 CLK_PCOM("jpeg_pclk", JPEG_P_CLK, NULL, OFF),
184 CLK_PCOM("lpa_codec_clk", LPA_CODEC_CLK, NULL, 0),
185 CLK_PCOM("lpa_core_clk", LPA_CORE_CLK, NULL, 0),
186 CLK_PCOM("lpa_pclk", LPA_P_CLK, NULL, 0),
187 CLK_PCOM("mdc_clk", MDC_CLK, NULL, 0),
188 CLK_PCOM("mddi_clk", PMDH_CLK, NULL, OFF | CLK_MINMAX),
189 CLK_PCOM("mddi_pclk", PMDH_P_CLK, NULL, 0),
190 CLK_PCOM("mdp_clk", MDP_CLK, NULL, OFF),
191 CLK_PCOM("mdp_pclk", MDP_P_CLK, NULL, 0),
192 CLK_PCOM("mdp_lcdc_pclk_clk", MDP_LCDC_PCLK_CLK, NULL, 0),
193 CLK_PCOM("mdp_lcdc_pad_pclk_clk", MDP_LCDC_PAD_PCLK_CLK, NULL, 0),
194 CLK_PCOM("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, 0),
195 CLK_PCOM("mfc_clk", MFC_CLK, NULL, 0),
196 CLK_PCOM("mfc_div2_clk", MFC_DIV2_CLK, NULL, 0),
197 CLK_PCOM("mfc_pclk", MFC_P_CLK, NULL, 0),
198 CLK_PCOM("mi2s_m_clk", MI2S_M_CLK, NULL, 0),
199 CLK_PCOM("mi2s_s_clk", MI2S_S_CLK, NULL, 0),
200 CLK_PCOM("mi2s_codec_rx_m_clk", MI2S_CODEC_RX_M_CLK, NULL, 0),
201 CLK_PCOM("mi2s_codec_rx_s_clk", MI2S_CODEC_RX_S_CLK, NULL, 0),
202 CLK_PCOM("mi2s_codec_tx_m_clk", MI2S_CODEC_TX_M_CLK, NULL, 0),
203 CLK_PCOM("mi2s_codec_tx_s_clk", MI2S_CODEC_TX_S_CLK, NULL, 0),
204 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
205 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
206 CLK_PCOM("rotator_clk", AXI_ROTATOR_CLK, NULL, 0),
207 CLK_PCOM("rotator_imem_clk", ROTATOR_IMEM_CLK, NULL, OFF),
208 CLK_PCOM("rotator_pclk", ROTATOR_P_CLK, NULL, OFF),
209 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
210 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
211 CLK_PCOM("spi_pclk", SPI_P_CLK, NULL, 0),
212 CLK_PCOM("tv_dac_clk", TV_DAC_CLK, NULL, 0),
213 CLK_PCOM("tv_enc_clk", TV_ENC_CLK, NULL, 0),
214 CLK_PCOM("core", UART2_CLK, "msm_serial.1", 0),
215 CLK_PCOM("usb_phy_clk", USB_PHY_CLK, NULL, 0),
216 CLK_PCOM("usb_hs_clk", USB_HS_CLK, NULL, OFF),
217 CLK_PCOM("usb_hs_pclk", USB_HS_P_CLK, NULL, OFF),
218 CLK_PCOM("usb_hs_core_clk", USB_HS_CORE_CLK, NULL, OFF),
219 CLK_PCOM("usb_hs2_clk", USB_HS2_CLK, NULL, OFF),
220 CLK_PCOM("usb_hs2_pclk", USB_HS2_P_CLK, NULL, OFF),
221 CLK_PCOM("usb_hs2_core_clk", USB_HS2_CORE_CLK, NULL, OFF),
222 CLK_PCOM("usb_hs3_clk", USB_HS3_CLK, NULL, OFF),
223 CLK_PCOM("usb_hs3_pclk", USB_HS3_P_CLK, NULL, OFF),
224 CLK_PCOM("usb_hs3_core_clk", USB_HS3_CORE_CLK, NULL, OFF),
225 CLK_PCOM("vdc_clk", VDC_CLK, NULL, OFF | CLK_MIN),
226 CLK_PCOM("vfe_camif_clk", VFE_CAMIF_CLK, NULL, 0),
227 CLK_PCOM("vfe_clk", VFE_CLK, NULL, 0),
228 CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK, NULL, 0),
229 CLK_PCOM("vfe_pclk", VFE_P_CLK, NULL, OFF),
230 CLK_PCOM("vpe_clk", VPE_CLK, NULL, 0),
231
232 /* 7x30 v2 hardware only. */
233 CLK_PCOM("csi_clk", CSI0_CLK, NULL, 0),
234 CLK_PCOM("csi_pclk", CSI0_P_CLK, NULL, 0),
235 CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK, NULL, 0),
236};
237
238static struct pcom_clk_pdata msm_clock_7x30_pdata = {
239 .lookup = msm_clocks_7x30,
240 .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
241};
242
243struct platform_device msm_clock_7x30 = {
244 .name = "msm-clock-pcom",
245 .dev.platform_data = &msm_clock_7x30_pdata,
246};