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1* Samsung Exynos specific extensions to the Synopsys Designware Mobile
2 Storage Host Controller
3
4The Synopsys designware mobile storage host controller is used to interface
5a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
6differences between the core Synopsys dw mshc controller properties described
7by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
8extensions to the Synopsys Designware Mobile Storage Host Controller.
9
10Required Properties:
11
12* compatible: should be
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
14 specific extensions.
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
16 specific extensions.
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
18 specific extensions.
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
20 specific extensions.
21
22* samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
23 unit (ciu) clock. This property is applicable only for Exynos5 SoC's and
24 ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7.
25
26* samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
27 in transmit mode and CIU clock phase shift value in receive mode for single
28 data rate mode operation. Refer notes below for the order of the cells and the
29 valid values.
30
31* samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
32 in transmit mode and CIU clock phase shift value in receive mode for double
33 data rate mode operation. Refer notes below for the order of the cells and the
34 valid values.
35
36 Notes for the sdr-timing and ddr-timing values:
37
38 The order of the cells should be
39 - First Cell: CIU clock phase shift value for tx mode.
40 - Second Cell: CIU clock phase shift value for rx mode.
41
42 Valid values for SDR and DDR CIU clock timing for Exynos5250:
43 - valid value for tx phase shift and rx phase shift is 0 to 7.
44 - when CIU clock divider value is set to 3, all possible 8 phase shift
45 values can be used.
46 - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
47 phase shift clocks should be 0.
48
49Required properties for a slot (Deprecated - Recommend to use one slot per host):
50
51* gpios: specifies a list of gpios used for command, clock and data bus. The
52 first gpio is the command line and the second gpio is the clock line. The
53 rest of the gpios (depending on the bus-width property) are the data lines in
54 no particular order. The format of the gpio specifier depends on the gpio
55 controller.
56(Deprecated - Refer to Documentation/devicetree/binding/pinctrl/samsung-pinctrl.txt)
57
58Example:
59
60 The MSHC controller node can be split into two portions, SoC specific and
61 board specific portions as listed below.
62
63 dwmmc0@12200000 {
64 compatible = "samsung,exynos5250-dw-mshc";
65 reg = <0x12200000 0x1000>;
66 interrupts = <0 75 0>;
67 #address-cells = <1>;
68 #size-cells = <0>;
69 };
70
71 dwmmc0@12200000 {
72 num-slots = <1>;
73 cap-mmc-highspeed;
74 cap-sd-highspeed;
75 broken-cd;
76 fifo-depth = <0x80>;
77 card-detect-delay = <200>;
78 samsung,dw-mshc-ciu-div = <3>;
79 samsung,dw-mshc-sdr-timing = <2 3>;
80 samsung,dw-mshc-ddr-timing = <1 2>;
81 bus-width = <8>;
82 };