tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_QP_H
34#define MLX5_QP_H
35
36#include <linux/mlx5/device.h>
37#include <linux/mlx5/driver.h>
38
39#define MLX5_INVALID_LKEY 0x100
40#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41#define MLX5_DIF_SIZE 8
42#define MLX5_STRIDE_BLOCK_OP 0x400
43#define MLX5_CPY_GRD_MASK 0xc0
44#define MLX5_CPY_APP_MASK 0x30
45#define MLX5_CPY_REF_MASK 0x0f
46#define MLX5_BSF_INC_REFTAG (1 << 6)
47#define MLX5_BSF_INL_VALID (1 << 15)
48#define MLX5_BSF_REFRESH_DIF (1 << 14)
49#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
50#define MLX5_BSF_APPTAG_ESCAPE 0x1
51#define MLX5_BSF_APPREF_ESCAPE 0x2
52
53enum mlx5_qp_optpar {
54 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
55 MLX5_QP_OPTPAR_RRE = 1 << 1,
56 MLX5_QP_OPTPAR_RAE = 1 << 2,
57 MLX5_QP_OPTPAR_RWE = 1 << 3,
58 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
59 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
60 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
61 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
62 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
63 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
64 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
65 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
66 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
67 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
68 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
69 MLX5_QP_OPTPAR_SRQN = 1 << 18,
70 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
71 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
72 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
73};
74
75enum mlx5_qp_state {
76 MLX5_QP_STATE_RST = 0,
77 MLX5_QP_STATE_INIT = 1,
78 MLX5_QP_STATE_RTR = 2,
79 MLX5_QP_STATE_RTS = 3,
80 MLX5_QP_STATE_SQER = 4,
81 MLX5_QP_STATE_SQD = 5,
82 MLX5_QP_STATE_ERR = 6,
83 MLX5_QP_STATE_SQ_DRAINING = 7,
84 MLX5_QP_STATE_SUSPENDED = 9,
85 MLX5_QP_NUM_STATE
86};
87
88enum {
89 MLX5_QP_ST_RC = 0x0,
90 MLX5_QP_ST_UC = 0x1,
91 MLX5_QP_ST_UD = 0x2,
92 MLX5_QP_ST_XRC = 0x3,
93 MLX5_QP_ST_MLX = 0x4,
94 MLX5_QP_ST_DCI = 0x5,
95 MLX5_QP_ST_DCT = 0x6,
96 MLX5_QP_ST_QP0 = 0x7,
97 MLX5_QP_ST_QP1 = 0x8,
98 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
99 MLX5_QP_ST_RAW_IPV6 = 0xa,
100 MLX5_QP_ST_SNIFFER = 0xb,
101 MLX5_QP_ST_SYNC_UMR = 0xe,
102 MLX5_QP_ST_PTP_1588 = 0xd,
103 MLX5_QP_ST_REG_UMR = 0xc,
104 MLX5_QP_ST_MAX
105};
106
107enum {
108 MLX5_QP_PM_MIGRATED = 0x3,
109 MLX5_QP_PM_ARMED = 0x0,
110 MLX5_QP_PM_REARM = 0x1
111};
112
113enum {
114 MLX5_NON_ZERO_RQ = 0 << 24,
115 MLX5_SRQ_RQ = 1 << 24,
116 MLX5_CRQ_RQ = 2 << 24,
117 MLX5_ZERO_LEN_RQ = 3 << 24
118};
119
120enum {
121 /* params1 */
122 MLX5_QP_BIT_SRE = 1 << 15,
123 MLX5_QP_BIT_SWE = 1 << 14,
124 MLX5_QP_BIT_SAE = 1 << 13,
125 /* params2 */
126 MLX5_QP_BIT_RRE = 1 << 15,
127 MLX5_QP_BIT_RWE = 1 << 14,
128 MLX5_QP_BIT_RAE = 1 << 13,
129 MLX5_QP_BIT_RIC = 1 << 4,
130};
131
132enum {
133 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
134 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
135};
136
137enum {
138 MLX5_SEND_WQE_BB = 64,
139};
140
141enum {
142 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
143 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
144 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
145 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
146 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
147};
148
149enum {
150 MLX5_FENCE_MODE_NONE = 0 << 5,
151 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
152 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
153 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
154};
155
156enum {
157 MLX5_QP_LAT_SENSITIVE = 1 << 28,
158 MLX5_QP_BLOCK_MCAST = 1 << 30,
159 MLX5_QP_ENABLE_SIG = 1 << 31,
160};
161
162enum {
163 MLX5_RCV_DBR = 0,
164 MLX5_SND_DBR = 1,
165};
166
167enum {
168 MLX5_FLAGS_INLINE = 1<<7,
169 MLX5_FLAGS_CHECK_FREE = 1<<5,
170};
171
172struct mlx5_wqe_fmr_seg {
173 __be32 flags;
174 __be32 mem_key;
175 __be64 buf_list;
176 __be64 start_addr;
177 __be64 reg_len;
178 __be32 offset;
179 __be32 page_size;
180 u32 reserved[2];
181};
182
183struct mlx5_wqe_ctrl_seg {
184 __be32 opmod_idx_opcode;
185 __be32 qpn_ds;
186 u8 signature;
187 u8 rsvd[2];
188 u8 fm_ce_se;
189 __be32 imm;
190};
191
192struct mlx5_wqe_xrc_seg {
193 __be32 xrc_srqn;
194 u8 rsvd[12];
195};
196
197struct mlx5_wqe_masked_atomic_seg {
198 __be64 swap_add;
199 __be64 compare;
200 __be64 swap_add_mask;
201 __be64 compare_mask;
202};
203
204struct mlx5_av {
205 union {
206 struct {
207 __be32 qkey;
208 __be32 reserved;
209 } qkey;
210 __be64 dc_key;
211 } key;
212 __be32 dqp_dct;
213 u8 stat_rate_sl;
214 u8 fl_mlid;
215 __be16 rlid;
216 u8 reserved0[10];
217 u8 tclass;
218 u8 hop_limit;
219 __be32 grh_gid_fl;
220 u8 rgid[16];
221};
222
223struct mlx5_wqe_datagram_seg {
224 struct mlx5_av av;
225};
226
227struct mlx5_wqe_raddr_seg {
228 __be64 raddr;
229 __be32 rkey;
230 u32 reserved;
231};
232
233struct mlx5_wqe_atomic_seg {
234 __be64 swap_add;
235 __be64 compare;
236};
237
238struct mlx5_wqe_data_seg {
239 __be32 byte_count;
240 __be32 lkey;
241 __be64 addr;
242};
243
244struct mlx5_wqe_umr_ctrl_seg {
245 u8 flags;
246 u8 rsvd0[3];
247 __be16 klm_octowords;
248 __be16 bsf_octowords;
249 __be64 mkey_mask;
250 u8 rsvd1[32];
251};
252
253struct mlx5_seg_set_psv {
254 __be32 psv_num;
255 __be16 syndrome;
256 __be16 status;
257 __be32 transient_sig;
258 __be32 ref_tag;
259};
260
261struct mlx5_seg_get_psv {
262 u8 rsvd[19];
263 u8 num_psv;
264 __be32 l_key;
265 __be64 va;
266 __be32 psv_index[4];
267};
268
269struct mlx5_seg_check_psv {
270 u8 rsvd0[2];
271 __be16 err_coalescing_op;
272 u8 rsvd1[2];
273 __be16 xport_err_op;
274 u8 rsvd2[2];
275 __be16 xport_err_mask;
276 u8 rsvd3[7];
277 u8 num_psv;
278 __be32 l_key;
279 __be64 va;
280 __be32 psv_index[4];
281};
282
283struct mlx5_rwqe_sig {
284 u8 rsvd0[4];
285 u8 signature;
286 u8 rsvd1[11];
287};
288
289struct mlx5_wqe_signature_seg {
290 u8 rsvd0[4];
291 u8 signature;
292 u8 rsvd1[11];
293};
294
295struct mlx5_wqe_inline_seg {
296 __be32 byte_count;
297};
298
299enum mlx5_sig_type {
300 MLX5_DIF_CRC = 0x1,
301 MLX5_DIF_IPCS = 0x2,
302};
303
304struct mlx5_bsf_inl {
305 __be16 vld_refresh;
306 __be16 dif_apptag;
307 __be32 dif_reftag;
308 u8 sig_type;
309 u8 rp_inv_seed;
310 u8 rsvd[3];
311 u8 dif_inc_ref_guard_check;
312 __be16 dif_app_bitmask_check;
313};
314
315struct mlx5_bsf {
316 struct mlx5_bsf_basic {
317 u8 bsf_size_sbs;
318 u8 check_byte_mask;
319 union {
320 u8 copy_byte_mask;
321 u8 bs_selector;
322 u8 rsvd_wflags;
323 } wire;
324 union {
325 u8 bs_selector;
326 u8 rsvd_mflags;
327 } mem;
328 __be32 raw_data_size;
329 __be32 w_bfs_psv;
330 __be32 m_bfs_psv;
331 } basic;
332 struct mlx5_bsf_ext {
333 __be32 t_init_gen_pro_size;
334 __be32 rsvd_epi_size;
335 __be32 w_tfs_psv;
336 __be32 m_tfs_psv;
337 } ext;
338 struct mlx5_bsf_inl w_inl;
339 struct mlx5_bsf_inl m_inl;
340};
341
342struct mlx5_klm {
343 __be32 bcount;
344 __be32 key;
345 __be64 va;
346};
347
348struct mlx5_stride_block_entry {
349 __be16 stride;
350 __be16 bcount;
351 __be32 key;
352 __be64 va;
353};
354
355struct mlx5_stride_block_ctrl_seg {
356 __be32 bcount_per_cycle;
357 __be32 op;
358 __be32 repeat_count;
359 u16 rsvd;
360 __be16 num_entries;
361};
362
363struct mlx5_core_qp {
364 struct mlx5_core_rsc_common common; /* must be first */
365 void (*event) (struct mlx5_core_qp *, int);
366 int qpn;
367 struct mlx5_rsc_debug *dbg;
368 int pid;
369};
370
371struct mlx5_qp_path {
372 u8 fl;
373 u8 rsvd3;
374 u8 free_ar;
375 u8 pkey_index;
376 u8 rsvd0;
377 u8 grh_mlid;
378 __be16 rlid;
379 u8 ackto_lt;
380 u8 mgid_index;
381 u8 static_rate;
382 u8 hop_limit;
383 __be32 tclass_flowlabel;
384 u8 rgid[16];
385 u8 rsvd1[4];
386 u8 sl;
387 u8 port;
388 u8 rsvd2[6];
389};
390
391struct mlx5_qp_context {
392 __be32 flags;
393 __be32 flags_pd;
394 u8 mtu_msgmax;
395 u8 rq_size_stride;
396 __be16 sq_crq_size;
397 __be32 qp_counter_set_usr_page;
398 __be32 wire_qpn;
399 __be32 log_pg_sz_remote_qpn;
400 struct mlx5_qp_path pri_path;
401 struct mlx5_qp_path alt_path;
402 __be32 params1;
403 u8 reserved2[4];
404 __be32 next_send_psn;
405 __be32 cqn_send;
406 u8 reserved3[8];
407 __be32 last_acked_psn;
408 __be32 ssn;
409 __be32 params2;
410 __be32 rnr_nextrecvpsn;
411 __be32 xrcd;
412 __be32 cqn_recv;
413 __be64 db_rec_addr;
414 __be32 qkey;
415 __be32 rq_type_srqn;
416 __be32 rmsn;
417 __be16 hw_sq_wqe_counter;
418 __be16 sw_sq_wqe_counter;
419 __be16 hw_rcyclic_byte_counter;
420 __be16 hw_rq_counter;
421 __be16 sw_rcyclic_byte_counter;
422 __be16 sw_rq_counter;
423 u8 rsvd0[5];
424 u8 cgs;
425 u8 cs_req;
426 u8 cs_res;
427 __be64 dc_access_key;
428 u8 rsvd1[24];
429};
430
431struct mlx5_create_qp_mbox_in {
432 struct mlx5_inbox_hdr hdr;
433 __be32 input_qpn;
434 u8 rsvd0[4];
435 __be32 opt_param_mask;
436 u8 rsvd1[4];
437 struct mlx5_qp_context ctx;
438 u8 rsvd3[16];
439 __be64 pas[0];
440};
441
442struct mlx5_create_qp_mbox_out {
443 struct mlx5_outbox_hdr hdr;
444 __be32 qpn;
445 u8 rsvd0[4];
446};
447
448struct mlx5_destroy_qp_mbox_in {
449 struct mlx5_inbox_hdr hdr;
450 __be32 qpn;
451 u8 rsvd0[4];
452};
453
454struct mlx5_destroy_qp_mbox_out {
455 struct mlx5_outbox_hdr hdr;
456 u8 rsvd0[8];
457};
458
459struct mlx5_modify_qp_mbox_in {
460 struct mlx5_inbox_hdr hdr;
461 __be32 qpn;
462 u8 rsvd1[4];
463 __be32 optparam;
464 u8 rsvd0[4];
465 struct mlx5_qp_context ctx;
466};
467
468struct mlx5_modify_qp_mbox_out {
469 struct mlx5_outbox_hdr hdr;
470 u8 rsvd0[8];
471};
472
473struct mlx5_query_qp_mbox_in {
474 struct mlx5_inbox_hdr hdr;
475 __be32 qpn;
476 u8 rsvd[4];
477};
478
479struct mlx5_query_qp_mbox_out {
480 struct mlx5_outbox_hdr hdr;
481 u8 rsvd1[8];
482 __be32 optparam;
483 u8 rsvd0[4];
484 struct mlx5_qp_context ctx;
485 u8 rsvd2[16];
486 __be64 pas[0];
487};
488
489struct mlx5_conf_sqp_mbox_in {
490 struct mlx5_inbox_hdr hdr;
491 __be32 qpn;
492 u8 rsvd[3];
493 u8 type;
494};
495
496struct mlx5_conf_sqp_mbox_out {
497 struct mlx5_outbox_hdr hdr;
498 u8 rsvd[8];
499};
500
501struct mlx5_alloc_xrcd_mbox_in {
502 struct mlx5_inbox_hdr hdr;
503 u8 rsvd[8];
504};
505
506struct mlx5_alloc_xrcd_mbox_out {
507 struct mlx5_outbox_hdr hdr;
508 __be32 xrcdn;
509 u8 rsvd[4];
510};
511
512struct mlx5_dealloc_xrcd_mbox_in {
513 struct mlx5_inbox_hdr hdr;
514 __be32 xrcdn;
515 u8 rsvd[4];
516};
517
518struct mlx5_dealloc_xrcd_mbox_out {
519 struct mlx5_outbox_hdr hdr;
520 u8 rsvd[8];
521};
522
523static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
524{
525 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
526}
527
528static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
529{
530 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
531}
532
533int mlx5_core_create_qp(struct mlx5_core_dev *dev,
534 struct mlx5_core_qp *qp,
535 struct mlx5_create_qp_mbox_in *in,
536 int inlen);
537int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
538 enum mlx5_qp_state new_state,
539 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
540 struct mlx5_core_qp *qp);
541int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
542 struct mlx5_core_qp *qp);
543int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
544 struct mlx5_query_qp_mbox_out *out, int outlen);
545
546int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
547int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
548void mlx5_init_qp_table(struct mlx5_core_dev *dev);
549void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
550int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
551void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
552
553static inline const char *mlx5_qp_type_str(int type)
554{
555 switch (type) {
556 case MLX5_QP_ST_RC: return "RC";
557 case MLX5_QP_ST_UC: return "C";
558 case MLX5_QP_ST_UD: return "UD";
559 case MLX5_QP_ST_XRC: return "XRC";
560 case MLX5_QP_ST_MLX: return "MLX";
561 case MLX5_QP_ST_QP0: return "QP0";
562 case MLX5_QP_ST_QP1: return "QP1";
563 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
564 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
565 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
566 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
567 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
568 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
569 default: return "Invalid transport type";
570 }
571}
572
573static inline const char *mlx5_qp_state_str(int state)
574{
575 switch (state) {
576 case MLX5_QP_STATE_RST:
577 return "RST";
578 case MLX5_QP_STATE_INIT:
579 return "INIT";
580 case MLX5_QP_STATE_RTR:
581 return "RTR";
582 case MLX5_QP_STATE_RTS:
583 return "RTS";
584 case MLX5_QP_STATE_SQER:
585 return "SQER";
586 case MLX5_QP_STATE_SQD:
587 return "SQD";
588 case MLX5_QP_STATE_ERR:
589 return "ERR";
590 case MLX5_QP_STATE_SQ_DRAINING:
591 return "SQ_DRAINING";
592 case MLX5_QP_STATE_SUSPENDED:
593 return "SUSPENDED";
594 default: return "Invalid QP state";
595 }
596}
597
598#endif /* MLX5_QP_H */