tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/clk.h>
13#include <linux/mmc/host.h>
14#include <linux/mmc/dw_mmc.h>
15#include <linux/of_address.h>
16
17#include "dw_mmc.h"
18#include "dw_mmc-pltfm.h"
19
20#define RK3288_CLKGEN_DIV 2
21
22static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
23{
24 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
25}
26
27static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
28{
29 host->bus_hz /= RK3288_CLKGEN_DIV;
30
31 return 0;
32}
33
34static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
35{
36 int ret;
37 unsigned int cclkin;
38 u32 bus_hz;
39
40 /*
41 * cclkin: source clock of mmc controller
42 * bus_hz: card interface clock generated by CLKGEN
43 * bus_hz = cclkin / RK3288_CLKGEN_DIV
44 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
45 *
46 * Note: div can only be 0 or 1
47 * if DDR50 8bit mode(only emmc work in 8bit mode),
48 * div must be set 1
49 */
50 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
51 ios->timing == MMC_TIMING_MMC_DDR52)
52 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
53 else
54 cclkin = ios->clock * RK3288_CLKGEN_DIV;
55
56 ret = clk_set_rate(host->ciu_clk, cclkin);
57 if (ret)
58 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
59
60 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
61 if (bus_hz != host->bus_hz) {
62 host->bus_hz = bus_hz;
63 /* force dw_mci_setup_bus() */
64 host->current_speed = 0;
65 }
66}
67
68static const struct dw_mci_drv_data rk2928_drv_data = {
69 .prepare_command = dw_mci_rockchip_prepare_command,
70};
71
72static const struct dw_mci_drv_data rk3288_drv_data = {
73 .prepare_command = dw_mci_rockchip_prepare_command,
74 .set_ios = dw_mci_rk3288_set_ios,
75 .setup_clock = dw_mci_rk3288_setup_clock,
76};
77
78static const struct of_device_id dw_mci_rockchip_match[] = {
79 { .compatible = "rockchip,rk2928-dw-mshc",
80 .data = &rk2928_drv_data },
81 { .compatible = "rockchip,rk3288-dw-mshc",
82 .data = &rk3288_drv_data },
83 {},
84};
85MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
86
87static int dw_mci_rockchip_probe(struct platform_device *pdev)
88{
89 const struct dw_mci_drv_data *drv_data;
90 const struct of_device_id *match;
91
92 if (!pdev->dev.of_node)
93 return -ENODEV;
94
95 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
96 drv_data = match->data;
97
98 return dw_mci_pltfm_register(pdev, drv_data);
99}
100
101#ifdef CONFIG_PM_SLEEP
102static int dw_mci_rockchip_suspend(struct device *dev)
103{
104 struct dw_mci *host = dev_get_drvdata(dev);
105
106 return dw_mci_suspend(host);
107}
108
109static int dw_mci_rockchip_resume(struct device *dev)
110{
111 struct dw_mci *host = dev_get_drvdata(dev);
112
113 return dw_mci_resume(host);
114}
115#endif /* CONFIG_PM_SLEEP */
116
117static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
118 dw_mci_rockchip_suspend,
119 dw_mci_rockchip_resume);
120
121static struct platform_driver dw_mci_rockchip_pltfm_driver = {
122 .probe = dw_mci_rockchip_probe,
123 .remove = __exit_p(dw_mci_pltfm_remove),
124 .driver = {
125 .name = "dwmmc_rockchip",
126 .of_match_table = dw_mci_rockchip_match,
127 .pm = &dw_mci_rockchip_pmops,
128 },
129};
130
131module_platform_driver(dw_mci_rockchip_pltfm_driver);
132
133MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
134MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
135MODULE_ALIAS("platform:dwmmc-rockchip");
136MODULE_LICENSE("GPL v2");