Linux kernel mirror (for testing)
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
16/*
17 * SMP assumption: Options of CPU 0 are a superset of all processors.
18 * This is true for all known MIPS systems.
19 */
20#ifndef cpu_has_tlb
21#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
22#endif
23#ifndef cpu_has_tlbinv
24#define cpu_has_tlbinv (cpu_data[0].options & MIPS_CPU_TLBINV)
25#endif
26#ifndef cpu_has_segments
27#define cpu_has_segments (cpu_data[0].options & MIPS_CPU_SEGMENTS)
28#endif
29#ifndef cpu_has_eva
30#define cpu_has_eva (cpu_data[0].options & MIPS_CPU_EVA)
31#endif
32#ifndef cpu_has_htw
33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34#endif
35#ifndef cpu_has_rixiex
36#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37#endif
38#ifndef cpu_has_maar
39#define cpu_has_maar (cpu_data[0].options & MIPS_CPU_MAAR)
40#endif
41
42/*
43 * For the moment we don't consider R6000 and R8000 so we can assume that
44 * anything that doesn't support R4000-style exceptions and interrupts is
45 * R3000-like. Users should still treat these two macro definitions as
46 * opaque.
47 */
48#ifndef cpu_has_3kex
49#define cpu_has_3kex (!cpu_has_4kex)
50#endif
51#ifndef cpu_has_4kex
52#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
53#endif
54#ifndef cpu_has_3k_cache
55#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
56#endif
57#define cpu_has_6k_cache 0
58#define cpu_has_8k_cache 0
59#ifndef cpu_has_4k_cache
60#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
61#endif
62#ifndef cpu_has_tx39_cache
63#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
64#endif
65#ifndef cpu_has_octeon_cache
66#define cpu_has_octeon_cache 0
67#endif
68#ifndef cpu_has_fpu
69#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
70#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
71#else
72#define raw_cpu_has_fpu cpu_has_fpu
73#endif
74#ifndef cpu_has_32fpr
75#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
76#endif
77#ifndef cpu_has_counter
78#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
79#endif
80#ifndef cpu_has_watch
81#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
82#endif
83#ifndef cpu_has_divec
84#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
85#endif
86#ifndef cpu_has_vce
87#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
88#endif
89#ifndef cpu_has_cache_cdex_p
90#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
91#endif
92#ifndef cpu_has_cache_cdex_s
93#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
94#endif
95#ifndef cpu_has_prefetch
96#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
97#endif
98#ifndef cpu_has_mcheck
99#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
100#endif
101#ifndef cpu_has_ejtag
102#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
103#endif
104#ifndef cpu_has_llsc
105#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
106#endif
107#ifndef kernel_uses_llsc
108#define kernel_uses_llsc cpu_has_llsc
109#endif
110#ifndef cpu_has_mips16
111#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
112#endif
113#ifndef cpu_has_mdmx
114#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
115#endif
116#ifndef cpu_has_mips3d
117#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
118#endif
119#ifndef cpu_has_smartmips
120#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
121#endif
122
123#ifndef cpu_has_rixi
124# ifdef CONFIG_64BIT
125# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI)
126# else /* CONFIG_32BIT */
127# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits)
128# endif
129#endif
130
131#ifndef cpu_has_mmips
132# ifdef CONFIG_SYS_SUPPORTS_MICROMIPS
133# define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS)
134# else
135# define cpu_has_mmips 0
136# endif
137#endif
138
139#ifndef cpu_has_vtag_icache
140#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
141#endif
142#ifndef cpu_has_dc_aliases
143#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
144#endif
145#ifndef cpu_has_ic_fills_f_dc
146#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
147#endif
148#ifndef cpu_has_pindexed_dcache
149#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
150#endif
151#ifndef cpu_has_local_ebase
152#define cpu_has_local_ebase 1
153#endif
154
155/*
156 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
157 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
158 * don't. For maintaining I-cache coherency this means we need to flush the
159 * D-cache all the way back to whever the I-cache does refills from, so the
160 * I-cache has a chance to see the new data at all. Then we have to flush the
161 * I-cache also.
162 * Note we may have been rescheduled and may no longer be running on the CPU
163 * that did the store so we can't optimize this into only doing the flush on
164 * the local CPU.
165 */
166#ifndef cpu_icache_snoops_remote_store
167#ifdef CONFIG_SMP
168#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
169#else
170#define cpu_icache_snoops_remote_store 1
171#endif
172#endif
173
174#ifndef cpu_has_mips_2
175# define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II)
176#endif
177#ifndef cpu_has_mips_3
178# define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III)
179#endif
180#ifndef cpu_has_mips_4
181# define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV)
182#endif
183#ifndef cpu_has_mips_5
184# define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V)
185#endif
186#ifndef cpu_has_mips32r1
187# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
188#endif
189#ifndef cpu_has_mips32r2
190# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
191#endif
192#ifndef cpu_has_mips64r1
193# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
194#endif
195#ifndef cpu_has_mips64r2
196# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
197#endif
198
199/*
200 * Shortcuts ...
201 */
202#define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5)
203#define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5)
204#define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5)
205
206#define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
207#define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r)
208#define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r)
209#define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r)
210
211#define cpu_has_mips_4_5_r2 (cpu_has_mips_4_5 | cpu_has_mips_r2)
212
213#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
214#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
215#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
216#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
217#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
218 cpu_has_mips64r1 | cpu_has_mips64r2)
219
220#ifndef cpu_has_mips_r2_exec_hazard
221#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
222#endif
223
224/*
225 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
226 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and
227 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels
228 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
229 */
230#ifndef cpu_has_clo_clz
231#define cpu_has_clo_clz cpu_has_mips_r
232#endif
233
234/*
235 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
236 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
237 * This indicates the availability of WSBH and in case of 64 bit CPUs also
238 * DSBH and DSHD.
239 */
240#ifndef cpu_has_wsbh
241#define cpu_has_wsbh cpu_has_mips_r2
242#endif
243
244#ifndef cpu_has_dsp
245#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
246#endif
247
248#ifndef cpu_has_dsp2
249#define cpu_has_dsp2 (cpu_data[0].ases & MIPS_ASE_DSP2P)
250#endif
251
252#ifndef cpu_has_mipsmt
253#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
254#endif
255
256#ifndef cpu_has_userlocal
257#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
258#endif
259
260#ifdef CONFIG_32BIT
261# ifndef cpu_has_nofpuex
262# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
263# endif
264# ifndef cpu_has_64bits
265# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
266# endif
267# ifndef cpu_has_64bit_zero_reg
268# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
269# endif
270# ifndef cpu_has_64bit_gp_regs
271# define cpu_has_64bit_gp_regs 0
272# endif
273# ifndef cpu_has_64bit_addresses
274# define cpu_has_64bit_addresses 0
275# endif
276# ifndef cpu_vmbits
277# define cpu_vmbits 31
278# endif
279#endif
280
281#ifdef CONFIG_64BIT
282# ifndef cpu_has_nofpuex
283# define cpu_has_nofpuex 0
284# endif
285# ifndef cpu_has_64bits
286# define cpu_has_64bits 1
287# endif
288# ifndef cpu_has_64bit_zero_reg
289# define cpu_has_64bit_zero_reg 1
290# endif
291# ifndef cpu_has_64bit_gp_regs
292# define cpu_has_64bit_gp_regs 1
293# endif
294# ifndef cpu_has_64bit_addresses
295# define cpu_has_64bit_addresses 1
296# endif
297# ifndef cpu_vmbits
298# define cpu_vmbits cpu_data[0].vmbits
299# define __NEED_VMBITS_PROBE
300# endif
301#endif
302
303#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
304# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
305#elif !defined(cpu_has_vint)
306# define cpu_has_vint 0
307#endif
308
309#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
310# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
311#elif !defined(cpu_has_veic)
312# define cpu_has_veic 0
313#endif
314
315#ifndef cpu_has_inclusive_pcaches
316#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
317#endif
318
319#ifndef cpu_dcache_line_size
320#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
321#endif
322#ifndef cpu_icache_line_size
323#define cpu_icache_line_size() cpu_data[0].icache.linesz
324#endif
325#ifndef cpu_scache_line_size
326#define cpu_scache_line_size() cpu_data[0].scache.linesz
327#endif
328
329#ifndef cpu_hwrena_impl_bits
330#define cpu_hwrena_impl_bits 0
331#endif
332
333#ifndef cpu_has_perf_cntr_intr_bit
334#define cpu_has_perf_cntr_intr_bit (cpu_data[0].options & MIPS_CPU_PCI)
335#endif
336
337#ifndef cpu_has_vz
338#define cpu_has_vz (cpu_data[0].ases & MIPS_ASE_VZ)
339#endif
340
341#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
342# define cpu_has_msa (cpu_data[0].ases & MIPS_ASE_MSA)
343#elif !defined(cpu_has_msa)
344# define cpu_has_msa 0
345#endif
346
347#endif /* __ASM_CPU_FEATURES_H */