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1* Renesas R-Car generation 2 USB PHY
2
3This file provides information on what the device node for the R-Car generation
42 USB PHY contains.
5
6Required properties:
7- compatible: "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
8 "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
9- reg: offset and length of the register block.
10- #address-cells: number of address cells for the USB channel subnodes, must
11 be <1>.
12- #size-cells: number of size cells for the USB channel subnodes, must be <0>.
13- clocks: clock phandle and specifier pair.
14- clock-names: string, clock input name, must be "usbhs".
15
16The USB PHY device tree node should have the subnodes corresponding to the USB
17channels. These subnodes must contain the following properties:
18- reg: the USB controller selector; see the table below for the values.
19- #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
20
21The phandle's argument in the PHY specifier is the USB controller selector for
22the USB channel; see the selector meanings below:
23
24+-----------+---------------+---------------+
25|\ Selector | | |
26+ --------- + 0 | 1 |
27| Channel \| | |
28+-----------+---------------+---------------+
29| 0 | PCI EHCI/OHCI | HS-USB |
30| 2 | PCI EHCI/OHCI | xHCI |
31+-----------+---------------+---------------+
32
33Example (Lager board):
34
35 usb-phy@e6590100 {
36 compatible = "renesas,usb-phy-r8a7790";
37 reg = <0 0xe6590100 0 0x100>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
41 clock-names = "usbhs";
42
43 usb-channel@0 {
44 reg = <0>;
45 #phy-cells = <1>;
46 };
47 usb-channel@2 {
48 reg = <2>;
49 #phy-cells = <1>;
50 };
51 };