tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef _ASM_CRIS_IO_H
2#define _ASM_CRIS_IO_H
3
4#include <asm/page.h> /* for __va, __pa */
5#include <arch/io.h>
6#include <asm-generic/iomap.h>
7#include <linux/kernel.h>
8
9struct cris_io_operations
10{
11 u32 (*read_mem)(void *addr, int size);
12 void (*write_mem)(u32 val, int size, void *addr);
13 u32 (*read_io)(u32 port, void *addr, int size, int count);
14 void (*write_io)(u32 port, void *addr, int size, int count);
15};
16
17#ifdef CONFIG_PCI
18extern struct cris_io_operations *cris_iops;
19#else
20#define cris_iops ((struct cris_io_operations*)NULL)
21#endif
22
23/*
24 * Change virtual addresses to physical addresses and vv.
25 */
26
27static inline unsigned long virt_to_phys(volatile void * address)
28{
29 return __pa(address);
30}
31
32static inline void * phys_to_virt(unsigned long address)
33{
34 return __va(address);
35}
36
37extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
38extern void __iomem * __ioremap_prot(unsigned long phys_addr, unsigned long size, pgprot_t prot);
39
40static inline void __iomem * ioremap (unsigned long offset, unsigned long size)
41{
42 return __ioremap(offset, size, 0);
43}
44
45extern void iounmap(volatile void * __iomem addr);
46
47extern void __iomem * ioremap_nocache(unsigned long offset, unsigned long size);
48
49/*
50 * IO bus memory addresses are also 1:1 with the physical address
51 */
52#define virt_to_bus virt_to_phys
53#define bus_to_virt phys_to_virt
54
55/*
56 * readX/writeX() are used to access memory mapped devices. On some
57 * architectures the memory mapped IO stuff needs to be accessed
58 * differently. On the CRIS architecture, we just read/write the
59 * memory location directly.
60 */
61#ifdef CONFIG_PCI
62#define PCI_SPACE(x) ((((unsigned)(x)) & 0x10000000) == 0x10000000)
63#else
64#define PCI_SPACE(x) 0
65#endif
66static inline unsigned char readb(const volatile void __iomem *addr)
67{
68 if (PCI_SPACE(addr) && cris_iops)
69 return cris_iops->read_mem((void*)addr, 1);
70 else
71 return *(volatile unsigned char __force *) addr;
72}
73static inline unsigned short readw(const volatile void __iomem *addr)
74{
75 if (PCI_SPACE(addr) && cris_iops)
76 return cris_iops->read_mem((void*)addr, 2);
77 else
78 return *(volatile unsigned short __force *) addr;
79}
80static inline unsigned int readl(const volatile void __iomem *addr)
81{
82 if (PCI_SPACE(addr) && cris_iops)
83 return cris_iops->read_mem((void*)addr, 4);
84 else
85 return *(volatile unsigned int __force *) addr;
86}
87#define readb_relaxed(addr) readb(addr)
88#define readw_relaxed(addr) readw(addr)
89#define readl_relaxed(addr) readl(addr)
90#define __raw_readb readb
91#define __raw_readw readw
92#define __raw_readl readl
93
94static inline void writeb(unsigned char b, volatile void __iomem *addr)
95{
96 if (PCI_SPACE(addr) && cris_iops)
97 cris_iops->write_mem(b, 1, (void*)addr);
98 else
99 *(volatile unsigned char __force *) addr = b;
100}
101static inline void writew(unsigned short b, volatile void __iomem *addr)
102{
103 if (PCI_SPACE(addr) && cris_iops)
104 cris_iops->write_mem(b, 2, (void*)addr);
105 else
106 *(volatile unsigned short __force *) addr = b;
107}
108static inline void writel(unsigned int b, volatile void __iomem *addr)
109{
110 if (PCI_SPACE(addr) && cris_iops)
111 cris_iops->write_mem(b, 4, (void*)addr);
112 else
113 *(volatile unsigned int __force *) addr = b;
114}
115#define __raw_writeb writeb
116#define __raw_writew writew
117#define __raw_writel writel
118
119#define mmiowb()
120
121#define memset_io(a,b,c) memset((void *)(a),(b),(c))
122#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
123#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
124
125
126/* I/O port access. Normally there is no I/O space on CRIS but when
127 * Cardbus/PCI is enabled the request is passed through the bridge.
128 */
129
130#define IO_SPACE_LIMIT 0xffff
131#define inb(port) (cris_iops ? cris_iops->read_io(port,NULL,1,1) : 0)
132#define inw(port) (cris_iops ? cris_iops->read_io(port,NULL,2,1) : 0)
133#define inl(port) (cris_iops ? cris_iops->read_io(port,NULL,4,1) : 0)
134#define insb(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,1,count) : 0)
135#define insw(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,2,count) : 0)
136#define insl(port,addr,count) (cris_iops ? cris_iops->read_io(port,addr,4,count) : 0)
137static inline void outb(unsigned char data, unsigned int port)
138{
139 if (cris_iops)
140 cris_iops->write_io(port, (void *) &data, 1, 1);
141}
142static inline void outw(unsigned short data, unsigned int port)
143{
144 if (cris_iops)
145 cris_iops->write_io(port, (void *) &data, 2, 1);
146}
147static inline void outl(unsigned int data, unsigned int port)
148{
149 if (cris_iops)
150 cris_iops->write_io(port, (void *) &data, 4, 1);
151}
152static inline void outsb(unsigned int port, const void *addr,
153 unsigned long count)
154{
155 if (cris_iops)
156 cris_iops->write_io(port, (void *)addr, 1, count);
157}
158static inline void outsw(unsigned int port, const void *addr,
159 unsigned long count)
160{
161 if (cris_iops)
162 cris_iops->write_io(port, (void *)addr, 2, count);
163}
164static inline void outsl(unsigned int port, const void *addr,
165 unsigned long count)
166{
167 if (cris_iops)
168 cris_iops->write_io(port, (void *)addr, 4, count);
169}
170
171#define inb_p(port) inb(port)
172#define inw_p(port) inw(port)
173#define inl_p(port) inl(port)
174#define outb_p(val, port) outb((val), (port))
175#define outw_p(val, port) outw((val), (port))
176#define outl_p(val, port) outl((val), (port))
177
178/*
179 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
180 * access
181 */
182#define xlate_dev_mem_ptr(p) __va(p)
183
184/*
185 * Convert a virtual cached pointer to an uncached pointer
186 */
187#define xlate_dev_kmem_ptr(p) p
188
189#endif