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1* Synopsys DesignWare ABP UART
2
3Required properties:
4- compatible : "snps,dw-apb-uart"
5- reg : offset and length of the register set for the device.
6- interrupts : should contain uart interrupt.
7
8Clock handling:
9The clock rate of the input clock needs to be supplied by one of
10- clock-frequency : the input clock frequency for the UART.
11- clocks : phandle to the input clock
12
13The supplying peripheral clock can also be handled, needing a second property
14- clock-names: tuple listing input clock names.
15 Required elements: "baudclk", "apb_pclk"
16
17Optional properties:
18- resets : phandle to the parent reset controller.
19- reg-shift : quantity to shift the register offsets by. If this property is
20 not present then the register offsets are not shifted.
21- reg-io-width : the size (in bytes) of the IO accesses that should be
22 performed on the device. If this property is not present then single byte
23 accesses are used.
24
25Example:
26
27 uart@80230000 {
28 compatible = "snps,dw-apb-uart";
29 reg = <0x80230000 0x100>;
30 clock-frequency = <3686400>;
31 interrupts = <10>;
32 reg-shift = <2>;
33 reg-io-width = <4>;
34 };
35
36Example with one clock:
37
38 uart@80230000 {
39 compatible = "snps,dw-apb-uart";
40 reg = <0x80230000 0x100>;
41 clocks = <&baudclk>;
42 interrupts = <10>;
43 reg-shift = <2>;
44 reg-io-width = <4>;
45 };
46
47Example with two clocks:
48
49 uart@80230000 {
50 compatible = "snps,dw-apb-uart";
51 reg = <0x80230000 0x100>;
52 clocks = <&baudclk>, <&apb_pclk>;
53 clock-names = "baudclk", "apb_pclk";
54 interrupts = <10>;
55 reg-shift = <2>;
56 reg-io-width = <4>;
57 };