Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1#ifndef MFD_TMIO_H
2#define MFD_TMIO_H
3
4#include <linux/device.h>
5#include <linux/fb.h>
6#include <linux/io.h>
7#include <linux/jiffies.h>
8#include <linux/platform_device.h>
9#include <linux/pm_runtime.h>
10
11#define tmio_ioread8(addr) readb(addr)
12#define tmio_ioread16(addr) readw(addr)
13#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
14#define tmio_ioread32(addr) \
15 (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
16
17#define tmio_iowrite8(val, addr) writeb((val), (addr))
18#define tmio_iowrite16(val, addr) writew((val), (addr))
19#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
20#define tmio_iowrite32(val, addr) \
21 do { \
22 writew((val), (addr)); \
23 writew((val) >> 16, (addr) + 2); \
24 } while (0)
25
26#define CNF_CMD 0x04
27#define CNF_CTL_BASE 0x10
28#define CNF_INT_PIN 0x3d
29#define CNF_STOP_CLK_CTL 0x40
30#define CNF_GCLK_CTL 0x41
31#define CNF_SD_CLK_MODE 0x42
32#define CNF_PIN_STATUS 0x44
33#define CNF_PWR_CTL_1 0x48
34#define CNF_PWR_CTL_2 0x49
35#define CNF_PWR_CTL_3 0x4a
36#define CNF_CARD_DETECT_MODE 0x4c
37#define CNF_SD_SLOT 0x50
38#define CNF_EXT_GCLK_CTL_1 0xf0
39#define CNF_EXT_GCLK_CTL_2 0xf1
40#define CNF_EXT_GCLK_CTL_3 0xf9
41#define CNF_SD_LED_EN_1 0xfa
42#define CNF_SD_LED_EN_2 0xfe
43
44#define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
45
46#define sd_config_write8(base, shift, reg, val) \
47 tmio_iowrite8((val), (base) + ((reg) << (shift)))
48#define sd_config_write16(base, shift, reg, val) \
49 tmio_iowrite16((val), (base) + ((reg) << (shift)))
50#define sd_config_write32(base, shift, reg, val) \
51 do { \
52 tmio_iowrite16((val), (base) + ((reg) << (shift))); \
53 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
54 } while (0)
55
56/* tmio MMC platform flags */
57#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
58/*
59 * Some controllers can support a 2-byte block size when the bus width
60 * is configured in 4-bit mode.
61 */
62#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
63/*
64 * Some controllers can support SDIO IRQ signalling.
65 */
66#define TMIO_MMC_SDIO_IRQ (1 << 2)
67/*
68 * Some controllers require waiting for the SD bus to become
69 * idle before writing to some registers.
70 */
71#define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
72/*
73 * A GPIO is used for card hotplug detection. We need an extra flag for this,
74 * because 0 is a valid GPIO number too, and requiring users to specify
75 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
76 */
77#define TMIO_MMC_USE_GPIO_CD (1 << 5)
78
79/*
80 * Some controllers doesn't have over 0x100 register.
81 * it is used to checking accessibility of
82 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
83 */
84#define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
85
86int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
87int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
88void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
89void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
90
91struct dma_chan;
92
93struct tmio_mmc_dma {
94 void *chan_priv_tx;
95 void *chan_priv_rx;
96 int slave_id_tx;
97 int slave_id_rx;
98 int alignment_shift;
99 bool (*filter)(struct dma_chan *chan, void *arg);
100};
101
102struct tmio_mmc_host;
103
104/*
105 * data for the MMC controller
106 */
107struct tmio_mmc_data {
108 unsigned int hclk;
109 unsigned long capabilities;
110 unsigned long capabilities2;
111 unsigned long flags;
112 unsigned long bus_shift;
113 u32 ocr_mask; /* available voltages */
114 struct tmio_mmc_dma *dma;
115 struct device *dev;
116 unsigned int cd_gpio;
117 void (*set_pwr)(struct platform_device *host, int state);
118 void (*set_clk_div)(struct platform_device *host, int state);
119 int (*write16_hook)(struct tmio_mmc_host *host, int addr);
120 /* clock management callbacks */
121 int (*clk_enable)(struct platform_device *pdev, unsigned int *f);
122 void (*clk_disable)(struct platform_device *pdev);
123};
124
125/*
126 * data for the NAND controller
127 */
128struct tmio_nand_data {
129 struct nand_bbt_descr *badblock_pattern;
130 struct mtd_partition *partition;
131 unsigned int num_partitions;
132};
133
134#define FBIO_TMIO_ACC_WRITE 0x7C639300
135#define FBIO_TMIO_ACC_SYNC 0x7C639301
136
137struct tmio_fb_data {
138 int (*lcd_set_power)(struct platform_device *fb_dev,
139 bool on);
140 int (*lcd_mode)(struct platform_device *fb_dev,
141 const struct fb_videomode *mode);
142 int num_modes;
143 struct fb_videomode *modes;
144
145 /* in mm: size of screen */
146 int height;
147 int width;
148};
149
150
151#endif