tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1#ifndef DW_SPI_HEADER_H
2#define DW_SPI_HEADER_H
3
4#include <linux/io.h>
5#include <linux/scatterlist.h>
6#include <linux/gpio.h>
7
8/* Register offsets */
9#define DW_SPI_CTRL0 0x00
10#define DW_SPI_CTRL1 0x04
11#define DW_SPI_SSIENR 0x08
12#define DW_SPI_MWCR 0x0c
13#define DW_SPI_SER 0x10
14#define DW_SPI_BAUDR 0x14
15#define DW_SPI_TXFLTR 0x18
16#define DW_SPI_RXFLTR 0x1c
17#define DW_SPI_TXFLR 0x20
18#define DW_SPI_RXFLR 0x24
19#define DW_SPI_SR 0x28
20#define DW_SPI_IMR 0x2c
21#define DW_SPI_ISR 0x30
22#define DW_SPI_RISR 0x34
23#define DW_SPI_TXOICR 0x38
24#define DW_SPI_RXOICR 0x3c
25#define DW_SPI_RXUICR 0x40
26#define DW_SPI_MSTICR 0x44
27#define DW_SPI_ICR 0x48
28#define DW_SPI_DMACR 0x4c
29#define DW_SPI_DMATDLR 0x50
30#define DW_SPI_DMARDLR 0x54
31#define DW_SPI_IDR 0x58
32#define DW_SPI_VERSION 0x5c
33#define DW_SPI_DR 0x60
34
35/* Bit fields in CTRLR0 */
36#define SPI_DFS_OFFSET 0
37
38#define SPI_FRF_OFFSET 4
39#define SPI_FRF_SPI 0x0
40#define SPI_FRF_SSP 0x1
41#define SPI_FRF_MICROWIRE 0x2
42#define SPI_FRF_RESV 0x3
43
44#define SPI_MODE_OFFSET 6
45#define SPI_SCPH_OFFSET 6
46#define SPI_SCOL_OFFSET 7
47
48#define SPI_TMOD_OFFSET 8
49#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
50#define SPI_TMOD_TR 0x0 /* xmit & recv */
51#define SPI_TMOD_TO 0x1 /* xmit only */
52#define SPI_TMOD_RO 0x2 /* recv only */
53#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
54
55#define SPI_SLVOE_OFFSET 10
56#define SPI_SRL_OFFSET 11
57#define SPI_CFS_OFFSET 12
58
59/* Bit fields in SR, 7 bits */
60#define SR_MASK 0x7f /* cover 7 bits */
61#define SR_BUSY (1 << 0)
62#define SR_TF_NOT_FULL (1 << 1)
63#define SR_TF_EMPT (1 << 2)
64#define SR_RF_NOT_EMPT (1 << 3)
65#define SR_RF_FULL (1 << 4)
66#define SR_TX_ERR (1 << 5)
67#define SR_DCOL (1 << 6)
68
69/* Bit fields in ISR, IMR, RISR, 7 bits */
70#define SPI_INT_TXEI (1 << 0)
71#define SPI_INT_TXOI (1 << 1)
72#define SPI_INT_RXUI (1 << 2)
73#define SPI_INT_RXOI (1 << 3)
74#define SPI_INT_RXFI (1 << 4)
75#define SPI_INT_MSTI (1 << 5)
76
77/* TX RX interrupt level threshold, max can be 256 */
78#define SPI_INT_THRESHOLD 32
79
80enum dw_ssi_type {
81 SSI_MOTO_SPI = 0,
82 SSI_TI_SSP,
83 SSI_NS_MICROWIRE,
84};
85
86struct dw_spi;
87struct dw_spi_dma_ops {
88 int (*dma_init)(struct dw_spi *dws);
89 void (*dma_exit)(struct dw_spi *dws);
90 int (*dma_transfer)(struct dw_spi *dws, int cs_change);
91};
92
93struct dw_spi {
94 struct spi_master *master;
95 struct spi_device *cur_dev;
96 enum dw_ssi_type type;
97 char name[16];
98
99 void __iomem *regs;
100 unsigned long paddr;
101 int irq;
102 u32 fifo_len; /* depth of the FIFO buffer */
103 u32 max_freq; /* max bus freq supported */
104
105 u16 bus_num;
106 u16 num_cs; /* supported slave numbers */
107
108 /* Message Transfer pump */
109 struct tasklet_struct pump_transfers;
110
111 /* Current message transfer state info */
112 struct spi_message *cur_msg;
113 struct spi_transfer *cur_transfer;
114 struct chip_data *cur_chip;
115 struct chip_data *prev_chip;
116 size_t len;
117 void *tx;
118 void *tx_end;
119 void *rx;
120 void *rx_end;
121 int dma_mapped;
122 dma_addr_t rx_dma;
123 dma_addr_t tx_dma;
124 size_t rx_map_len;
125 size_t tx_map_len;
126 u8 n_bytes; /* current is a 1/2 bytes op */
127 u8 max_bits_per_word; /* maxim is 16b */
128 u32 dma_width;
129 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
130 void (*cs_control)(u32 command);
131
132 /* Dma info */
133 int dma_inited;
134 struct dma_chan *txchan;
135 struct scatterlist tx_sgl;
136 struct dma_chan *rxchan;
137 struct scatterlist rx_sgl;
138 int dma_chan_done;
139 struct device *dma_dev;
140 dma_addr_t dma_addr; /* phy address of the Data register */
141 struct dw_spi_dma_ops *dma_ops;
142 void *dma_priv; /* platform relate info */
143 struct pci_dev *dmac;
144
145 /* Bus interface info */
146 void *priv;
147#ifdef CONFIG_DEBUG_FS
148 struct dentry *debugfs;
149#endif
150};
151
152static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
153{
154 return __raw_readl(dws->regs + offset);
155}
156
157static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
158{
159 __raw_writel(val, dws->regs + offset);
160}
161
162static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
163{
164 return __raw_readw(dws->regs + offset);
165}
166
167static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
168{
169 __raw_writew(val, dws->regs + offset);
170}
171
172static inline void spi_enable_chip(struct dw_spi *dws, int enable)
173{
174 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
175}
176
177static inline void spi_set_clk(struct dw_spi *dws, u16 div)
178{
179 dw_writel(dws, DW_SPI_BAUDR, div);
180}
181
182static inline void spi_chip_sel(struct dw_spi *dws, struct spi_device *spi,
183 int active)
184{
185 u16 cs = spi->chip_select;
186 int gpio_val = active ? (spi->mode & SPI_CS_HIGH) :
187 !(spi->mode & SPI_CS_HIGH);
188
189 if (dws->cs_control)
190 dws->cs_control(active);
191 if (gpio_is_valid(spi->cs_gpio))
192 gpio_set_value(spi->cs_gpio, gpio_val);
193
194 if (active)
195 dw_writel(dws, DW_SPI_SER, 1 << cs);
196}
197
198/* Disable IRQ bits */
199static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
200{
201 u32 new_mask;
202
203 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
204 dw_writel(dws, DW_SPI_IMR, new_mask);
205}
206
207/* Enable IRQ bits */
208static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
209{
210 u32 new_mask;
211
212 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
213 dw_writel(dws, DW_SPI_IMR, new_mask);
214}
215
216/*
217 * Each SPI slave device to work with dw_api controller should
218 * has such a structure claiming its working mode (PIO/DMA etc),
219 * which can be save in the "controller_data" member of the
220 * struct spi_device
221 */
222struct dw_spi_chip {
223 u8 poll_mode; /* 0 for contoller polling mode */
224 u8 type; /* SPI/SSP/Micrwire */
225 u8 enable_dma;
226 void (*cs_control)(u32 command);
227};
228
229extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
230extern void dw_spi_remove_host(struct dw_spi *dws);
231extern int dw_spi_suspend_host(struct dw_spi *dws);
232extern int dw_spi_resume_host(struct dw_spi *dws);
233extern void dw_spi_xfer_done(struct dw_spi *dws);
234
235/* platform related setup */
236extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
237#endif /* DW_SPI_HEADER_H */