tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/interrupt.h>
35
36#include "shpchp.h"
37
38/* Slot Available Register I field definition */
39#define SLOT_33MHZ 0x0000001f
40#define SLOT_66MHZ_PCIX 0x00001f00
41#define SLOT_100MHZ_PCIX 0x001f0000
42#define SLOT_133MHZ_PCIX 0x1f000000
43
44/* Slot Available Register II field definition */
45#define SLOT_66MHZ 0x0000001f
46#define SLOT_66MHZ_PCIX_266 0x00000f00
47#define SLOT_100MHZ_PCIX_266 0x0000f000
48#define SLOT_133MHZ_PCIX_266 0x000f0000
49#define SLOT_66MHZ_PCIX_533 0x00f00000
50#define SLOT_100MHZ_PCIX_533 0x0f000000
51#define SLOT_133MHZ_PCIX_533 0xf0000000
52
53/* Slot Configuration */
54#define SLOT_NUM 0x0000001F
55#define FIRST_DEV_NUM 0x00001F00
56#define PSN 0x07FF0000
57#define UPDOWN 0x20000000
58#define MRLSENSOR 0x40000000
59#define ATTN_BUTTON 0x80000000
60
61/*
62 * Interrupt Locator Register definitions
63 */
64#define CMD_INTR_PENDING (1 << 0)
65#define SLOT_INTR_PENDING(i) (1 << (i + 1))
66
67/*
68 * Controller SERR-INT Register
69 */
70#define GLOBAL_INTR_MASK (1 << 0)
71#define GLOBAL_SERR_MASK (1 << 1)
72#define COMMAND_INTR_MASK (1 << 2)
73#define ARBITER_SERR_MASK (1 << 3)
74#define COMMAND_DETECTED (1 << 16)
75#define ARBITER_DETECTED (1 << 17)
76#define SERR_INTR_RSVDZ_MASK 0xfffc0000
77
78/*
79 * Logical Slot Register definitions
80 */
81#define SLOT_REG(i) (SLOT1 + (4 * i))
82
83#define SLOT_STATE_SHIFT (0)
84#define SLOT_STATE_MASK (3 << 0)
85#define SLOT_STATE_PWRONLY (1)
86#define SLOT_STATE_ENABLED (2)
87#define SLOT_STATE_DISABLED (3)
88#define PWR_LED_STATE_SHIFT (2)
89#define PWR_LED_STATE_MASK (3 << 2)
90#define ATN_LED_STATE_SHIFT (4)
91#define ATN_LED_STATE_MASK (3 << 4)
92#define ATN_LED_STATE_ON (1)
93#define ATN_LED_STATE_BLINK (2)
94#define ATN_LED_STATE_OFF (3)
95#define POWER_FAULT (1 << 6)
96#define ATN_BUTTON (1 << 7)
97#define MRL_SENSOR (1 << 8)
98#define MHZ66_CAP (1 << 9)
99#define PRSNT_SHIFT (10)
100#define PRSNT_MASK (3 << 10)
101#define PCIX_CAP_SHIFT (12)
102#define PCIX_CAP_MASK_PI1 (3 << 12)
103#define PCIX_CAP_MASK_PI2 (7 << 12)
104#define PRSNT_CHANGE_DETECTED (1 << 16)
105#define ISO_PFAULT_DETECTED (1 << 17)
106#define BUTTON_PRESS_DETECTED (1 << 18)
107#define MRL_CHANGE_DETECTED (1 << 19)
108#define CON_PFAULT_DETECTED (1 << 20)
109#define PRSNT_CHANGE_INTR_MASK (1 << 24)
110#define ISO_PFAULT_INTR_MASK (1 << 25)
111#define BUTTON_PRESS_INTR_MASK (1 << 26)
112#define MRL_CHANGE_INTR_MASK (1 << 27)
113#define CON_PFAULT_INTR_MASK (1 << 28)
114#define MRL_CHANGE_SERR_MASK (1 << 29)
115#define CON_PFAULT_SERR_MASK (1 << 30)
116#define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
117
118/*
119 * SHPC Command Code definitions
120 *
121 * Slot Operation 00h - 3Fh
122 * Set Bus Segment Speed/Mode A 40h - 47h
123 * Power-Only All Slots 48h
124 * Enable All Slots 49h
125 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
126 * Reserved Command Codes 60h - BFh
127 * Vendor Specific Commands C0h - FFh
128 */
129#define SET_SLOT_PWR 0x01 /* Slot Operation */
130#define SET_SLOT_ENABLE 0x02
131#define SET_SLOT_DISABLE 0x03
132#define SET_PWR_ON 0x04
133#define SET_PWR_BLINK 0x08
134#define SET_PWR_OFF 0x0c
135#define SET_ATTN_ON 0x10
136#define SET_ATTN_BLINK 0x20
137#define SET_ATTN_OFF 0x30
138#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
139#define SETA_PCI_66MHZ 0x41
140#define SETA_PCIX_66MHZ 0x42
141#define SETA_PCIX_100MHZ 0x43
142#define SETA_PCIX_133MHZ 0x44
143#define SETA_RESERVED1 0x45
144#define SETA_RESERVED2 0x46
145#define SETA_RESERVED3 0x47
146#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
147#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
148#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
149#define SETB_PCI_66MHZ 0x51
150#define SETB_PCIX_66MHZ_PM 0x52
151#define SETB_PCIX_100MHZ_PM 0x53
152#define SETB_PCIX_133MHZ_PM 0x54
153#define SETB_PCIX_66MHZ_EM 0x55
154#define SETB_PCIX_100MHZ_EM 0x56
155#define SETB_PCIX_133MHZ_EM 0x57
156#define SETB_PCIX_66MHZ_266 0x58
157#define SETB_PCIX_100MHZ_266 0x59
158#define SETB_PCIX_133MHZ_266 0x5a
159#define SETB_PCIX_66MHZ_533 0x5b
160#define SETB_PCIX_100MHZ_533 0x5c
161#define SETB_PCIX_133MHZ_533 0x5d
162#define SETB_RESERVED1 0x5e
163#define SETB_RESERVED2 0x5f
164
165/*
166 * SHPC controller command error code
167 */
168#define SWITCH_OPEN 0x1
169#define INVALID_CMD 0x2
170#define INVALID_SPEED_MODE 0x4
171
172/*
173 * For accessing SHPC Working Register Set via PCI Configuration Space
174 */
175#define DWORD_SELECT 0x2
176#define DWORD_DATA 0x4
177
178/* Field Offset in Logical Slot Register - byte boundary */
179#define SLOT_EVENT_LATCH 0x2
180#define SLOT_SERR_INT_MASK 0x3
181
182static irqreturn_t shpc_isr(int irq, void *dev_id);
183static void start_int_poll_timer(struct controller *ctrl, int sec);
184static int hpc_check_cmd_status(struct controller *ctrl);
185
186static inline u8 shpc_readb(struct controller *ctrl, int reg)
187{
188 return readb(ctrl->creg + reg);
189}
190
191static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
192{
193 writeb(val, ctrl->creg + reg);
194}
195
196static inline u16 shpc_readw(struct controller *ctrl, int reg)
197{
198 return readw(ctrl->creg + reg);
199}
200
201static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
202{
203 writew(val, ctrl->creg + reg);
204}
205
206static inline u32 shpc_readl(struct controller *ctrl, int reg)
207{
208 return readl(ctrl->creg + reg);
209}
210
211static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
212{
213 writel(val, ctrl->creg + reg);
214}
215
216static inline int shpc_indirect_read(struct controller *ctrl, int index,
217 u32 *value)
218{
219 int rc;
220 u32 cap_offset = ctrl->cap_offset;
221 struct pci_dev *pdev = ctrl->pci_dev;
222
223 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
224 if (rc)
225 return rc;
226 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
227}
228
229/*
230 * This is the interrupt polling timeout function.
231 */
232static void int_poll_timeout(unsigned long data)
233{
234 struct controller *ctrl = (struct controller *)data;
235
236 /* Poll for interrupt events. regs == NULL => polling */
237 shpc_isr(0, ctrl);
238
239 init_timer(&ctrl->poll_timer);
240 if (!shpchp_poll_time)
241 shpchp_poll_time = 2; /* default polling interval is 2 sec */
242
243 start_int_poll_timer(ctrl, shpchp_poll_time);
244}
245
246/*
247 * This function starts the interrupt polling timer.
248 */
249static void start_int_poll_timer(struct controller *ctrl, int sec)
250{
251 /* Clamp to sane value */
252 if ((sec <= 0) || (sec > 60))
253 sec = 2;
254
255 ctrl->poll_timer.function = &int_poll_timeout;
256 ctrl->poll_timer.data = (unsigned long)ctrl;
257 ctrl->poll_timer.expires = jiffies + sec * HZ;
258 add_timer(&ctrl->poll_timer);
259}
260
261static inline int is_ctrl_busy(struct controller *ctrl)
262{
263 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
264 return cmd_status & 0x1;
265}
266
267/*
268 * Returns 1 if SHPC finishes executing a command within 1 sec,
269 * otherwise returns 0.
270 */
271static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
272{
273 int i;
274
275 if (!is_ctrl_busy(ctrl))
276 return 1;
277
278 /* Check every 0.1 sec for a total of 1 sec */
279 for (i = 0; i < 10; i++) {
280 msleep(100);
281 if (!is_ctrl_busy(ctrl))
282 return 1;
283 }
284
285 return 0;
286}
287
288static inline int shpc_wait_cmd(struct controller *ctrl)
289{
290 int retval = 0;
291 unsigned long timeout = msecs_to_jiffies(1000);
292 int rc;
293
294 if (shpchp_poll_mode)
295 rc = shpc_poll_ctrl_busy(ctrl);
296 else
297 rc = wait_event_interruptible_timeout(ctrl->queue,
298 !is_ctrl_busy(ctrl), timeout);
299 if (!rc && is_ctrl_busy(ctrl)) {
300 retval = -EIO;
301 ctrl_err(ctrl, "Command not completed in 1000 msec\n");
302 } else if (rc < 0) {
303 retval = -EINTR;
304 ctrl_info(ctrl, "Command was interrupted by a signal\n");
305 }
306
307 return retval;
308}
309
310static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
311{
312 struct controller *ctrl = slot->ctrl;
313 u16 cmd_status;
314 int retval = 0;
315 u16 temp_word;
316
317 mutex_lock(&slot->ctrl->cmd_lock);
318
319 if (!shpc_poll_ctrl_busy(ctrl)) {
320 /* After 1 sec and and the controller is still busy */
321 ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
322 retval = -EBUSY;
323 goto out;
324 }
325
326 ++t_slot;
327 temp_word = (t_slot << 8) | (cmd & 0xFF);
328 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
329
330 /* To make sure the Controller Busy bit is 0 before we send out the
331 * command.
332 */
333 shpc_writew(ctrl, CMD, temp_word);
334
335 /*
336 * Wait for command completion.
337 */
338 retval = shpc_wait_cmd(slot->ctrl);
339 if (retval)
340 goto out;
341
342 cmd_status = hpc_check_cmd_status(slot->ctrl);
343 if (cmd_status) {
344 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
345 cmd, cmd_status);
346 retval = -EIO;
347 }
348 out:
349 mutex_unlock(&slot->ctrl->cmd_lock);
350 return retval;
351}
352
353static int hpc_check_cmd_status(struct controller *ctrl)
354{
355 int retval = 0;
356 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
357
358 switch (cmd_status >> 1) {
359 case 0:
360 retval = 0;
361 break;
362 case 1:
363 retval = SWITCH_OPEN;
364 ctrl_err(ctrl, "Switch opened!\n");
365 break;
366 case 2:
367 retval = INVALID_CMD;
368 ctrl_err(ctrl, "Invalid HPC command!\n");
369 break;
370 case 4:
371 retval = INVALID_SPEED_MODE;
372 ctrl_err(ctrl, "Invalid bus speed/mode!\n");
373 break;
374 default:
375 retval = cmd_status;
376 }
377
378 return retval;
379}
380
381
382static int hpc_get_attention_status(struct slot *slot, u8 *status)
383{
384 struct controller *ctrl = slot->ctrl;
385 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
386 u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
387
388 switch (state) {
389 case ATN_LED_STATE_ON:
390 *status = 1; /* On */
391 break;
392 case ATN_LED_STATE_BLINK:
393 *status = 2; /* Blink */
394 break;
395 case ATN_LED_STATE_OFF:
396 *status = 0; /* Off */
397 break;
398 default:
399 *status = 0xFF; /* Reserved */
400 break;
401 }
402
403 return 0;
404}
405
406static int hpc_get_power_status(struct slot *slot, u8 *status)
407{
408 struct controller *ctrl = slot->ctrl;
409 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
410 u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
411
412 switch (state) {
413 case SLOT_STATE_PWRONLY:
414 *status = 2; /* Powered only */
415 break;
416 case SLOT_STATE_ENABLED:
417 *status = 1; /* Enabled */
418 break;
419 case SLOT_STATE_DISABLED:
420 *status = 0; /* Disabled */
421 break;
422 default:
423 *status = 0xFF; /* Reserved */
424 break;
425 }
426
427 return 0;
428}
429
430
431static int hpc_get_latch_status(struct slot *slot, u8 *status)
432{
433 struct controller *ctrl = slot->ctrl;
434 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
435
436 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
437
438 return 0;
439}
440
441static int hpc_get_adapter_status(struct slot *slot, u8 *status)
442{
443 struct controller *ctrl = slot->ctrl;
444 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
445 u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
446
447 *status = (state != 0x3) ? 1 : 0;
448
449 return 0;
450}
451
452static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
453{
454 struct controller *ctrl = slot->ctrl;
455
456 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
457
458 return 0;
459}
460
461static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
462{
463 int retval = 0;
464 struct controller *ctrl = slot->ctrl;
465 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
466 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
467 u8 pi, pcix_cap;
468
469 if ((retval = hpc_get_prog_int(slot, &pi)))
470 return retval;
471
472 switch (pi) {
473 case 1:
474 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
475 break;
476 case 2:
477 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
478 break;
479 default:
480 return -ENODEV;
481 }
482
483 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
484 __func__, slot_reg, pcix_cap, m66_cap);
485
486 switch (pcix_cap) {
487 case 0x0:
488 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
489 break;
490 case 0x1:
491 *value = PCI_SPEED_66MHz_PCIX;
492 break;
493 case 0x3:
494 *value = PCI_SPEED_133MHz_PCIX;
495 break;
496 case 0x4:
497 *value = PCI_SPEED_133MHz_PCIX_266;
498 break;
499 case 0x5:
500 *value = PCI_SPEED_133MHz_PCIX_533;
501 break;
502 case 0x2:
503 default:
504 *value = PCI_SPEED_UNKNOWN;
505 retval = -ENODEV;
506 break;
507 }
508
509 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
510 return retval;
511}
512
513static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
514{
515 int retval = 0;
516 struct controller *ctrl = slot->ctrl;
517 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
518 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
519
520 if (pi == 2) {
521 *mode = (sec_bus_status & 0x0100) >> 8;
522 } else {
523 retval = -1;
524 }
525
526 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
527 return retval;
528}
529
530static int hpc_query_power_fault(struct slot *slot)
531{
532 struct controller *ctrl = slot->ctrl;
533 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
534
535 /* Note: Logic 0 => fault */
536 return !(slot_reg & POWER_FAULT);
537}
538
539static int hpc_set_attention_status(struct slot *slot, u8 value)
540{
541 u8 slot_cmd = 0;
542
543 switch (value) {
544 case 0 :
545 slot_cmd = SET_ATTN_OFF; /* OFF */
546 break;
547 case 1:
548 slot_cmd = SET_ATTN_ON; /* ON */
549 break;
550 case 2:
551 slot_cmd = SET_ATTN_BLINK; /* BLINK */
552 break;
553 default:
554 return -1;
555 }
556
557 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
558}
559
560
561static void hpc_set_green_led_on(struct slot *slot)
562{
563 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
564}
565
566static void hpc_set_green_led_off(struct slot *slot)
567{
568 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
569}
570
571static void hpc_set_green_led_blink(struct slot *slot)
572{
573 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
574}
575
576static void hpc_release_ctlr(struct controller *ctrl)
577{
578 int i;
579 u32 slot_reg, serr_int;
580
581 /*
582 * Mask event interrupts and SERRs of all slots
583 */
584 for (i = 0; i < ctrl->num_slots; i++) {
585 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
586 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
587 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
588 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
589 CON_PFAULT_SERR_MASK);
590 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
591 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
592 }
593
594 cleanup_slots(ctrl);
595
596 /*
597 * Mask SERR and System Interrupt generation
598 */
599 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
600 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
601 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
602 serr_int &= ~SERR_INTR_RSVDZ_MASK;
603 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
604
605 if (shpchp_poll_mode)
606 del_timer(&ctrl->poll_timer);
607 else {
608 free_irq(ctrl->pci_dev->irq, ctrl);
609 pci_disable_msi(ctrl->pci_dev);
610 }
611
612 iounmap(ctrl->creg);
613 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
614}
615
616static int hpc_power_on_slot(struct slot *slot)
617{
618 int retval;
619
620 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
621 if (retval)
622 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
623
624 return retval;
625}
626
627static int hpc_slot_enable(struct slot *slot)
628{
629 int retval;
630
631 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
632 retval = shpc_write_cmd(slot, slot->hp_slot,
633 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
634 if (retval)
635 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
636
637 return retval;
638}
639
640static int hpc_slot_disable(struct slot *slot)
641{
642 int retval;
643
644 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
645 retval = shpc_write_cmd(slot, slot->hp_slot,
646 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
647 if (retval)
648 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
649
650 return retval;
651}
652
653static int shpc_get_cur_bus_speed(struct controller *ctrl)
654{
655 int retval = 0;
656 struct pci_bus *bus = ctrl->pci_dev->subordinate;
657 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
658 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
659 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
660 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
661
662 if ((pi == 1) && (speed_mode > 4)) {
663 retval = -ENODEV;
664 goto out;
665 }
666
667 switch (speed_mode) {
668 case 0x0:
669 bus_speed = PCI_SPEED_33MHz;
670 break;
671 case 0x1:
672 bus_speed = PCI_SPEED_66MHz;
673 break;
674 case 0x2:
675 bus_speed = PCI_SPEED_66MHz_PCIX;
676 break;
677 case 0x3:
678 bus_speed = PCI_SPEED_100MHz_PCIX;
679 break;
680 case 0x4:
681 bus_speed = PCI_SPEED_133MHz_PCIX;
682 break;
683 case 0x5:
684 bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
685 break;
686 case 0x6:
687 bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
688 break;
689 case 0x7:
690 bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
691 break;
692 case 0x8:
693 bus_speed = PCI_SPEED_66MHz_PCIX_266;
694 break;
695 case 0x9:
696 bus_speed = PCI_SPEED_100MHz_PCIX_266;
697 break;
698 case 0xa:
699 bus_speed = PCI_SPEED_133MHz_PCIX_266;
700 break;
701 case 0xb:
702 bus_speed = PCI_SPEED_66MHz_PCIX_533;
703 break;
704 case 0xc:
705 bus_speed = PCI_SPEED_100MHz_PCIX_533;
706 break;
707 case 0xd:
708 bus_speed = PCI_SPEED_133MHz_PCIX_533;
709 break;
710 default:
711 retval = -ENODEV;
712 break;
713 }
714
715 out:
716 bus->cur_bus_speed = bus_speed;
717 dbg("Current bus speed = %d\n", bus_speed);
718 return retval;
719}
720
721
722static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value)
723{
724 int retval;
725 struct controller *ctrl = slot->ctrl;
726 u8 pi, cmd;
727
728 pi = shpc_readb(ctrl, PROG_INTERFACE);
729 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
730 return -EINVAL;
731
732 switch (value) {
733 case PCI_SPEED_33MHz:
734 cmd = SETA_PCI_33MHZ;
735 break;
736 case PCI_SPEED_66MHz:
737 cmd = SETA_PCI_66MHZ;
738 break;
739 case PCI_SPEED_66MHz_PCIX:
740 cmd = SETA_PCIX_66MHZ;
741 break;
742 case PCI_SPEED_100MHz_PCIX:
743 cmd = SETA_PCIX_100MHZ;
744 break;
745 case PCI_SPEED_133MHz_PCIX:
746 cmd = SETA_PCIX_133MHZ;
747 break;
748 case PCI_SPEED_66MHz_PCIX_ECC:
749 cmd = SETB_PCIX_66MHZ_EM;
750 break;
751 case PCI_SPEED_100MHz_PCIX_ECC:
752 cmd = SETB_PCIX_100MHZ_EM;
753 break;
754 case PCI_SPEED_133MHz_PCIX_ECC:
755 cmd = SETB_PCIX_133MHZ_EM;
756 break;
757 case PCI_SPEED_66MHz_PCIX_266:
758 cmd = SETB_PCIX_66MHZ_266;
759 break;
760 case PCI_SPEED_100MHz_PCIX_266:
761 cmd = SETB_PCIX_100MHZ_266;
762 break;
763 case PCI_SPEED_133MHz_PCIX_266:
764 cmd = SETB_PCIX_133MHZ_266;
765 break;
766 case PCI_SPEED_66MHz_PCIX_533:
767 cmd = SETB_PCIX_66MHZ_533;
768 break;
769 case PCI_SPEED_100MHz_PCIX_533:
770 cmd = SETB_PCIX_100MHZ_533;
771 break;
772 case PCI_SPEED_133MHz_PCIX_533:
773 cmd = SETB_PCIX_133MHZ_533;
774 break;
775 default:
776 return -EINVAL;
777 }
778
779 retval = shpc_write_cmd(slot, 0, cmd);
780 if (retval)
781 ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
782 else
783 shpc_get_cur_bus_speed(ctrl);
784
785 return retval;
786}
787
788static irqreturn_t shpc_isr(int irq, void *dev_id)
789{
790 struct controller *ctrl = (struct controller *)dev_id;
791 u32 serr_int, slot_reg, intr_loc, intr_loc2;
792 int hp_slot;
793
794 /* Check to see if it was our interrupt */
795 intr_loc = shpc_readl(ctrl, INTR_LOC);
796 if (!intr_loc)
797 return IRQ_NONE;
798
799 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
800
801 if(!shpchp_poll_mode) {
802 /*
803 * Mask Global Interrupt Mask - see implementation
804 * note on p. 139 of SHPC spec rev 1.0
805 */
806 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
807 serr_int |= GLOBAL_INTR_MASK;
808 serr_int &= ~SERR_INTR_RSVDZ_MASK;
809 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
810
811 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
812 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
813 }
814
815 if (intr_loc & CMD_INTR_PENDING) {
816 /*
817 * Command Complete Interrupt Pending
818 * RO only - clear by writing 1 to the Command Completion
819 * Detect bit in Controller SERR-INT register
820 */
821 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
822 serr_int &= ~SERR_INTR_RSVDZ_MASK;
823 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
824
825 wake_up_interruptible(&ctrl->queue);
826 }
827
828 if (!(intr_loc & ~CMD_INTR_PENDING))
829 goto out;
830
831 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
832 /* To find out which slot has interrupt pending */
833 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
834 continue;
835
836 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
837 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
838 hp_slot, slot_reg);
839
840 if (slot_reg & MRL_CHANGE_DETECTED)
841 shpchp_handle_switch_change(hp_slot, ctrl);
842
843 if (slot_reg & BUTTON_PRESS_DETECTED)
844 shpchp_handle_attention_button(hp_slot, ctrl);
845
846 if (slot_reg & PRSNT_CHANGE_DETECTED)
847 shpchp_handle_presence_change(hp_slot, ctrl);
848
849 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
850 shpchp_handle_power_fault(hp_slot, ctrl);
851
852 /* Clear all slot events */
853 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
854 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
855 }
856 out:
857 if (!shpchp_poll_mode) {
858 /* Unmask Global Interrupt Mask */
859 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
860 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
861 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
862 }
863
864 return IRQ_HANDLED;
865}
866
867static int shpc_get_max_bus_speed(struct controller *ctrl)
868{
869 int retval = 0;
870 struct pci_bus *bus = ctrl->pci_dev->subordinate;
871 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
872 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
873 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
874 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
875
876 if (pi == 2) {
877 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
878 bus_speed = PCI_SPEED_133MHz_PCIX_533;
879 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
880 bus_speed = PCI_SPEED_100MHz_PCIX_533;
881 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
882 bus_speed = PCI_SPEED_66MHz_PCIX_533;
883 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
884 bus_speed = PCI_SPEED_133MHz_PCIX_266;
885 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
886 bus_speed = PCI_SPEED_100MHz_PCIX_266;
887 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
888 bus_speed = PCI_SPEED_66MHz_PCIX_266;
889 }
890
891 if (bus_speed == PCI_SPEED_UNKNOWN) {
892 if (slot_avail1 & SLOT_133MHZ_PCIX)
893 bus_speed = PCI_SPEED_133MHz_PCIX;
894 else if (slot_avail1 & SLOT_100MHZ_PCIX)
895 bus_speed = PCI_SPEED_100MHz_PCIX;
896 else if (slot_avail1 & SLOT_66MHZ_PCIX)
897 bus_speed = PCI_SPEED_66MHz_PCIX;
898 else if (slot_avail2 & SLOT_66MHZ)
899 bus_speed = PCI_SPEED_66MHz;
900 else if (slot_avail1 & SLOT_33MHZ)
901 bus_speed = PCI_SPEED_33MHz;
902 else
903 retval = -ENODEV;
904 }
905
906 bus->max_bus_speed = bus_speed;
907 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
908
909 return retval;
910}
911
912static struct hpc_ops shpchp_hpc_ops = {
913 .power_on_slot = hpc_power_on_slot,
914 .slot_enable = hpc_slot_enable,
915 .slot_disable = hpc_slot_disable,
916 .set_bus_speed_mode = hpc_set_bus_speed_mode,
917 .set_attention_status = hpc_set_attention_status,
918 .get_power_status = hpc_get_power_status,
919 .get_attention_status = hpc_get_attention_status,
920 .get_latch_status = hpc_get_latch_status,
921 .get_adapter_status = hpc_get_adapter_status,
922
923 .get_adapter_speed = hpc_get_adapter_speed,
924 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
925 .get_prog_int = hpc_get_prog_int,
926
927 .query_power_fault = hpc_query_power_fault,
928 .green_led_on = hpc_set_green_led_on,
929 .green_led_off = hpc_set_green_led_off,
930 .green_led_blink = hpc_set_green_led_blink,
931
932 .release_ctlr = hpc_release_ctlr,
933};
934
935int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
936{
937 int rc = -1, num_slots = 0;
938 u8 hp_slot;
939 u32 shpc_base_offset;
940 u32 tempdword, slot_reg, slot_config;
941 u8 i;
942
943 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
944 ctrl_dbg(ctrl, "Hotplug Controller:\n");
945
946 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
947 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
948 /* amd shpc driver doesn't use Base Offset; assume 0 */
949 ctrl->mmio_base = pci_resource_start(pdev, 0);
950 ctrl->mmio_size = pci_resource_len(pdev, 0);
951 } else {
952 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
953 if (!ctrl->cap_offset) {
954 ctrl_err(ctrl, "Cannot find PCI capability\n");
955 goto abort;
956 }
957 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
958
959 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
960 if (rc) {
961 ctrl_err(ctrl, "Cannot read base_offset\n");
962 goto abort;
963 }
964
965 rc = shpc_indirect_read(ctrl, 3, &tempdword);
966 if (rc) {
967 ctrl_err(ctrl, "Cannot read slot config\n");
968 goto abort;
969 }
970 num_slots = tempdword & SLOT_NUM;
971 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
972
973 for (i = 0; i < 9 + num_slots; i++) {
974 rc = shpc_indirect_read(ctrl, i, &tempdword);
975 if (rc) {
976 ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
977 i);
978 goto abort;
979 }
980 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
981 }
982
983 ctrl->mmio_base =
984 pci_resource_start(pdev, 0) + shpc_base_offset;
985 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
986 }
987
988 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
989 pdev->vendor, pdev->device, pdev->subsystem_vendor,
990 pdev->subsystem_device);
991
992 rc = pci_enable_device(pdev);
993 if (rc) {
994 ctrl_err(ctrl, "pci_enable_device failed\n");
995 goto abort;
996 }
997
998 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
999 ctrl_err(ctrl, "Cannot reserve MMIO region\n");
1000 rc = -1;
1001 goto abort;
1002 }
1003
1004 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1005 if (!ctrl->creg) {
1006 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
1007 ctrl->mmio_size, ctrl->mmio_base);
1008 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1009 rc = -1;
1010 goto abort;
1011 }
1012 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
1013
1014 mutex_init(&ctrl->crit_sect);
1015 mutex_init(&ctrl->cmd_lock);
1016
1017 /* Setup wait queue */
1018 init_waitqueue_head(&ctrl->queue);
1019
1020 ctrl->hpc_ops = &shpchp_hpc_ops;
1021
1022 /* Return PCI Controller Info */
1023 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1024 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1025 ctrl->num_slots = slot_config & SLOT_NUM;
1026 ctrl->first_slot = (slot_config & PSN) >> 16;
1027 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1028
1029 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1030 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1031 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1032 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1033 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1034 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1035 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1036 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1037 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1038
1039 /* Mask the MRL sensor SERR Mask of individual slot in
1040 * Slot SERR-INT Mask & clear all the existing event if any
1041 */
1042 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1043 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1044 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1045 hp_slot, slot_reg);
1046 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1047 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1048 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1049 CON_PFAULT_SERR_MASK);
1050 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1051 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1052 }
1053
1054 if (shpchp_poll_mode) {
1055 /* Install interrupt polling timer. Start with 10 sec delay */
1056 init_timer(&ctrl->poll_timer);
1057 start_int_poll_timer(ctrl, 10);
1058 } else {
1059 /* Installs the interrupt handler */
1060 rc = pci_enable_msi(pdev);
1061 if (rc) {
1062 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
1063 ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1064 }
1065
1066 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1067 MY_NAME, (void *)ctrl);
1068 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1069 ctrl->pci_dev->irq, rc);
1070 if (rc) {
1071 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1072 ctrl->pci_dev->irq);
1073 goto abort_iounmap;
1074 }
1075 }
1076 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1077
1078 shpc_get_max_bus_speed(ctrl);
1079 shpc_get_cur_bus_speed(ctrl);
1080
1081 /*
1082 * Unmask all event interrupts of all slots
1083 */
1084 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1085 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1086 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1087 hp_slot, slot_reg);
1088 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1089 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1090 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1091 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1092 }
1093 if (!shpchp_poll_mode) {
1094 /* Unmask all general input interrupts and SERR */
1095 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1096 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1097 SERR_INTR_RSVDZ_MASK);
1098 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1099 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1100 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1101 }
1102
1103 return 0;
1104
1105 /* We end up here for the many possible ways to fail this API. */
1106abort_iounmap:
1107 iounmap(ctrl->creg);
1108abort:
1109 return rc;
1110}