tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3188-cru.h>
19#include "rk3xxx.dtsi"
20
21/ {
22 compatible = "rockchip,rk3188";
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp";
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
33 reg = <0x0>;
34 };
35 cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 reg = <0x1>;
40 };
41 cpu@2 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
45 reg = <0x2>;
46 };
47 cpu@3 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x3>;
52 };
53 };
54
55 sram: sram@10080000 {
56 compatible = "mmio-sram";
57 reg = <0x10080000 0x8000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0x10080000 0x8000>;
61
62 smp-sram@0 {
63 compatible = "rockchip,rk3066-smp-sram";
64 reg = <0x0 0x50>;
65 };
66 };
67
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
72
73 #clock-cells = <1>;
74 #reset-cells = <1>;
75 };
76
77 pinctrl: pinctrl {
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
81
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
91
92 gpio-controller;
93 #gpio-cells = <2>;
94
95 interrupt-controller;
96 #interrupt-cells = <2>;
97 };
98
99 gpio1: gpio1@0x2003c000 {
100 compatible = "rockchip,gpio-bank";
101 reg = <0x2003c000 0x100>;
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cru PCLK_GPIO1>;
104
105 gpio-controller;
106 #gpio-cells = <2>;
107
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 };
111
112 gpio2: gpio2@2003e000 {
113 compatible = "rockchip,gpio-bank";
114 reg = <0x2003e000 0x100>;
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
117
118 gpio-controller;
119 #gpio-cells = <2>;
120
121 interrupt-controller;
122 #interrupt-cells = <2>;
123 };
124
125 gpio3: gpio3@20080000 {
126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
130
131 gpio-controller;
132 #gpio-cells = <2>;
133
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 };
137
138 pcfg_pull_up: pcfg_pull_up {
139 bias-pull-up;
140 };
141
142 pcfg_pull_down: pcfg_pull_down {
143 bias-pull-down;
144 };
145
146 pcfg_pull_none: pcfg_pull_none {
147 bias-disable;
148 };
149
150 i2c0 {
151 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
153 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
154 };
155 };
156
157 i2c1 {
158 i2c1_xfer: i2c1-xfer {
159 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
160 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
161 };
162 };
163
164 i2c2 {
165 i2c2_xfer: i2c2-xfer {
166 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
167 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
168 };
169 };
170
171 i2c3 {
172 i2c3_xfer: i2c3-xfer {
173 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
174 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
175 };
176 };
177
178 i2c4 {
179 i2c4_xfer: i2c4-xfer {
180 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
182 };
183 };
184
185 pwm0 {
186 pwm0_out: pwm0-out {
187 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
188 };
189 };
190
191 pwm1 {
192 pwm1_out: pwm1-out {
193 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
194 };
195 };
196
197 pwm2 {
198 pwm2_out: pwm2-out {
199 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 };
202
203 pwm3 {
204 pwm3_out: pwm3-out {
205 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
206 };
207 };
208
209 uart0 {
210 uart0_xfer: uart0-xfer {
211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
212 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
213 };
214
215 uart0_cts: uart0-cts {
216 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
217 };
218
219 uart0_rts: uart0-rts {
220 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
221 };
222 };
223
224 uart1 {
225 uart1_xfer: uart1-xfer {
226 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
227 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
228 };
229
230 uart1_cts: uart1-cts {
231 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
232 };
233
234 uart1_rts: uart1-rts {
235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
236 };
237 };
238
239 uart2 {
240 uart2_xfer: uart2-xfer {
241 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
242 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
243 };
244 /* no rts / cts for uart2 */
245 };
246
247 uart3 {
248 uart3_xfer: uart3-xfer {
249 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
250 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
251 };
252
253 uart3_cts: uart3-cts {
254 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
255 };
256
257 uart3_rts: uart3-rts {
258 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
259 };
260 };
261
262 sd0 {
263 sd0_clk: sd0-clk {
264 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
265 };
266
267 sd0_cmd: sd0-cmd {
268 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
269 };
270
271 sd0_cd: sd0-cd {
272 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
273 };
274
275 sd0_wp: sd0-wp {
276 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
277 };
278
279 sd0_pwr: sd0-pwr {
280 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
281 };
282
283 sd0_bus1: sd0-bus-width1 {
284 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
285 };
286
287 sd0_bus4: sd0-bus-width4 {
288 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
289 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
290 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
291 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
292 };
293 };
294
295 sd1 {
296 sd1_clk: sd1-clk {
297 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
298 };
299
300 sd1_cmd: sd1-cmd {
301 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
302 };
303
304 sd1_cd: sd1-cd {
305 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
306 };
307
308 sd1_wp: sd1-wp {
309 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
310 };
311
312 sd1_bus1: sd1-bus-width1 {
313 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
314 };
315
316 sd1_bus4: sd1-bus-width4 {
317 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
318 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
319 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
320 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
321 };
322 };
323 };
324};
325
326&global_timer {
327 interrupts = <GIC_PPI 11 0xf04>;
328};
329
330&local_timer {
331 interrupts = <GIC_PPI 13 0xf04>;
332};
333
334&i2c0 {
335 compatible = "rockchip,rk3188-i2c";
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c0_xfer>;
338};
339
340&i2c1 {
341 compatible = "rockchip,rk3188-i2c";
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c1_xfer>;
344};
345
346&i2c2 {
347 compatible = "rockchip,rk3188-i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c2_xfer>;
350};
351
352&i2c3 {
353 compatible = "rockchip,rk3188-i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
356};
357
358&i2c4 {
359 compatible = "rockchip,rk3188-i2c";
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_xfer>;
362};
363
364&pwm0 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&pwm0_out>;
367};
368
369&pwm1 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pwm1_out>;
372};
373
374&pwm2 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm2_out>;
377};
378
379&pwm3 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm3_out>;
382};
383
384&uart0 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>;
387};
388
389&uart1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&uart1_xfer>;
392};
393
394&uart2 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2_xfer>;
397};
398
399&uart3 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart3_xfer>;
402};
403
404&wdt {
405 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
406};