tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3066a-cru.h>
19#include "rk3xxx.dtsi"
20
21/ {
22 compatible = "rockchip,rk3066a";
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "rockchip,rk3066-smp";
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
33 reg = <0x0>;
34 };
35 cpu@1 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 reg = <0x1>;
40 };
41 };
42
43 sram: sram@10080000 {
44 compatible = "mmio-sram";
45 reg = <0x10080000 0x10000>;
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0 0x10080000 0x10000>;
49
50 smp-sram@0 {
51 compatible = "rockchip,rk3066-smp-sram";
52 reg = <0x0 0x50>;
53 };
54 };
55
56 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>;
59 rockchip,grf = <&grf>;
60
61 #clock-cells = <1>;
62 #reset-cells = <1>;
63 };
64
65 timer@2000e000 {
66 compatible = "snps,dw-apb-timer-osc";
67 reg = <0x2000e000 0x100>;
68 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
70 clock-names = "timer", "pclk";
71 };
72
73 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
78 clock-names = "timer", "pclk";
79 };
80
81 timer@2003a000 {
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
86 clock-names = "timer", "pclk";
87 };
88
89 pinctrl: pinctrl {
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 gpio0: gpio0@20034000 {
97 compatible = "rockchip,gpio-bank";
98 reg = <0x20034000 0x100>;
99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru PCLK_GPIO0>;
101
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 interrupt-controller;
106 #interrupt-cells = <2>;
107 };
108
109 gpio1: gpio1@2003c000 {
110 compatible = "rockchip,gpio-bank";
111 reg = <0x2003c000 0x100>;
112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&cru PCLK_GPIO1>;
114
115 gpio-controller;
116 #gpio-cells = <2>;
117
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 };
121
122 gpio2: gpio2@2003e000 {
123 compatible = "rockchip,gpio-bank";
124 reg = <0x2003e000 0x100>;
125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&cru PCLK_GPIO2>;
127
128 gpio-controller;
129 #gpio-cells = <2>;
130
131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpio3: gpio3@20080000 {
136 compatible = "rockchip,gpio-bank";
137 reg = <0x20080000 0x100>;
138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru PCLK_GPIO3>;
140
141 gpio-controller;
142 #gpio-cells = <2>;
143
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 };
147
148 gpio4: gpio4@20084000 {
149 compatible = "rockchip,gpio-bank";
150 reg = <0x20084000 0x100>;
151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&cru PCLK_GPIO4>;
153
154 gpio-controller;
155 #gpio-cells = <2>;
156
157 interrupt-controller;
158 #interrupt-cells = <2>;
159 };
160
161 gpio6: gpio6@2000a000 {
162 compatible = "rockchip,gpio-bank";
163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
166
167 gpio-controller;
168 #gpio-cells = <2>;
169
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 pcfg_pull_default: pcfg_pull_default {
175 bias-pull-pin-default;
176 };
177
178 pcfg_pull_none: pcfg_pull_none {
179 bias-disable;
180 };
181
182 i2c0 {
183 i2c0_xfer: i2c0-xfer {
184 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
185 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
186 };
187 };
188
189 i2c1 {
190 i2c1_xfer: i2c1-xfer {
191 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
192 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
193 };
194 };
195
196 i2c2 {
197 i2c2_xfer: i2c2-xfer {
198 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
199 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 };
202
203 i2c3 {
204 i2c3_xfer: i2c3-xfer {
205 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
206 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
207 };
208 };
209
210 i2c4 {
211 i2c4_xfer: i2c4-xfer {
212 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
213 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
214 };
215 };
216
217 pwm0 {
218 pwm0_out: pwm0-out {
219 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
220 };
221 };
222
223 pwm1 {
224 pwm1_out: pwm1-out {
225 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
226 };
227 };
228
229 pwm2 {
230 pwm2_out: pwm2-out {
231 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
232 };
233 };
234
235 pwm3 {
236 pwm3_out: pwm3-out {
237 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
238 };
239 };
240
241 uart0 {
242 uart0_xfer: uart0-xfer {
243 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
244 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
245 };
246
247 uart0_cts: uart0-cts {
248 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
249 };
250
251 uart0_rts: uart0-rts {
252 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
253 };
254 };
255
256 uart1 {
257 uart1_xfer: uart1-xfer {
258 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
260 };
261
262 uart1_cts: uart1-cts {
263 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
264 };
265
266 uart1_rts: uart1-rts {
267 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
268 };
269 };
270
271 uart2 {
272 uart2_xfer: uart2-xfer {
273 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
274 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
275 };
276 /* no rts / cts for uart2 */
277 };
278
279 uart3 {
280 uart3_xfer: uart3-xfer {
281 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
282 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
283 };
284
285 uart3_cts: uart3-cts {
286 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
287 };
288
289 uart3_rts: uart3-rts {
290 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
291 };
292 };
293
294 sd0 {
295 sd0_clk: sd0-clk {
296 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
297 };
298
299 sd0_cmd: sd0-cmd {
300 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
301 };
302
303 sd0_cd: sd0-cd {
304 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
305 };
306
307 sd0_wp: sd0-wp {
308 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
309 };
310
311 sd0_bus1: sd0-bus-width1 {
312 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
313 };
314
315 sd0_bus4: sd0-bus-width4 {
316 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
317 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
318 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
319 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
320 };
321 };
322
323 sd1 {
324 sd1_clk: sd1-clk {
325 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
326 };
327
328 sd1_cmd: sd1-cmd {
329 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
330 };
331
332 sd1_cd: sd1-cd {
333 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
334 };
335
336 sd1_wp: sd1-wp {
337 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
338 };
339
340 sd1_bus1: sd1-bus-width1 {
341 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
342 };
343
344 sd1_bus4: sd1-bus-width4 {
345 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
346 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
347 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
348 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
349 };
350 };
351 };
352};
353
354&i2c0 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c0_xfer>;
357};
358
359&i2c1 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c1_xfer>;
362};
363
364&i2c2 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c2_xfer>;
367};
368
369&i2c3 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c3_xfer>;
372};
373
374&i2c4 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c4_xfer>;
377};
378
379&mmc0 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
382};
383
384&mmc1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
387};
388
389&pwm0 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pwm0_out>;
392};
393
394&pwm1 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm1_out>;
397};
398
399&pwm2 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&pwm2_out>;
402};
403
404&pwm3 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm3_out>;
407};
408
409&uart0 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart0_xfer>;
412};
413
414&uart1 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart1_xfer>;
417};
418
419&uart2 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
422};
423
424&uart3 {
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart3_xfer>;
427};
428
429&wdt {
430 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
431};