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1/*
2 * Device Tree Include file for Marvell Armada XP family SoC
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 *
15 * Contains definitions specific to the Armada XP SoC that are not
16 * common to all Armada SoCs.
17 */
18
19#include "armada-370-xp.dtsi"
20
21/ {
22 model = "Marvell Armada XP family SoC";
23 compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25 aliases {
26 eth2 = ð2;
27 };
28
29 soc {
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
31
32 bootrom {
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
35 };
36
37 internal-regs {
38 L2: l2-cache {
39 compatible = "marvell,aurora-system-cache";
40 reg = <0x08000 0x1000>;
41 cache-id-part = <0x100>;
42 wt-override;
43 };
44
45 i2c0: i2c@11000 {
46 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
47 reg = <0x11000 0x100>;
48 };
49
50 i2c1: i2c@11100 {
51 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
52 reg = <0x11100 0x100>;
53 };
54
55 serial@12200 {
56 compatible = "snps,dw-apb-uart";
57 reg = <0x12200 0x100>;
58 reg-shift = <2>;
59 interrupts = <43>;
60 reg-io-width = <1>;
61 clocks = <&coreclk 0>;
62 status = "disabled";
63 };
64 serial@12300 {
65 compatible = "snps,dw-apb-uart";
66 reg = <0x12300 0x100>;
67 reg-shift = <2>;
68 interrupts = <44>;
69 reg-io-width = <1>;
70 clocks = <&coreclk 0>;
71 status = "disabled";
72 };
73
74 system-controller@18200 {
75 compatible = "marvell,armada-370-xp-system-controller";
76 reg = <0x18200 0x500>;
77 };
78
79 gateclk: clock-gating-control@18220 {
80 compatible = "marvell,armada-xp-gating-clock";
81 reg = <0x18220 0x4>;
82 clocks = <&coreclk 0>;
83 #clock-cells = <1>;
84 };
85
86 coreclk: mvebu-sar@18230 {
87 compatible = "marvell,armada-xp-core-clock";
88 reg = <0x18230 0x08>;
89 #clock-cells = <1>;
90 };
91
92 thermal@182b0 {
93 compatible = "marvell,armadaxp-thermal";
94 reg = <0x182b0 0x4
95 0x184d0 0x4>;
96 status = "okay";
97 };
98
99 cpuclk: clock-complex@18700 {
100 #clock-cells = <1>;
101 compatible = "marvell,armada-xp-cpu-clock";
102 reg = <0x18700 0xA0>, <0x1c054 0x10>;
103 clocks = <&coreclk 1>;
104 };
105
106 interrupt-controller@20000 {
107 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
108 };
109
110 timer@20300 {
111 compatible = "marvell,armada-xp-timer";
112 clocks = <&coreclk 2>, <&refclk>;
113 clock-names = "nbclk", "fixed";
114 };
115
116 watchdog@20300 {
117 compatible = "marvell,armada-xp-wdt";
118 clocks = <&coreclk 2>, <&refclk>;
119 clock-names = "nbclk", "fixed";
120 };
121
122 cpurst@20800 {
123 compatible = "marvell,armada-370-cpu-reset";
124 reg = <0x20800 0x20>;
125 };
126
127 eth2: ethernet@30000 {
128 compatible = "marvell,armada-370-neta";
129 reg = <0x30000 0x4000>;
130 interrupts = <12>;
131 clocks = <&gateclk 2>;
132 status = "disabled";
133 };
134
135 usb@50000 {
136 clocks = <&gateclk 18>;
137 };
138
139 usb@51000 {
140 clocks = <&gateclk 19>;
141 };
142
143 usb@52000 {
144 compatible = "marvell,orion-ehci";
145 reg = <0x52000 0x500>;
146 interrupts = <47>;
147 clocks = <&gateclk 20>;
148 status = "disabled";
149 };
150
151 xor@60900 {
152 compatible = "marvell,orion-xor";
153 reg = <0x60900 0x100
154 0x60b00 0x100>;
155 clocks = <&gateclk 22>;
156 status = "okay";
157
158 xor10 {
159 interrupts = <51>;
160 dmacap,memcpy;
161 dmacap,xor;
162 };
163 xor11 {
164 interrupts = <52>;
165 dmacap,memcpy;
166 dmacap,xor;
167 dmacap,memset;
168 };
169 };
170
171 xor@f0900 {
172 compatible = "marvell,orion-xor";
173 reg = <0xF0900 0x100
174 0xF0B00 0x100>;
175 clocks = <&gateclk 28>;
176 status = "okay";
177
178 xor00 {
179 interrupts = <94>;
180 dmacap,memcpy;
181 dmacap,xor;
182 };
183 xor01 {
184 interrupts = <95>;
185 dmacap,memcpy;
186 dmacap,xor;
187 dmacap,memset;
188 };
189 };
190 };
191 };
192
193 clocks {
194 /* 25 MHz reference crystal */
195 refclk: oscillator {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <25000000>;
199 };
200 };
201};